Datasheet
Table Of Contents
- Features
- CMOS Technology
- Packages
- Package Types
- Block Diagram
- 1.0 Device OvervieW
- 1.1 Pin Descriptions
- 1.2 Power-on Reset (POR)
- 1.3 Power-up Timer (PWRT)
- 1.4 Clock Generator
- 1.5 I2C Bus Interface/ Protocol Handler
- 1.6 Address Decoder
- 1.7 Register Block
- 1.8 Serializer/Deserializer
- 1.9 Interrupt Logic
- 2.0 Electrical Characteristics
- 2.1 DC Characteristics
- TABLE 2-1: DC Characteristics
- FIGURE 2-1: respOnse time
- TABLE 2-2: response time
- FIGURE 2-2: TEST POINT Clock Timing
- TABLE 2-3: TEST POINT Clock Timing
- TABLE 2-4: Power-up Timer Requirements
- FIGURE 2-3: I2C Bus Start/Stop Bits Timing
- FIGURE 2-4: I2C Bus Data Timing
- TABLE 2-5: I2C Bus Data Requirements
- FIGURE 2-5: GP0 and GP1 POrt Timings
- 2.1 DC Characteristics
- 3.0 Package InFormation
- Appendix A: Revision History
- Product Identification System
- Worldwide Sales and Service
MCP23016
DS20090C-page 20 © 2007 Microchip Technology Inc.
2.1 DC Characteristics
TABLE 2-1: DC CHARACTERISTICS
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature: -40°C ≤ T
A ≤ +85°C for industrial
Param
No.
Characteristic Sym Min Typ† Max Units Conditions
D001 Supply Voltage V
DD 2.0 — 5.5 V
D002 Standby Current IDD — 0.4 mA IARES = 1
D003 Standby Current I
PD — 25 µA IARES = 0
Input Low Voltage
I/O ports VIL
D004 TTL buffer Vss — 0.15 VDD V For entire VDD range
D004A Vss — 0.8V 4.5V ≤ VDD ≤ 5.5V
D005 Schmitt Trigger buffer Vss — 0.2 VDD V
Input High Voltage
I/O ports V
IH —
D006 TTL buffer 2.0 — VDD V4.5V ≤ VDD ≤ 5.5V
D006A 0.25 V
DD
+ 0.8V
—VDD V For entire VDD range
D007 Schmitt Trigger buffer 0.8 V
DD —VDD V For entire VDD range
Input Leakage Current
D008 I/O ports I
IL ——±1.0 µA Vss ≤ VPIN ≤ VDD,
Pin at hi-impedance
D009 CLK — — ±5.0 µA Vss ≤ V
PIN ≤ VDD
Output Low Voltage
D010 I/O Ports VOL ——0.6VIOL = 8.5 mA, VDD = 4.5V
Output High Voltage
D010 I/O Ports V
OH VDD-0.7 — — V IOH = 3.0 mA, VDD = 4.5V
D011 VDD start voltage to ensure
internal POR signal
VPOR —Vss— V
D012 V
DD rise rate to ensure
internal POR signal
SVDD 0.05 - — V/ms Note 1
DC Trip Point V
TPOR 1.5 1.7 1.9 V DC Slow Ramp
D012 VDD rise rate to ensure
internal POR signal with
PWRT enabled
SVDD 0.05 — — V/ms Note 1
DC Current Draw IPOR — 5.0 — µA At 5.0V (1 µ/Volt typical)
Note 1: These parameters are characterized but not tested.
2: Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
3: Standby current is measured with all I/O in hi-impedance state and tied to V
DD and VSS.
4: For RC CLK, current through R
EXT is not included. The current through the resistor can be estimated by
the formula
Ir = VDD/2 REXT (mA) with REXT in kohm.
5: Negative current is defined as coming out of the pin.