MCP23017/MCP23S17 16-Bit I/O Expander with Serial Interface MCP23017 GPA7 GPA6 GPA5 GPA4 GPA3 GPA2 GPA1 GPA0 INTA INTB RESET A2 A1 A0 GPB3 GPB2 GPB1 GPB0 GPA7 GPA6 GPA5 GPB4 GPB5 GPB6 GPB7 VDD VSS NC 1 2 3 4 5 6 7 28 27 26 25 24 23 22 21 20 19 MCP23017 18 17 16 15 8 9 10 11 121314 •1 2 3 4 5 6 7 8 9 10 11 12 13 14 GPA4 GPA3 GPA2 GPA1 GPA0 INTA INTB 28 27 26 25 24 23 22 21 20 19 18 17 16 15 GPA7 GPA6 GPA5 GPA4 GPA3 GPA2 GPA1 GPA0 INTA INTB RESET A2 A1 A0 GPB3 GPB2 GPB1 GPB0 GPA7 GPA6 GPA5 GPB0 GPB
MCP23017/MCP23S17 Functional Block Diagram MCP23S17 CS SCK SI SO SPI MCP23017 SCL SDA I2C™ 3 A2:A0 Decode RESET INTA INTB GPIO GPB7 GPB6 GPB5 GPB4 GPB3 GPB2 GPB1 GPB0 GPIO GPA7 GPA6 GPA5 GPA4 GPA3 GPA2 GPA1 GPA0 Serializer/ Deserializer Control 16 Interrupt Logic 8 Configuration/ Control Registers DS21952B-page 2 © 2007 Microchip Technology Inc.
MCP23017/MCP23S17 1.0 DEVICE OVERVIEW The MCP23017/MCP23S17 (MCP23X17) device family provides 16-bit, general purpose parallel I/O expansion for I2C bus or SPI applications. The two devices differ only in the serial interface. • MCP23017 – I2C interface • MCP23S17 – SPI interface The MCP23X17 consists of multiple 8-bit configuration registers for input, output and polarity selection. The system master can enable the I/Os as either inputs or outputs by writing the I/O configuration bits (IODIRA/B).
MCP23017/MCP23S17 1.1 Pin Descriptions TABLE 1-1: PINOUT DESCRIPTION PDIP/ SOIC/ SSOP QFN Pin Type GPB0 1 25 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor. GPB1 2 26 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor. GPB2 3 27 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor. GPB3 4 28 I/O Bidirectional I/O pin.
MCP23017/MCP23S17 1.2 Power-on Reset (POR) 1.3.1 The on-chip POR circuit holds the device in reset until VDD has reached a high enough voltage to deactivate the POR circuit (i.e., release the device from reset). The maximum VDD rise time is specified in Section 2.0 “Electrical Characteristics”. When the device exits the POR condition (releases reset), device operating parameters (i.e., voltage, temperature, serial bus frequency, etc.) must be met to ensure proper operation. 1.
MCP23017/MCP23S17 1.3.2.2 I2C Read Operation 2 I C Read operations include the control byte sequence, as shown in the bottom of Figure 1-1. This sequence is followed by another control byte (including the Start condition and ACK) with the R/W bit set (R/W = 1). The MCP23017 then transmits the data contained in the addressed register. The sequence is ended with the master generating a Stop or Restart condition. 1.3.2.
MCP23017/MCP23S17 MCP23017 I2C™ DEVICE PROTOCOL FIGURE 1-1: S - Start SR - Restart S OP DIN W ADDR DIN .... P P - Stop w - Write SR OP R DOUT .... DOUT P SR OP W DIN DIN P R - Read OP - Device opcode ADDR - Device register address DOUT - Data out from MCP23017 DIN .... P - Data in to MCP23017 OP S DOUT R SR SR OP W OP DOUT .... R ADDR P DOUT .... DOUT P DIN ....
MCP23017/MCP23S17 1.4 Hardware Address Decoder The hardware address pins are used to determine the device address. To address a device, the corresponding address bits in the control byte must match the pin state. The pins must be biased externally. Control Byte S ADDRESSING I2C DEVICES (MCP23017) 1.4.1 0 0 A2 A1 A0 R/W ACK R/W bit ACK bit R/W = 0 = write R/W = 1 = read FIGURE 1-3: SPI CONTROL BYTE FORMAT CS The MCP23S17 is a slave SPI device.
MCP23017/MCP23S17 1.5 GPIO Port Reading the GPIOn register reads the value on the port. Reading the OLATn register only reads the latches, not the actual value on the port. The GPIO module is a general purpose, 16-bit wide, bidirectional port that is functionally split into two 8-bit wide ports. Writing to the GPIOn register actually causes a write to the latches (OLATn). Writing to the OLATn register forces the associated output drivers to drive to the level in OLATn.
MCP23017/MCP23S17 1.6 Configuration and Control Registers are associated with PortB. One register (IOCON) is shared between the two ports. The PortA registers are identical to the PortB registers, therefore, they will be referred to without differentiating between the port designation (i.e., they will not have the “A” or “B” designator assigned) in the register tables. There are 21 registers associated with the MCP23X17, as shown in Table 1-5 and Table 1-6.
MCP23017/MCP23S17 TABLE 1-6: CONTROL REGISTER SUMMARY (IOCON.
MCP23017/MCP23S17 1.6.1 I/O DIRECTION REGISTER Controls the direction of the data I/O. When a bit is set, the corresponding pin becomes an input. When a bit is clear, the corresponding pin becomes an output.
MCP23017/MCP23S17 1.6.2 INPUT POLARITY REGISTER This register allows the user to configure the polarity on the corresponding GPIO port bits. If a bit is set, the corresponding GPIO register bit will reflect the inverted value on the pin.
MCP23017/MCP23S17 1.6.3 INTERRUPT-ON-CHANGE CONTROL REGISTER The GPINTEN register controls the interrupt-onchange feature for each pin. If a bit is set, the corresponding pin is enabled for interrupt-on-change. The DEFVAL and INTCON registers must also be configured if any pins are enabled for interrupt-on-change.
MCP23017/MCP23S17 1.6.4 DEFAULT COMPARE REGISTER FOR INTERRUPT-ON-CHANGE The default comparison value is configured in the DEFVAL register. If enabled (via GPINTEN and INTCON) to compare against the DEFVAL register, an opposite value on the associated pin will cause an interrupt to occur.
MCP23017/MCP23S17 1.6.5 INTERRUPT CONTROL REGISTER The INTCON register controls how the associated pin value is compared for the interrupt-on-change feature. If a bit is set, the corresponding I/O pin is compared against the associated bit in the DEFVAL register. If a bit value is clear, the corresponding I/O pin is compared against the previous value.
MCP23017/MCP23S17 1.6.6 CONFIGURATION REGISTER The IOCON register configuring the device: contains several bits for The BANK bit changes how the registers are mapped (see Table 1-5 and Table 1-6 for more details). • If BANK = 1, the registers associated with each port are segregated. Registers associated with PORTA are mapped from address 00h - 0Ah and registers associated with PORTB are mapped from 10h - 1Ah. • If BANK = 0, the A/B registers are paired.
MCP23017/MCP23S17 REGISTER 1-6: IOCON – I/O EXPANDER CONFIGURATION REGISTER (ADDR 0x05) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 BANK MIRROR SEQOP DISSLW HAEN ODR INTPOL — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 BANK: Controls how the registers are addressed 1 = The registers associated with each port are separated into different banks 0 = The reg
MCP23017/MCP23S17 1.6.7 PULL-UP RESISTOR CONFIGURATION REGISTER The GPPU register controls the pull-up resistors for the port pins. If a bit is set and the corresponding pin is configured as an input, the corresponding port pin is internally pulled up with a 100 kΩ resistor.
MCP23017/MCP23S17 1.6.8 INTERRUPT FLAG REGISTER The INTF register reflects the interrupt condition on the port pins of any pin that is enabled for interrupts via the GPINTEN register. A ‘set’ bit indicates that the associated pin caused the interrupt. This register is ‘read-only’. Writes to this register will be ignored.
MCP23017/MCP23S17 1.6.9 INTERRUPT CAPTURE REGISTER The INTCAP register captures the GPIO port value at the time the interrupt occurred. The register is ‘read only’ and is updated only when an interrupt occurs. The register will remain unchanged until the interrupt is cleared via a read of INTCAP or GPIO.
MCP23017/MCP23S17 1.6.10 PORT REGISTER The GPIO register reflects the value on the port. Reading from this register reads the port. Writing to this register modifies the Output Latch (OLAT) register.
MCP23017/MCP23S17 1.6.11 OUTPUT LATCH REGISTER (OLAT) The OLAT register provides access to the output latches. A read from this register results in a read of the OLAT and not the port itself. A write to this register modifies the output latches that modifies the pins configured as outputs.
MCP23017/MCP23S17 1.7 Interrupt Logic 1.7.2 If enabled, the MCP23X17 activates the INTn interrupt output when one of the port pins changes state or when a pin does not match the preconfigured default. Each pin is individually configurable as follows: • Enable/disable interrupt via GPINTEN • Can interrupt on either pin change or change from default as configured in DEFVAL Both conditions are referred to as Interrupt-on-Change (IOC). The interrupt control module uses the following registers/bits: • IOCON.
MCP23017/MCP23S17 1.7.5 INTERRUPT CONDITIONS FIGURE 1-7: INTERRUPT-ON-CHANGE FROM REGISTER DEFAULT There are two possible configurations that cause interrupts (configured via INTCON): 1. 2. Pins configured for interrupt-on-pin change will cause an interrupt to occur if a pin changes to the opposite state. The default state is reset after an interrupt occurs and after clearing the interrupt condition (i.e., after reading GPIO or INTCAP).
MCP23017/MCP23S17 NOTES: DS21952B-page 26 © 2007 Microchip Technology Inc.
MCP23017/MCP23S17 2.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings † Ambient temperature under bias............................................................................................................. -40°C to +125°C Storage temperature ............................................................................................................................... -65°C to +150°C Voltage on VDD with respect to VSS ...............................................................................
MCP23017/MCP23S17 2.1 DC Characteristics DC Characteristics Param No. Operating Conditions (unless otherwise indicated): 1.8V ≤ VDD ≤ 5.5V at -40°C ≤ TA ≤ +85°C (I-Temp) 4.5V ≤ VDD ≤ 5.5V at -40°C ≤ TA ≤ +125°C (E-Temp) (Note 1) Characteristic Sym Min Typ (Note 1( Max Units Conditions D001 Supply Voltage VDD 1.8 — 5.5 V D002 VDD Start Voltage to Ensure Power-on Reset VPOR — VSS — V D003 VDD Rise Rate to Ensure Power-on Reset SVDD 0.
MCP23017/MCP23S17 FIGURE 2-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS VDD Pin 1 kΩ SCL and SDA pin MCP23017 50 pF 135 pF FIGURE 2-2: RESET AND DEVICE RESET TIMER TIMING VDD RESET 30 32 Internal RESET 34 Output pin © 2007 Microchip Technology Inc.
MCP23017/MCP23S17 TABLE 2-1: DEVICE RESET SPECIFICATIONS Operating Conditions (unless otherwise indicated): 1.8V ≤ VDD ≤ 5.5V at -40°C ≤ TA ≤ +85°C (I-Temp) 4.5V ≤ VDD ≤ 5.5V at -40°C ≤ TA ≤ +125°C (E-Temp) (Note 1) AC Characteristics Param No. Characteristic Sym Min Typ(1) Max Units 30 RESET Pulse Width (Low) TRSTL 1 — — µs 32 Device Active After Reset high THLD — 0 — ns 34 Output High-Impedance From RESET Low TIOZ — — 1 µs Note 1: Conditions VDD = 5.
MCP23017/MCP23S17 TABLE 2-2: I2C™ BUS DATA REQUIREMENTS 2 I C™ AC Characteristics Param No. 100 Characteristic Operating Conditions (unless otherwise indicated): 1.8V ≤ VDD ≤ 5.5V at -40°C ≤ TA ≤ +85°C (I-Temp) 4.5V ≤ VDD ≤ 5.5V at -40°C ≤ TA ≤ +125°C (E-Temp) (Note 1) RPU (SCL, SDA) = 1 kΩ, CL (SCL, SDA) = 135 pF Min Typ 100 kHz mode 4.0 — — µs 1.8V–5.5V (I-Temp) 400 kHz mode 0.6 — — µs 2.7V–5.5V (I-Temp) 0.12 — — µs 4.5V–5.5V (E-Temp) 4.7 — — µs 1.8V–5.
MCP23017/MCP23S17 I2C™ BUS DATA REQUIREMENTS (CONTINUED) TABLE 2-2: Operating Conditions (unless otherwise indicated): 1.8V ≤ VDD ≤ 5.5V at -40°C ≤ TA ≤ +85°C (I-Temp) 4.5V ≤ VDD ≤ 5.5V at -40°C ≤ TA ≤ +125°C (E-Temp) (Note 1) RPU (SCL, SDA) = 1 kΩ, CL (SCL, SDA) = 135 pF 2 I C™ AC Characteristics Param No. Characteristic 109 Sym Output Valid From Clock: — — Max Units Conditions 3.45 µs 1.8V–5.5V (I-Temp) 400 kHz mode — — 0.9 µs 2.7V–5.5V (I-Temp) 1.7 MHz mode — — 0.18 µs 4.5V–5.
MCP23017/MCP23S17 FIGURE 2-6: SPI OUTPUT TIMING CS 8 SCK 2 9 Mode 1,1 Mode 0,0 12 SO MSB out LSB out Don’t Care SI TABLE 2-3: SPI INTERFACE AC CHARACTERISTICS SPI Interface AC Characteristics Param No. 14 13 Characteristic Clock Frequency Operating Conditions (unless otherwise indicated): 1.8V ≤ VDD ≤ 5.5V at -40°C ≤ TA ≤ +85°C (I-Temp) 4.5V ≤ VDD ≤ 5.5V at -40°C ≤ TA ≤ +125°C (E-Temp) (Note 1) Sym Min Typ Max Units Conditions FCLK — — 5 MHz 1.8V–5.5V (I-Temp) — — 10 MHz 2.
MCP23017/MCP23S17 TABLE 2-3: SPI INTERFACE AC CHARACTERISTICS (CONTINUED) SPI Interface AC Characteristics Param No. 9 Characteristic Clock Low Time Operating Conditions (unless otherwise indicated): 1.8V ≤ VDD ≤ 5.5V at -40°C ≤ TA ≤ +85°C (I-Temp) 4.5V ≤ VDD ≤ 5.5V at -40°C ≤ TA ≤ +125°C (E-Temp) (Note 1) Sym Min Typ Max Units TLO 90 — — ns Conditions 1.8V–5.5V (I-Temp) 45 — — ns 2.7V–5.5V (I-Temp) 45 — — ns 4.5V–5.
MCP23017/MCP23S17 TABLE 2-4: GP AND INT PINS AC Characteristics Operating Conditions (unless otherwise indicated): 1.8V ≤ VDD ≤ 5.5V at -40°C ≤ TA ≤ +85°C (I-Temp) 4.5V ≤ VDD ≤ 5.5V at -40°C ≤ TA ≤ +125°C (E-Temp) (Note 1) Param No.
MCP23017/MCP23S17 NOTES: DS21952B-page 36 © 2007 Microchip Technology Inc.
MCP23017/MCP23S17 3.0 PACKAGING INFORMATION 3.1 Package Marking Information 28-Lead PDIP (Skinny DIP) Example: XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNN 28-Lead QFN e3 MCP23017-E/SP^^ 0648256 Example: XXXXXXXX XXXXXXXX YYWWNNN 23017 e3 E/ML^^ 0648256 28-Lead SOIC Example: XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX e3 MCP23017-E/SO^^ 0648256 YYWWNNN Example: 28-Lead SSOP XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN Legend: XX...
MCP23017/MCP23S17 28-Lead Skinny Plastic Dual In-Line (SP) – 300 mil Body [SPDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N NOTE 1 E1 1 2 3 D E A2 A L c b1 A1 b e eB Units Dimension Limits Number of Pins INCHES MIN N NOM MAX 28 Pitch e Top to Seating Plane A – – .200 Molded Package Thickness A2 .120 .135 .150 Base to Seating Plane A1 .
MCP23017/MCP23S17 28-Lead Plastic Quad Flat, No Lead Package (ML) – 6x6 mm Body [QFN] with 0.55 mm Contact Length Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D2 EXPOSED PAD e E b E2 2 2 1 1 N K N NOTE 1 L BOTTOM VIEW TOP VIEW A A3 A1 Units Dimension Limits Number of Pins MILLIMETERS MIN N NOM MAX 28 Pitch e Overall Height A 0.80 0.65 BSC 0.90 1.00 Standoff A1 0.00 0.02 0.
MCP23017/MCP23S17 28-Lead Plastic Small Outline (SO) – Wide, 7.50 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 NOTE 1 1 2 3 b e h α A2 A h c φ L A1 Units Dimension Limits Number of Pins β L1 MILLMETERS MIN N NOM MAX 28 Pitch e Overall Height A – 1.27 BSC – Molded Package Thickness A2 2.05 – – Standoff § A1 0.10 – 0.
MCP23017/MCP23S17 28-Lead Plastic Shrink Small Outline (SS) – 5.30 mm Body [SSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 1 2 NOTE 1 b e c A2 A φ A1 L L1 Units Dimension Limits Number of Pins MILLIMETERS MIN N NOM MAX 28 Pitch e Overall Height A – 0.65 BSC – 2.00 Molded Package Thickness A2 1.65 1.75 1.85 Standoff A1 0.05 – – Overall Width E 7.40 7.80 8.
MCP23017/MCP23S17 NOTES: DS21952B-page 42 © 2007 Microchip Technology Inc.
MCP23017/MCP23S17 APPENDIX A: REVISION HISTORY Revision B (February 2007) 1. 2. 3. 4. Changed Byte and Sequential Read in Figure 1-1 from “R” to “W”. Table 2-4, Param No. 51 and 53: Changed from 450 to 600 and 500 to 600, respecively. Added disclaimers to package outline drawings. Updated package outline drawings. Revision A (June 2005) • Original Release of this Document. © 2007 Microchip Technology Inc.
MCP23017/MCP23S17 NOTES: DS21952B-page 40 © 2007 Microchip Technology Inc.
MCP23017/MCP23S17 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO.
MCP23017/MCP23S17 NOTES: DS21952B-page 42 © 2007 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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