Datasheet

© 2007 Microchip Technology Inc. DS21952B-page 5
MCP23017/MCP23S17
1.2 Power-on Reset (POR)
The on-chip POR circuit holds the device in reset until
V
DD has reached a high enough voltage to deactivate
the POR circuit (i.e., release the device from reset).
The maximum VDD rise time is specified in Section 2.0
“Electrical Characteristics”.
When the device exits the POR condition (releases
reset), device operating parameters (i.e., voltage,
temperature, serial bus frequency, etc.) must be met to
ensure proper operation.
1.3 Serial Interface
This block handles the functionality of the I
2
C
(MCP23017) or SPI (MCP23S17) interface protocol.
The MCP23X17 contains 22 individual registers (11
register pairs) that can be addressed through the Serial
Interface block, as shown in Table 1-2.
TABLE 1-2: REGISTER ADDRESSES
1.3.1 BYTE MODE AND SEQUENTIAL
MODE
The MCP23X17 family has the ability to operate in Byte
mode or Sequential mode (IOCON.SEQOP).
Byte Mode disables automatic Address Pointer
incrementing. When operating in Byte mode, the
MCP23X17 family does not increment its internal
address counter after each byte during the data
transfer. This gives the ability to continually access the
same address by providing extra clocks (without
additional control bytes). This is useful for polling the
GPIO register for data changes or for continually
writing to the output latches.
A special mode (Byte mode with IOCON.BANK = 0)
causes the address pointer to toggle between
associated A/B register pairs. For example, if the BANK
bit is cleared and the Address Pointer is initially set to
address 12h (GPIOA) or 13h (GPIOB), the pointer will
toggle between GPIOA and GPIOB. Note that the
Address Pointer can initially point to either address in
the register pair.
Sequential mode enables automatic address pointer
incrementing. When operating in Sequential mode, the
MCP23X17 family increments its address counter after
each byte during the data transfer. The Address Pointer
automatically rolls over to address 00h after accessing
the last register.
These two modes are not to be confused with single
writes/reads and continuous writes/reads that are
serial protocol sequences. For example, the device
may be configured for Byte mode and the master may
perform a continuous read. In this case, the
MCP23X17 would not increment the Address Pointer
and would repeatedly drive data from the same
location.
1.3.2 I
2
C INTERFACE
1.3.2.1 I
2
C Write Operation
The I
2
C write operation includes the control byte and
register address sequence, as shown in the bottom of
Figure 1-1. This sequence is followed by eight bits of
data from the master and an Acknowledge (ACK) from
the MCP23017. The operation is ended with a Stop (P)
or Restart (SR) condition being generated by the
master.
Data is written to the MCP23017 after every byte
transfer. If a Stop or Restart condition is generated
during a data transfer, the data will not be written to the
MCP23017.
Both “byte writes” and “sequential writes” are
supported by the MCP23017. If Sequential mode is
enabled (IOCON, SEQOP = 0) (default), the
MCP23017 increments its address counter after each
ACK during the data transfer.
Address
IOCON.BANK = 1
Address
IOCON.BANK = 0
Access to:
00h 00h IODIRA
10h 01h IODIRB
01h 02h IPOLA
11h 03h IPOLB
02h 04h GPINTENA
12h 05h GPINTENB
03h 06h DEFVALA
13h 07h DEFVALB
04h 08h INTCONA
14h 09h INTCONB
05h 0Ah IOCON
15h 0Bh IOCON
06h 0Ch GPPUA
16h 0Dh GPPUB
07h 0Eh INTFA
17h 0Fh INTFB
08h 10h INTCAPA
18h 11h INTCAPB
09h 12h GPIOA
19h 13h GPIOB
0Ah 14h OLATA
1Ah 15h OLATB