Datasheet

MCP23018/MCP23S18

1.6.4 DEFAULT COMPARE REGISTER

FOR INTERRUPT-ON-CHANGE

The default comparison value is configured in the

DEFVAL register. If enabled (via GPINTEN and INT-

CON) to compare against the DEFVAL register, an

opposite value on the associated pin will cause an

interrupt to occur.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

DEF7 DEF6 DEF5 DEF4 DEF3 DEF2 DEF1 DEF0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 DEF7:DEF0: Sets the compare value for pins configured for interrupt-on-change from defaults <7:0>.

Refer to INTCON.

If the associated pin level is the opposite from the register bit, an interrupt occurs.

Refer to INTCON and GPINTEN.