Datasheet

MCP23018/MCP23S18

R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0

BANK MIRROR

SEQOP

- - ODR INTPOL INTCC

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 BANK: Controls how the registers are addressed (see Figure 1-4 and Figure 1-5)

1 = The registers associated with each port are separated into different banks

0 = The registers are in the same bank (addresses are sequential)

bit 6 MIRROR: INT pins mirror bit

1 = The INT pins are internally connected in a wired OR configuration

0 = The INT pins are not connected. INTA is associated with Port A and INTB is associated with Port B

bit 5 SEQOP: Sequential Operation mode bit.

1 = Sequential operation disabled, address pointer does not increment.

0 = Sequential operation enabled, address pointer increments.

bit 4 Unimplemented: Reads as 0

bit 3 Unimplemented: Reads as 0

bit 2 ODR: Configures the INT pin as an open-drain output.

1 = Open-drain output (overrides the INTPOL bit).

0 = Active driver output (INTPOL bit sets the polarity).

bit 1 INTPOL: Sets the polarity of the INT output pin.

1 = Active-high.

0 = Active-low.

bit 0 INTCC: Interrupt Clearing Control

1 = Reading INTCAP register clears the interrupt

0 = Reading GPIO register clears the interrupt