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MCP3004/3008

Features

• 10-bit resolution

• ± 1 LSB max DNL

• ± 1 LSB max INL

• 4 (MCP3004) or 8 (MCP3008) input channels

• Analog inputs programmable as single-ended or

pseudo-differential pairs

• On-chip sample and hold

• SPI serial interface (modes 0,0 and 1,1)

• Single supply operation: 2.7V - 5.5V

• 200 ksps max. sampling rate at V

=5V

• 75 ksps max. sampling rate at V

=2.7V

• Low power CMOS technology

• 5 nA typical standby current, 2 µA max.

• 500 µA max. active current at 5V

• Industrial temp range: -40°C to +85°C

• Available in PDIP, SOIC and TSSOP packages

Applications

• Sensor Interface

• Process Control

• Data Acquisition

• Battery Operated Systems

Functional Block Diagram

Description

The Microchip Technology Inc. MCP3004/3008

devices are successive approximation 10-bit Analog-

to-Digital (A/D) converters with on-board sample and

hold circuitry. The MCP3004 is programmable to

provide two pseudo-differential input pairs or four

single-ended inputs. The MCP3008 is programmable

to provide four pseudo-differential input pairs or eight

single-ended inputs. Differential Nonlinearity (DNL)

and Integral Nonlinearity (INL) are specified at ±1 LSB.

Communication with the devices is accomplished using

a simple serial interface compatible with the SPI

protocol. The devices are capable of conversion rates

of up to 200 ksps. The MCP3004/3008 devices operate

over a broad voltage range (2.7V - 5.5V). Low-current

design permits operation with typical standby currents

of only 5 nA and typical active currents of 320 µA. The

MCP3004 is offered in 14-pin PDIP, 150 mil SOIC and

TSSOP packages, while the MCP3008 is offered in 16-

pin PDIP and SOIC packages.

Package Types

Comparator

Sample

and

Hold

10-Bit SAR

DAC

Control Logic

CS/SHDN

REF

CLK

OUT

Shift

CH0

Channel

Max

Input

CH1

CH7*

* Note: Channels 4-7 are available on MCP3008 Only

CLK

OUT

MCP3004

REF

CH0

CH1

CH2

CH3

/SHDN

DGND

AGND

CLK

OUT

MCP3008

REF

CS/SHDN

DGND

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

AGND

PDIP, SOIC, TSSOP

PDIP, SOIC

2.7V 4-Channel/8-Channel 10-Bit A/D Converters

with SPI Serial Interface

Summary of content (40 pages)

PAGE 1
MCP3004/3008 2.7V 4-Channel/8-Channel 10-Bit A/D Converters with SPI Serial Interface Features Description • • • • • The Microchip Technology Inc. MCP3004/3008 devices are successive approximation 10-bit Analogto-Digital (A/D) converters with on-board sample and hold circuitry. The MCP3004 is programmable to provide two pseudo-differential input pairs or four single-ended inputs. The MCP3008 is programmable to provide four pseudo-differential input pairs or eight single-ended inputs.
PAGE 3
MCP3004/3008 1.0 † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings † VDD ..........................................
PAGE 4
MCP3004/3008 ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5V, VREF = 5V, TA = -40°C to +85°C, fSAMPLE = 200 ksps and fCLK = 18*fSAMPLE. Unless otherwise noted, typical values apply for VDD = 5V, TA = +25°C. Parameter Sym Min Typ Max Units — 0.001 ±1 µA Switch Resistance — 1000 — Ω See Figure 4-1 Sample Capacitor — 20 — pF See Figure 4-1 — — V — 0.
PAGE 5
MCP3004/3008 ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5V, VREF = 5V, TA = -40°C to +85°C, fSAMPLE = 200 ksps and fCLK = 18*fSAMPLE. Unless otherwise noted, typical values apply for VDD = 5V, TA = +25°C. Parameter Sym Min Typ Max Units Conditions Operating Voltage VDD 2.7 — 5.5 V Operating Current IDD — 425 225 550 µA VDD = VREF = 5V, DOUT unloaded VDD = VREF = 2.7V, DOUT unloaded Standby Current IDDS — 0.
PAGE 6
MCP3004/3008 Test Point 1.4V VDD 3 kΩ Test Point VDD/2 3 kΩ DOUT DOUT 100 pF CL = 100 pF tEN Waveform tDIS Waveform 1 VSS Voltage Waveforms for tR, tF tDIS Waveform 2 Voltage Waveforms for tEN VOH VOL DOUT tF tR Voltage Waveforms for tDO CS 1 CLK 2 3 B9 DOUT CLK tEN tDO Voltage Waveforms for tDIS DOUT CS FIGURE 1-2: 4 Load Circuit for tR, tF, tDO.
PAGE 7
MCP3004/3008 2.0 TYPICAL PERFORMANCE CHARACTERISTICS The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
PAGE 8
MCP3004/3008 Note: Unless otherwise indicated, VDD = VREF = 5V, fCLK = 18* fSAMPLE, TA = +25°C. 0.6 0.6 0.4 0.4 INL (LSB) INL (LSB) Positive INL 0.2 0.0 -0.2 VDD = VREF = 2.7 V fSAMPLE = 75 ksps Positive INL 0.2 0.0 Negative INL -0.2 Negative INL -0.4 -0.4 -0.6 -0.6 -50 -25 0 25 50 75 -50 100 -25 0 FIGURE 2-7: vs. Temperature. 25 50 75 100 Temperature (°C) Temperature (°C) Integral Nonlinearity (INL) FIGURE 2-10: Integral Nonlinearity (INL) vs. Temperature (VDD = 2.7V). 0.
PAGE 9
MCP3004/3008 Note: Unless otherwise indicated, VDD = VREF = 5V, fCLK = 18* fSAMPLE, TA = +25°C. 1.0 1.0 VDD = VREF = 5 V fSAMPLE = 200 ksps VDD = VREF = 2.7 V fSAMPLE = 75 ksps 0.8 0.6 0.6 0.4 0.4 DNL (LSB) DNL (LSB) 0.8 0.2 0.0 -0.2 0.2 0.0 -0.2 -0.4 -0.4 -0.6 -0.6 -0.8 -0.8 -1.0 -1.0 0 128 256 384 512 640 768 896 1024 0 128 256 384 Digital Code 512 640 768 896 1024 Digital Code FIGURE 2-16: Differential Nonlinearity (DNL) vs. Code (Representative Part, VDD =2.7V).
PAGE 10
MCP3004/3008 Note: Unless otherwise indicated, VDD = VREF = 5V, fCLK = 18* fSAMPLE, TA = +25°C. 1.2 0.0 VDD = VREF = 2.7 V fSAMPLE = 75 ksps -0.2 -0.3 -0.4 VDD = VREF = 5 V fSAMPLE = 200 ksps -0.5 VDD = VREF = 5 V fSAMPLE = 200 ksps 1.0 Offset Error (LSB) Gain Error (LSB) -0.1 0.8 VDD = VREF = 2.7 V fSAMPLE = 75 ksps 0.6 0.4 0.2 0.0 -0.6 -50 -25 0 25 50 75 -50 100 -25 0 FIGURE 2-19: Gain Error vs. Temperature. FIGURE 2-22: Temperature. 80 50 75 100 Offset Error vs.
PAGE 11
MCP3004/3008 Note: Unless otherwise indicated, VDD = VREF = 5V, fCLK = 18* fSAMPLE, TA = +25°C. 10.00 10.0 9.8 9.6 9.4 9.2 9.0 8.8 8.6 8.4 8.2 8.0 VDD = VREF = 2.7 V fSAMPLE = 75 ksps 9.50 9.25 VDD = VREF = 5 V fSAMPLE = 200 ksps 9.00 0.0 0.5 1.0 1.5 2.0 2.5 VDD = VREF = 5V fSAMPLE = 200 ksps ENOB (rms) ENOB (rms) 9.75 3.0 3.5 4.0 4.5 5.0 VDD = VREF = 2.7V fSAMPLE = 75 ksps 1 10 Input Frequency (kHz) VREF (V) FIGURE 2-25: (ENOB) vs. VREF.
PAGE 12
MCP3004/3008 550 550 500 500 450 450 400 400 350 350 IDD (µA) IDD (µA) Note: Unless otherwise indicated, VDD = VREF = 5V, fCLK = 18* fSAMPLE, TA = +25°C. 300 250 200 VREF = VDD All points at fCLK = 3.6 MHz except at VREF = VDD = 2.5 V, fCLK = 1.35 MHz 150 100 50 300 250 200 150 VREF = VDD All points at fCLK = 3.6 MHz except at VREF = VDD = 2.5 V, fCLK = 1.35 MHz 100 50 0 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 2.0 6.0 2.5 3.0 3.5 FIGURE 2-31: FIGURE 2-34: IDD vs. VDD.
PAGE 13
MCP3004/3008 Note: Unless otherwise indicated, VDD = VREF = 5V, fCLK = 18* fSAMPLE, TA = +25°C. 2.0 70 Analog Input Leakage (nA) VREF = CS = VDD 60 IDDS (pA) 50 40 30 20 10 0 1.8 VDD = VREF = 5 V 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 2-37: -50 -25 0 25 50 75 100 Temperature (°C) FIGURE 2-39: Analog Input Leakage Current vs. Temperature. IDDS vs. VDD. 100.00 VDD = VREF = CS = 5 V IDDS (nA) 10.00 1.00 0.10 0.
PAGE 15
MCP3004/3008 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 3-1. Additional descriptions of the device pins follows. TABLE 3-1: PIN FUNCTION TABLE MCP3004 MCP3008 PDIP, SOIC, TSSOP PDIP, SOIC 1 1 CH0 Analog Input 2 2 CH1 Analog Input 3 3 CH2 Analog Input 4 4 CH3 Analog Input – 5 CH4 Analog Input – 6 CH5 Analog Input – 7 CH6 Analog Input – 8 CH7 Analog Input 3.
PAGE 17
MCP3004/3008 4.0 DEVICE OPERATION The MCP3004/3008 A/D converters employ a conventional SAR architecture. With this architecture, a sample is acquired on an internal sample/hold capacitor for 1.5 clock cycles starting on the first rising edge of the serial clock once CS has been pulled low. Following this sample time, the device uses the collected charge on the internal sample and hold capacitor to produce a serial 10-bit digital output code. Conversion rates of 100 ksps are possible on the MCP3004/3008.
PAGE 18
MCP3004/3008 VDD RSS Sampling Switch VT = 0.6V CHx CPIN 7 pF VA VT = 0.6V SS ILEAKAGE ±1 nA RS = 1 kΩ CSAMPLE = DAC capacitance = 20 pF VSS Legend VA = Signal Source ILEAKAGE = Leakage Current At The Pin Due To Various Junctions RSS = Source Impedance SS = sampling switch CHx = Input Channel Pad RS = sampling switch resistor CPIN = Input Pin Capacitance VT = Threshold Voltage FIGURE 4-1: CSAMPLE = sample/hold capacitance Analog Input Model.
PAGE 19
MCP3004/3008 5.0 SERIAL COMMUNICATION Communication with the MCP3004/3008 devices is accomplished using a standard SPI-compatible serial interface. Initiating communication with either device is done by bringing the CS line low (see Figure 5-1). If the device was powered up with the CS pin low, it must be brought high and back low to initiate communication. The first clock received with CS low and DIN high will constitute a start bit.
PAGE 20
MCP3004/3008 tCYC tCYC tCSH CS tSUCS CLK DIN DOUT Start D2 D1 D0 SGL/ DIFF HI-Z Null Bit B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 * tCONV tSAMPLE D2 Start Don’t Care SGL/ DIFF HI-Z tDATA ** * After completing the data transfer, if further clocks are applied with CS low, the A/D converter will output LSB first data, then followed with zeros indefinitely. See Figure 5-2 below.
PAGE 21
MCP3004/3008 6.0 APPLICATIONS INFORMATION 6.1 Using the MCP3004/3008 with Microcontroller (MCU) SPI Ports As is shown in Figure 6-1, the first byte transmitted to the A/D converter contains seven leading zeros before the start bit. Arranging the leading zeros this way induces the 10 data bits to fall in positions easily manipulated by the MCU. The MSB is clocked out of the A/D converter on the falling edge of clock number 14.
PAGE 22
MCP3004/3008 MCU latches data from A/D converter on rising edges of SCLK CS 1 SCLK 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Data is clocked out of A/D converter on falling edges DIN Start Don’t Care NULL BIT B9 HI-Z DOUT Start Bit MCU Transmitted Data (Aligned with falling 0 edge of clock) MCU Received Data (Aligned with rising edge of clock) X = “Don’t Care” Bits FIGURE 6-2: 6.
PAGE 23
MCP3004/3008 6.4 Layout Considerations When laying out a printed circuit board for use with analog components, care should be taken to reduce noise wherever possible. A bypass capacitor should always be used with this device and should be placed as close as possible to the device pin. A bypass capacitor value of 1 µF is recommended. Digital and analog traces should be separated as much as possible on the board, with no traces running underneath the device or bypass capacitor.
PAGE 25
MCP3004/3008 7.0 PACKAGING INFORMATION 7.1 Package Marking Information 14-Lead PDIP (300 mil) Example: MCP3004 I/P e3 XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN 14-Lead SOIC (150 mil) 0819256 Example: XXXXXXXXXXX XXXXXXXXXXX YYWWNNN 14-Lead TSSOP (4.4mm) * MCP3004 3 ISL e^^ XXXXXXXXXXX 0819256 Example: XXXXXXXX 3004 YYWW I819 NNN 256 Legend: XX...
PAGE 26
MCP3004/3008 Package Marking Information (Continued) 16-Lead PDIP (300 mil) (MCP3008) Example: XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN 16-Lead SOIC (150 mil) (MCP3008) XXXXXXXXXXXXX XXXXXXXXXXXXX YYWWNNN DS21295D-page 26 MCP3008-I/P e3 0819256 Example: MCP3008 3 I/SL e^^ XXXXXXXXXX 0819256 © 2008 Microchip Technology Inc.
PAGE 27
MCP3004/3008 3 % & % ! % 4 " ) ' % 4 $ % % " % %% 255))) & &5 4 N NOTE 1 E1 1 3 2 D E A2 A L A1 c b1 b e eB 6 % & 9 & % 7!&( $ 7+8- 7 7 % ; % % 7: 1 + < < 0 , 0 1 % % 0 < < - , , 0 " " 4 ! " % 4 ! " = "% " "
PAGE 28
MCP3004/3008 ! " ! ## $% &' !" ( 3 % & % ! % 4 " ) ' % 4 $ % % " % %% 255))) & &5 4 D N E E1 NOTE 1 1 2 3 e h b A2 A α h c φ L A1 β L1 6 % & 9 & % 7!&( $ 99 - - 7 7 7: ; % : 8 % < < 0 < < < 0 " " 4 4 % " $$ * 1 + : = "% - " " 4 = "% - , 1 +
PAGE 29
MCP3004/3008 ) ! " ! ## $% &' !" ( 3 % & % ! % 4 " ) ' % 4 $ % % " % %% 255))) & &5 4 © 2008 Microchip Technology Inc.
PAGE 30
MCP3004/3008 *+ !+# , ! " !* & *!!" 3 % & % ! % 4 " ) ' % 4 $ % % " % %% 255))) & &5 4 D N E E1 NOTE 1 1 2 e b A2 A c A1 φ L L1 6 % & 9 & % 7!&( $ 99 - - 7 7 7: ; % : 8 % < < > 0 0 < 0 " " 4 4 % " $$ ?0 1 + : = "% - " " 4 = "% - ,
PAGE 31
MCP3004/3008 - 3 % & % ! % 4 " ) ' % 4 $ % % " % %% 255))) & &5 4 N NOTE 1 E1 1 2 3 D E A A2 L A1 c b1 e b eB 6 % & 9 & % 7!&( $ 7+8- 7 7 % ; ? % % 7: 1 + < < 0 , 0 1 % % 0 < < - , , 0 " " 4 ! " % 4 ! " = "% " "
PAGE 32
MCP3004/3008 - ! " ! ## $% &' !" ( 3 % & % ! % 4 " ) ' % 4 $ % % " % %% 255))) & &5 4 D N E E1 NOTE 1 1 3 2 e b h α h c φ A2 A L β A1 L1 6 % & 9 & % 7!&( $ 99 - - 7 7 7: ; ? % : 8 % < < 0 < < < 0 " " 4 4 % " $$ * 1 + : = "% - " " 4 = "% - , 1 + :
PAGE 35
MCP3004/3008 APPENDIX A: REVISION HISTORY Revision D (December 2008) The following is the list of modifications: 1. Updates to Section 7.0 “Packaging Information”. Revision C (January 2007) The following is the list of modifications: 1. Updates to the packaging diagrams. Revision B (May 2002) The following is the list of modifications: 1. Undocumented changes. Revision A (February 2000) • Initial release of this document. © 2008 Microchip Technology Inc.
PAGE 37
MCP3004/3008 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO.
PAGE 39
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PAGE 40
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