Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsData collecting ICsData acquisition IC - Digital potentiometer linear Non-permanent SC 70 6

MCP40D17/18/19

Features

• Potentiometer or Rheostat configuration options

• 7-bit: Resistor Network Resolution

- 127 Resistors (128 Steps)

• Zero Scale to Full Scale Wiper operation

•R

Resistances: 5 kΩ, 10 kΩ, 50 kΩ, or 100 kΩ

• Low Wiper Resistance: 100Ω (typical)

• Low Tempco:

- Absolute (Rheostat): 50 ppm typical

(0°C to 70°C)

- Ratiometric (Potentiometer): 15 ppm typical

•I

C Protocol

- Supports SMBus 2.0 Write Byte/Word

Protocol Formats

- Supports SMBus 2.0 Read Byte/Word

Protocol Formats

• Standard I

C Device Addresses:

- All devices offered with address “0101110”

- MCP40D18 also offered with address

“0111110”

• Brown-out reset protection (1.5V typical)

• Power-on Default Wiper Setting (Mid-scale)

• Low-Power Operation:

- 2.5 µA Static Current (typical)

• Wide Operating Voltage Range:

- 2.7V to 5.5V - Device Characteristics

Specified

- 1.8V to 5.5V - Device Operation

• Wide Bandwidth (-3 dB) Operation:

- 2 MHz (typical) for 5.0 kΩ device

• Extended temperature range (-40°C to +125°C)

• Very small package (SC70)

• Lead free (Pb-free) package

Package Types

Applications

• PC Servers (I

C Protocol with Command Code)

• Amplifier Gain Control and Offset Adjustment

• Sensor Calibration (Pressure, Temperature,

Position, Optical and Chemical)

• Set point or offset trimming

• Cost-sensitive mechanical trim pot replacement

• RF Amplifier Biasing

• LCD Brightnes and Contract Adjustment

Device Features

MCP40D18

SC70-6

MCP40D19

SC70-5

Rheostat

SDA

SCL

SDA

SCL

Potentiometer

MCP40D17

SC70-6

SDA

SCL

Device

Control

Interface

# of Steps

Wiper

Configuration

Memory

Type

Resistance (typical)

Operating

Range

(1)

PackageOptions (kΩ)

Wiper

(Ω)

MCP40D17 I

C 128 Rheostat RAM 5.0, 10.0, 50.0, 100.0 75 1.8V to 5.5V SC70-6

MCP40D18 I

C 128 Potentiometer RAM 5.0, 10.0, 50.0, 100.0 75 1.8V to 5.5V SC70-6

MCP40D19 I

C 128 Rheostat RAM 5.0, 10.0, 50.0, 100.0 75 1.8V to 5.5V SC70-5

Note 1: Analog characteristics only tested from 2.7V to 5.5V

7-Bit Single I

C™ (with Command Code) Digital POT

with Volatile Memory in SC70

Summary of content (66 pages)

PAGE 1
MCP40D17/18/19 7-Bit Single I2C™ (with Command Code) Digital POT with Volatile Memory in SC70 Package Types Features • Potentiometer or Rheostat configuration options • 7-bit: Resistor Network Resolution - 127 Resistors (128 Steps) • Zero Scale to Full Scale Wiper operation • RAB Resistances: 5 kΩ, 10 kΩ, 50 kΩ, or 100 kΩ • Low Wiper Resistance: 100Ω (typical) • Low Tempco: - Absolute (Rheostat): 50 ppm typical (0°C to 70°C) - Ratiometric (Potentiometer): 15 ppm typical • I2C Protocol - Supports SMBus 2.
PAGE 2
MCP40D17/18/19 Device Block Diagram VDD A (2) Power-up/ Brown-out Control VSS W I2C Serial Interface Module, Control Logic, & Memory SCL SDA Resistor Network 0 (Pot 0) B (1, 2) Note 1 Note 1: Some configurations will have this signal internally connected to ground. 2: In some configurations, this signal may not be connected externally (internally floating or grounded). I2C 128 Rheostat RAM 5.0, 10.0, 50.0, 100.0 1.8V to 5.5V No No SC70-6 MCP4017 ( 2, 4) I2C 128 Rheostat RAM 5.0, 10.
PAGE 3
MCP40D17/18/19 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings † Voltage on VDD with respect to VSS ..... -0.6V to +7.0V Voltage on SCL, and SDA with respect to VSS ............................................................................. -0.6V to 12.5V Voltage on all other pins (A, W, and B) with respect to VSS ............................ -0.3V to VDD + 0.3V Input clamp current, IIK (VI < 0, VI > VDD, VI > VPP ON HV pins) ........... ±20 mA Output clamp current, IOK (VO < 0 or VO > VDD) ....
PAGE 4
MCP40D17/18/19 AC/DC CHARACTERISTICS Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C ≤ TA ≤ +125°C (extended) DC Characteristics All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices. Typical specifications represent values for VDD = 5.5V, TA = +25°C. Parameters Sym Min Typ Max Units Conditions Supply Voltage VDD 2.7 — 5.5 V Analog Characteristics specified 1.8 — 5.
PAGE 5
MCP40D17/18/19 AC/DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C ≤ TA ≤ +125°C (extended) DC Characteristics Parameters Resistance (± 20%) All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices. Typical specifications represent values for VDD = 5.5V, TA = +25°C.
PAGE 6
MCP40D17/18/19 AC/DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C ≤ TA ≤ +125°C (extended) DC Characteristics All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices. Typical specifications represent values for VDD = 5.5V, TA = +25°C. Parameters Sym Min Typ Max Units Full Scale Error (MCP40D18 only) (code = 7Fh) VWFSE -3.0 -0.1 — LSb 5 kΩ 2.
PAGE 7
MCP40D17/18/19 AC/DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C ≤ TA ≤ +125°C (extended) DC Characteristics Parameters Rheostat Integral Non-linearity MCP40D18 (Note 3) MCP40D17 and MCP40D19 devices only (Note 3) All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices. Typical specifications represent values for VDD = 5.5V, TA = +25°C.
PAGE 8
MCP40D17/18/19 AC/DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C ≤ TA ≤ +125°C (extended) DC Characteristics All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices. Typical specifications represent values for VDD = 5.5V, TA = +25°C. Parameters Sym Min Typ Max Units Conditions Digital Inputs/Outputs (SDA, SCK) Schmitt Trigger High Input Threshold VIH 0.
PAGE 9
MCP40D17/18/19 I2C Mode Timing Waveforms and Requirements 1.1 SCL 93 91 90 92 SDA STOP Condition START Condition I2C Bus Start/Stop Bits Timing Waveforms. FIGURE 1-1: I2C BUS START/STOP BITS REQUIREMENTS TABLE 1-1: I2C AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C ≤ TA ≤ +125°C (Extended) Operating Voltage VDD range is described in Section 2.0 “Typical Performance Curves” Param. Symbol No.
PAGE 10
MCP40D17/18/19 I2C BUS DATA REQUIREMENTS (SLAVE MODE) TABLE 1-2: I2C AC Characteristics Parameter No. Sym Characteristic 100 THIGH Clock high time 101 TLOW Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C ≤ TA ≤ +125°C (Extended) Operating Voltage VDD range is described in AC/DC characteristics Min Max Units 100 kHz mode 4000 — ns 1.8V-5.5V 600 4700 — — ns ns 2.7V-5.
PAGE 11
MCP40D17/18/19 TEMPERATURE CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND.
PAGE 13
MCP40D17/18/19 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
PAGE 14
MCP40D17/18/19 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V. 0.2 0.1 0 60 -0.1 25°C RW -40°C 40 -0.2 20 125C Rw 125C INL 125C DNL 125°C 220 85° INL -40°C 0.1 140 100 RW 60 -40°C 25°C -0.1 -0.2 DNL DNL 125C Rw 125C INL 125C DNL 0.25 0.05 1000 -0.05 -0.15 RW -0.25 0 FIGURE 2-5: 5.0 kΩ : Pot Mode – RW (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (VDD = 1.8V).
PAGE 15
MCP40D17/18/19 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V. -0.4 RBW Tempco (PPM) Full-Scale Error (FSE) (LSb) 0.0 -0.2 -0.6 -0.8 5.5V -1.0 -1.2 2.7 -1.4 1.8V -1.6 -1.8 -40 0 40 80 Ambient Temperature (°C) 120 FIGURE 2-9: 5.0 kΩ : Full Scale Error (FSE) vs. Temperature (VDD = 5.5V, 2.7V, 1.8V). 200 180 160 140 120 100 80 60 40 20 0 2.7V 5.5V 0 32 64 96 Wiper Setting (decimal) FIGURE 2-12: 5.0 kΩ : RBW Tempco FIGURE 2-13: Response Time. 5.
PAGE 16
MCP40D17/18/19 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V. FIGURE 2-15: 5.0 kΩ : Write Wiper (40h → 3Fh) Settling Time (VDD=5.5V). FIGURE 2-18: 5.0 kΩ : Write Wiper (FFh → 00h) Settling Time (VDD=5.5V). FIGURE 2-16: 5.0 kΩ : Write Wiper (40h → 3Fh) Settling Time (VDD=2.7V). FIGURE 2-19: 5.0 kΩ : Write Wiper (FFh → 00h) Settling Time (VDD=2.7V). FIGURE 2-17: 5.0 kΩ : Write Wiper (40h → 3Fh) Settling Time (VDD=1.8V). FIGURE 2-20: 5.
PAGE 17
MCP40D17/18/19 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V. 0.2 0.1 80 0 60 -0.1 -40°C DNL 25°C RW INL -0.2 20 -0.3 260 25C Rw 25C INL 25C DNL INL 220 85C Rw 85C INL 85C DNL 125C Rw 125C INL 125C DNL 180 0 140 -0.1 DNL 100 RW 25°C 60 -0.2 -40°C 20 85C Rw 85C INL 85C DNL 125C Rw 125C INL 125C DNL 2000 0.25 0.05 -0.05 1000 RW INL -0.15 -0.25 0 85°C FIGURE 2-23: 10 kΩ Pot Mode : RW (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (VDD = 1.
PAGE 18
MCP40D17/18/19 0.0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 -0.9 -1.0 100 RBW Tempco (PPM) Full-Scale Error (FSE) (LSb) Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V. 5.5V 2.7 1.8V 80 2.7V 60 40 5.5V 20 0 -40 0 40 80 Ambient Temperature (°C) 120 FIGURE 2-27: 10 kΩ : Full Scale Error (FSE) vs. Temperature (VDD = 5.5V, 2.7V, 1.8V). 0 32 64 96 Wiper Setting (decimal) FIGURE 2-30: 10 kΩ : RBW Tempco FIGURE 2-31: Response Time. 10 kΩ : Power-Up Wiper ΔRWB / ΔT vs. Code.
PAGE 19
MCP40D17/18/19 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V. FIGURE 2-33: 10 kΩ : Write Wiper (40h → 3Fh) Settling Time (VDD=5.5V). FIGURE 2-36: 10 kΩ : Write Wiper (FFh → 00h) Settling Time (VDD=5.5V). FIGURE 2-34: 10 kΩ : Write Wiper (40h → 3Fh) Settling Time (VDD=2.7V). FIGURE 2-37: 10 kΩ : Write Wiper (FFh → 00h) Settling Time (VDD=2.7V). FIGURE 2-35: 10 kΩ : Write Wiper (40h → 3Fh) Settling Time (VDD=1.8V). FIGURE 2-38: 10 kΩ : Write Wiper (FFh → 00h) Settling Time (VDD=1.8V).
PAGE 20
MCP40D17/18/19 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V. 0.2 0.1 0 60 DNL -0.1 INL -40°C RW 25°C -0.2 20 -0.3 260 25C Rw 25C INL 25C DNL 85C Rw 85C INL 85C DNL 220 125C Rw 125C INL 125C DNL 125°C 85° 0 DNL -0.1 INL RW 25°C 60 -0.2 20 -0.05 INL -0.15 2000 RW 0 -0.25 DS22152B-page 20 125C Rw 125C INL 125C DNL 125°C 0.3 0.2 INL 0.1 25°C -0.1 DNL 60 RW -0.2 -40°C 20 -0.
PAGE 21
MCP40D17/18/19 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V. 100 RBW Tempco (PPM) Full-Scale Error (FSE) (LSb) 0.00 -0.04 -0.08 2.7 5.5V -0.12 1.8V -0.16 80 60 2.7V 40 5.5V 20 0 -40 0 40 80 Ambient Temperature (°C) 120 FIGURE 2-45: 50 kΩ : Full Scale Error (FSE) vs. Temperature (VDD = 5.5V, 2.7V, 1.8V). 0 32 64 96 Wiper Setting (decimal) FIGURE 2-48: 50 kΩ : RBW Tempco FIGURE 2-49: Response Time. 50 kΩ : Power-Up Wiper ΔRWB / ΔT vs. Code.
PAGE 22
MCP40D17/18/19 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V. FIGURE 2-51: 50 kΩ : Write Wiper (40h → 3Fh) Settling Time (VDD=5.5V). FIGURE 2-54: 50 kΩ : Write Wiper (FFh → 00h) Settling Time (VDD=5.5V). FIGURE 2-52: 50 kΩ : Write Wiper (40h → 3Fh) Settling Time (VDD=2.7V). FIGURE 2-55: 50 kΩ : Write Wiper (FFh → 00h) Settling Time (VDD=2.7V). FIGURE 2-53: 50 kΩ : Write Wiper (40h → 3Fh) Settling Time (VDD=1.8V). FIGURE 2-56: 50 kΩ : Write Wiper (FFh → 00h) Settling Time (VDD=1.8V).
PAGE 23
MCP40D17/18/19 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V. 0.2 0.1 0 INL 40 -0.1 RW -40°C 25°C -0.2 20 -0.3 260 25C Rw 25C INL 25C DNL DNL 220 85° 85C Rw 85C INL 85C DNL 125C Rw 125C INL 125C DNL 0 -0.1 100 INL 25°C 60 RW -0.2 2500 RW INL 0 -0.25 FIGURE 2-59: 100 kΩ Pot Mode : RW (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (VDD = 1.8V). © 2009 Microchip Technology Inc. 0.3 0.2 -0.1 -40°C RW -0.2 25°C 20 -0.
PAGE 24
MCP40D17/18/19 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V. 100 RBW Tempco (PPM) Full-Scale Error (FSE) (LSb) 0.00 -0.02 5.5V -0.04 2.7 -0.06 80 60 2.7V 40 20 5.5V 1.8V -0.08 0 -40 0 40 80 Ambient Temperature (°C) 120 FIGURE 2-63: 100 kΩ : Full Scale Error (FSE) vs. Temperature (VDD = 5.5V, 2.7V, 1.8V). 0 32 64 96 Wiper Setting (decimal) FIGURE 2-66: 100 kΩ : RBW Tempco ΔRWB / ΔT vs. Code. Zero-Scale Error (ZSE) (LSb) 0.12 0.08 1.8V 2.7 0.04 5.5V 0.
PAGE 25
MCP40D17/18/19 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V. FIGURE 2-69: 100 kΩ : Write Wiper (40h → 3Fh) Settling Time (VDD = 5.5V). FIGURE 2-72: 100 kΩ : Write Wiper (FFh → 00h) Settling Time (VDD = 5.5V). FIGURE 2-70: 100 kΩ : Write Wiper (40h → 3Fh) Settling Time (VDD = 2.7V). FIGURE 2-73: 100 kΩ : Write Wiper (FFh → 00h) Settling Time (VDD = 2.7V). FIGURE 2-71: 100 kΩ : Write Wiper (40h → 3Fh) Settling Time (VDD = 1.8V).
PAGE 26
MCP40D17/18/19 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V. 4 0.3 3.5 2.5 VOL (mV) VIH (V) 0.25 5.5V 3 2.7V 2 1.5 2.7V (@ 3mA) 0.2 0.15 5.5V (@ 3mA) 0.1 1 1.8V (@ 1mA) 0.05 0.5 1.8V 0 0 -40 0 40 80 120 -40 0 Temperature (°C) FIGURE 2-75: Temperature. VIH (SCL, SDA) vs. VDD and FIGURE 2-77: Temperature. 80 120 VOL (SDA) vs. VDD and 1.2 2 5.5 V 1 5.5V 1.5 2.7V 0.8 VDD (V) VIL (V) 40 Temperature (°C) 1 2.7V 0.6 0.4 0.5 1.8V 0.
PAGE 27
MCP40D17/18/19 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V. 10 10 Code = 7Fh Code = 7Fh 0 0 Code = 3Fh dB dB -20 Code = 0Fh -30 Code = 3Fh -10 -10 Code = 1Fh Code = 1Fh -20 Code = 0Fh -30 Code = 01h -40 Code = 01h -40 -50 -50 100 1,000 -60 100 10,000 1,000 5 kΩ – Gain vs. Frequency FIGURE 2-79: (-3 dB). FIGURE 2-82: 100 kΩ – Gain vs. Frequency (-3 dB). 2.
PAGE 29
MCP40D17/18/19 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 3-1. Additional descriptions of the device pins follow.
PAGE 30
MCP40D17/18/19 3.1 Positive Power Supply Input (VDD) The VDD pin is the device’s positive power supply input. The input power supply is relative to VSS and can range from 1.8V to 5.5V. A de-coupling capacitor on VDD (to VSS) is recommended to achieve maximum performance. While the device’s voltage is in the range of 1.8V ≤ VDD < 2.7V, the Resistor Network’s electrical performance of the device may not meet the data sheet specifications. 3.2 Ground (VSS) The VSS pin is the device ground reference. 3.
PAGE 31
MCP40D17/18/19 4.0 GENERAL OVERVIEW The MCP40D17/18/19 devices are general purpose digital potentiometers intended to be used in applications where a programmable resistance with moderate bandwidth is desired. This Data Sheet covers a family of three Digital Potentiometer and Rheostat devices. The MCP40D18 device is the Potentiometer configuration, while the MCP40D17 and MCP40D19 devices are the Rheostat configuration.
PAGE 32
MCP40D17/18/19 TABLE 4-1: VDD Level DEVICE FUNCTIONALITY AT EACH VDD REGION (NOTE 1) Serial Interface Potentiometer Terminals “unknown” VDD < VBOR < 1.8V Ignored VBOR ≤ VDD < 1.8V “Unknown” Operational with reduced electrical specs 1.8V ≤ VDD < 2.7V Accepted Operational with reduced electrical specs 2.7V ≤ VDD ≤ 5.
PAGE 33
MCP40D17/18/19 5.0 SERIAL INTERFACE I2C MODULE 5.1 A 2-wire I2C serial protocol is used to write or read the digital potentiometer’s wiper register. The I2C protocol utilizes the SCL input pin and SDA input/output pin.
PAGE 34
MCP40D17/18/19 5.2 I2C Bit Definitions If the Slave Address is not valid, the Slave Device will issue a Not A (A). The A bit will have the SDA signal high. I2C bit definitions include: • • • • • • Start Bit Data Bit Acknowledge (A) Bit Repeated Start Bit Stop Bit Clock Stretching If an error condition occurs (such as an A instead of A) then a START bit must be issued to reset the command state machine. TABLE 5-1: Figure 5-8 shows the waveform for these states. 5.2.
PAGE 35
MCP40D17/18/19 5.2.5 STOP BIT 5.2.7 If any part of the I2C transmission does not meet the command format, it is aborted. This can be intentionally accomplished with a START or STOP condition. This is done so that noisy transmissions (usually an extra START or STOP condition) are aborted before they corrupt the device. The Stop bit (see Figure 5-6) Indicates the end of the I2C Data Transfer Sequence. The Stop bit is defined as the SDA signal rising when the SCL signal is “High”.
PAGE 36
MCP40D17/18/19 I2C COMMAND PROTOCOL 5.2.9 TABLE 5-2: The MCP40D17/18/19 is a slave I2C device which supports 7-bit slave addressing. The slave address contains seven fixed bits. Figure 5-9 shows the control byte format. MCP40D17 5.2.9.1 MCP40D19 Device MCP40D18 Control Byte (Slave Address) The Control Byte is always preceded by a START condition. The Control Byte contains the slave address consisting of seven fixed bits and the R/W bit.
PAGE 37
MCP40D17/18/19 5.3 Software Reset Sequence Note: This technique should be supported by any I2C compliant device. The 24XXXX I2C Serial EEPROM devices support this technique, which is documented in AN1028. The Stop bit terminates the current I2C bus activity. The MCP40D17/18/19 wait to detect the next Start condition. This sequence does not effect any other I2C devices which may be on the bus, as they should disregard this as an invalid command.
PAGE 38
MCP40D17/18/19 5.4.1 WRITE OPERATION 5.4.2 The read operation requires the START condition, Control Byte, Acknowledge, Command Code, Acknowledge, Restart Condition, Control Byte, Acknowledge, Data Byte, the master generating the A and STOP (or RESTART) condition. The first Control Byte requires the R/W bit equal to a logic zero (R/W = “0”) to write the Command Code, while the second Control Byte requires the R/W bit equal to a logic one (R/W = “1”) to generate a read sequence.
PAGE 39
MCP40D17/18/19 Fixed Address S 0 1 0 1 1 Read/Write bit (“0” = Write) 1 1 0 A 0 0 0 0 0 0 0 0 A X D6 D5 D4 D3 D2 D1 D0 A Command Code Slave Address Byte Data Byte STOP bit X D6 D5 D4 D3 D2 D1 D0 A X D6 D5 D4 D3 D2 D1 D0 A P Data Byte Data Byte Legend S = Start Condition P = Stop Condition A = Acknowledge X = Don’t Care R/W = Read/Write bit D6:D0 = Data bits FIGURE 5-13: I2C Write Command Format (Slave Address = “0101110”).
PAGE 40
MCP40D17/18/19 Read/Write bit (“0” = Write) S 0 1 0 1 1 1 0 0 A 0 0 0 0 0 0 0 0 A Command Code Slave Address Byte STOP bit Read/Write bit (“1” = Read) S 0 1 0 1 1 1 0 1 A 0 D6 D5 D4 D3 D2 D1 D0 A(2) P Slave Address Byte Legend S = Start Condition P = Stop Condition A = Acknowledge X = Don’t Care R/W = Read/Write bit D6:D0 = Data bits Data Byte Note 1: Master Device is responsible for ACK / NACK signal.
PAGE 41
MCP40D17/18/19 6.0 RESISTOR NETWORK A The Resistor Network is made up of two parts. These are: • Resistor Ladder • Wiper Figure 6-1 shows a block diagram for the resistive network.
PAGE 42
MCP40D17/18/19 Step resistance (RS) is the resistance from one tap setting to the next. This value will be dependent on the RAB value that has been selected. Equation 6-1 shows the calculation for the step resistance while Table 6-2 shows the typical step resistances for each device. EQUATION 6-1: RS CALCULATION A POR/BOR event will load the Volatile Wiper register value with the default value. Table 6-3 shows the default values offered.
PAGE 43
MCP40D17/18/19 6.2 Resistor Configurations 6.2.1 6.2.2 RHEOSTAT CONFIGURATION When used as a rheostat, two of the three digital potentiometer’s terminals are used as a resistive element in the circuit. With terminal W (wiper) and either terminal A or terminal B, a variable resistor is created. The resistance will depend on the tap setting of the wiper (and the wiper’s resistance). The resistance is controlled by changing the wiper setting The unused terminal (B or A) should be left floating.
PAGE 44
MCP40D17/18/19 6.3 Wiper Resistance In a potentiometer configuration, the wiper resistance variation does not effect the output voltage seen on the W pin. Wiper resistance is the series resistance of the analog switch that connects the selected resistor ladder node to the Wiper Terminal common signal (see Figure 6-1). The slope of the resistance has a linear area (at the higher voltages) and a non-linear area (at the lower voltages).
PAGE 45
MCP40D17/18/19 6.4 Operational Characteristics Understanding the operational characteristics of the device’s resistor components is important to the system design. 6.4.1 6.4.1.1 6.4.1.2 Differential Non-linearity (DNL) DNL error is the measure of variations in code widths from the ideal code width. A DNL error of zero would imply that every code is exactly 1 LSb wide.
PAGE 46
MCP40D17/18/19 6.4.2 MONOTONIC OPERATION Monotonic operation means that the device’s resistance increases with every step change (from terminal A to terminal B or terminal B to terminal A). The wiper resistances difference at each tap location. When changing from one tap position to the next (either increasing or decreasing), the ΔRW is less than the ΔRS. When this change occurs, the device voltage and temperature are “the same” for the two tap positions.
PAGE 47
MCP40D17/18/19 7.0 DESIGN CONSIDERATIONS In the design of a system with the MCP40D17/18/19 devices, the following considerations should be taken into account. These are: • The Power Supply • The Layout In the design of a system with the MCP40D17/18/19 devices, the following considerations should be taken into account: • Power Supply Considerations • Layout Considerations 7.
PAGE 49
MCP40D17/18/19 8.0 APPLICATIONS EXAMPLES VDD Digital potentiometers have a multitude of practical uses in modern electronic circuits. The most popular uses include precision calibration of set point thresholds, sensor trimming, LCD bias trimming, audio attenuation, adjustable power supplies, motor control overcurrent trip setting, adjustable gain amplifiers and offset trimming.
PAGE 50
MCP40D17/18/19 8.2 Operational Amplifier Applications MCP40D18 B Figure 8-3 and Figure 8-4 illustrate typical amplifier circuits that could replace fixed resistors with the MCP40D17/18/19 to achieve digitally-adjustable analog solutions. VIN + VOUT ‚ VDD ‚ Op Amp VIN A Op Amp VDD W R1 MCP6291 R1 W B MCP40D18 A W MCP40D17 FIGURE 8-3: Trimming Offset and Gain in a Non-Inverting Amplifier.
PAGE 51
MCP40D17/18/19 8.3 Temperature Sensor Applications Thermistors are resistors with very predictable variation with temperature. Thermistors are a popular sensor choice when a low-cost temperature-sensing solution is desired. Unfortunately, thermistors have non-linear characteristics that are undesirable, typically requiring trimming in an application to achieve greater accuracy. There are several common solutions to trim and linearize thermistors.
PAGE 52
MCP40D17/18/19 8.4 Wheatstone Bridge Trimming Another common configuration to “excite” a sensor (such as a strain gauge, pressure sensor or thermistor) is the wheatstone bridge configuration. The wheatstone bridge provides a differential output instead of a single-ended output. Figure 8-7 illustrates a wheatstone bridge utilizing one to three digital potentiometers. The digital potentiometers in this example are used to trim the offset and gain of the wheatstone bridge.
PAGE 53
MCP40D17/18/19 9.0 DEVELOPMENT SUPPORT 9.1 Development Tools 9.2 Several additional technical documents are available to assist you in your design and development. These technical documents include Application Notes, Technical Briefs, and Design Guides. Table 9-1 shows some of these documents. The MCP40D17/18/19 devices can be evaluated with the MCP4XXXDM-PGA board, but it will require the removal of the MCP4017 device and the installation of the MCP40D17 device.
PAGE 55
MCP40D17/18/19 10.0 PACKAGING INFORMATION 10.
PAGE 56
MCP40D17/18/19 .
PAGE 58
MCP40D17/18/19 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22152B-page 58 © 2009 Microchip Technology Inc.
PAGE 59
MCP40D17/18/19 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2009 Microchip Technology Inc.
PAGE 60
MCP40D17/18/19 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22152B-page 60 © 2009 Microchip Technology Inc.
PAGE 61
MCP40D17/18/19 APPENDIX A: REVISION HISTORY Revision B (August 2009) the following is the List of Modifications: 1. 2. Document updated to include the new standard I2C slave address (“0111110“) for the MCP40D18 device. Section 10.0 “Packaging Information”: Corrected the Marking codes for 5-lead SC70 Codes shown were for the 6-lead SC70. Updated Package Outline Drawings. Revision A (May 2009) • Original Release of this Document. © 2009 Microchip Technology Inc.
PAGE 63
MCP40D17/18/19 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO.
PAGE 65
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PAGE 66
WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.