Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsData collecting ICsData acquisition IC - Digital potentiometer linear Non-permanent PDIP 14

 2003 Microchip Technology Inc. DS11195C-page 1

MCP41XXX/42XXX

Features

• 256 taps for each potentiometer

• Potentiometer values for 10 kΩ, 50 kΩ and

100 kΩ

• Single and dual versions

• SPI™ serial interface (mode 0,0 and 1,1)

• ±1 LSB max INL & DNL

• Low power CMOS technology

• 1 µA maximum supply current in static operation

• Multiple devices can be daisy-chained together

(MCP42XXX only)

• Shutdown feature open circuits of all resistors for

maximum power savings

• Hardware shutdown pin available on MCP42XXX

only

• Single supply operation (2.7V - 5.5V)

• Industrial temperature range: -40°C to +85°C

• Extended temperature range: -40°C to +125°C

Block Diagram

Description

The MCP41XXX and MCP42XXX devices are 256-

position, digital potentiometers available in 10 kΩ,

50 kΩ and 100 kΩ resistance versions. The

MCP41XXX is a single-channel device and is offered in

an 8-pin PDIP or SOIC package. The MCP42XXX con-

tains two independent channels in a 14-pin PDIP, SOIC

or TSSOP package. The wiper position of the

MCP41XXX/42XXX varies linearly and is controlled via

an industry-standard SPI interface. The devices con-

sume <1 µA during static operation. A software shut-

down feature is provided that disconnects the “A”

terminal from the resistor stack and simultaneously con-

nects the wiper to the “B” terminal. In addition, the dual

MCP42XXX has a SHDN

pin that performs the same

function in hardware. During shutdown mode, the con-

tents of the wiper register can be changed and the

potentiometer returns from shutdown to the new value.

The wiper is reset to the mid-scale position (80h) upon

power-up. The RS

(reset) pin implements a hardware

reset and also returns the wiper to mid-scale. The

MCP42XXX SPI interface includes both the SI and SO

pins, allowing daisy-chaining of multiple devices. Chan-

nel-to-channel resistance matching on the MCP42XXX

varies by less than 1%. These devices operate from a

single 2.7 - 5.5V supply and are specified over the

extended and industrial temperature ranges.

Package Types

16-Bit

Shift

SCK

SHDN

PB1

PA1

PW1

Resistor

Array 1*

Wiper

PB0

PW0

PA0

Resistor

Array 0

Wiper

Control

Logic

*Potentiometer P1 is only available on the dual

MCP42XXX version.

MCP42XXX

PDIP/SOIC/TSSOP

PB1

PA1

PW1

SHDN

PW0

PB0

PA0

SCK

MCP41XXX

PDIP/SOIC

PB0

PA0

PW0

SCK

Single/Dual Digital Potentiometer with SPI

™

Interface

Summary of content (32 pages)

PAGE 1
M MCP41XXX/42XXX Single/Dual Digital Potentiometer with SPI™ Interface Features Description • 256 taps for each potentiometer • Potentiometer values for 10 kΩ, 50 kΩ and 100 kΩ • Single and dual versions • SPI™ serial interface (mode 0,0 and 1,1) • ±1 LSB max INL & DNL • Low power CMOS technology • 1 µA maximum supply current in static operation • Multiple devices can be daisy-chained together (MCP42XXX only) • Shutdown feature open circuits of all resistors for maximum power savings • Hardware shutdown
PAGE 2
MCP41XXX/42XXX 1.0 ELECTRICAL CHARACTERISTICS DC CHARACTERISTICS: 10 kΩ VERSION Electrical Characteristics: Unless otherwise indicated, VDD = +2.7V to 5.5V, TA = -40°C to +85°C (TSSOP devices are only specified at +25°C and +85°C). Typical specifications represent values for VDD = 5V, VSS = 0V, VB = 0V, TA = +25°C.
PAGE 3
MCP41XXX/42XXX DC CHARACTERISTICS: 50 kΩ VERSION Electrical Characteristics: Unless otherwise indicated, VDD = +2.7V to 5.5V, TA = -40°C to +85°C (TSSOP devices are only specified at +25°C and +85°C). Typical specifications represent values for VDD = 5V, VSS = 0V, VB = 0V, TA = +25°C.
PAGE 4
MCP41XXX/42XXX DC CHARACTERISTICS: 100 kΩ VERSION Electrical Characteristics: Unless otherwise indicated, VDD = +2.7V to 5.5V, TA = -40°C to +85°C (TSSOP devices are only specified at +25°C and +85°C). Typical specifications represent values for VDD = 5V, VSS = 0V, VB = 0V, TA = +25°C.
PAGE 5
MCP41XXX/42XXX Absolute Maximum Ratings † VDD...................................................................................7.0V † Notice: Stresses above those listed under “maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied.
PAGE 6
MCP41XXX/42XXX tCSH CS 1/FCLK tCSSR tHI tCSO SCK tCHS tLO tCS1 tSU tHD SI msb in tDO (First 16 bits out are always zeros) SO tS ±1% Error Band VOUT FIGURE 1-1: ±1% Detailed Serial interface Timing. Wiper position is changed to mid-scale (80h) if RS is held low for 150 ns Code 80h is latched on rising edge of RS CS tRSCS tRS RS tS VOUT FIGURE 1-2: ±1% Error Band ±1% Reset Timing. tCSL CS tSE tRS RS tSE tSH SHDN FIGURE 1-3: DS11195C-page 6 Software Shutdown Exit Timing.
PAGE 7
MCP41XXX/42XXX 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
PAGE 8
MCP41XXX/42XXX Refer to Figure 2-27 TA = +85°C TA = +25°C TA = -40°C 0 32 64 FIGURE 2-7: Code. 96 128 160 Code (Decimal) 224 TA = -40°C to +85°C, VA = no connect, RWB measured 2500 2000 1500 1000 500 0 0 32 64 96 280 VDD = 5V 230 130 80 VDD = 3V 30 5 FIGURE 2-10: Temperature. 1000 Active Supply Current vs. A - VDD = 5.5V, Code = AAh B - VDD = 3.3V, Code = AAh C - VDD = 5.5V, Code = FFh D - VDD = 3.
PAGE 9
MCP41XXX/42XXX Note: Unless otherwise indicated, curve represents 10 kΩ, 50 kΩ and 100 kΩ devices, VDD = 5V, VSS = 0V, TA = +25°C, VB = 0V. Number of Occurrences 180 160 140 CL = 27 pF MCP41010,MCP42010 Code = 00h, Sample Size = 400 VOUT 120 FFh 100 80 00h 60 40 20 CS 0 47 48 49 50 51 52 53 54 55 56 57 58 59 Wiper Resistance (Ω) FIGURE 2-13: 10 kΩ Device Wiper Resistance Histogram. Number of Occurrences 140 FIGURE 2-16: Full-Scale Settling Time.
PAGE 10
MCP41XXX/42XXX Note: Unless otherwise indicated, curve represents 10 kΩ, 50 kΩ and 100 kΩ devices, VDD = 5V, VSS = 0V, TA = +25°C, VB = 0V.
PAGE 11
MCP41XXX/42XXX 2.1 Parametric Test Circuits A V+ B DUT VA V+ = VDD 1LSB = V+/256 VDD A V+ W B DUT + VMEAS* - W + V MEAS* - *Assume infinite input impedance V+ = VDD ± 10% FIGURE 2-25: Potentiometer Divider NonLinearity Error Test Circuit (DNL, INL). PSRR (dB) = 20LOG ( PSS (%/%) = ∆VDD ∆VMEAS No Connection *Assume infinite input impedance A FIGURE 2-28: Power Supply Sensitivity Test Circuit (PSS, PSRR). IW W B + - VMEAS* DUT A VIN *Assume infinite input impedance Rsw = 0.
PAGE 12
MCP41XXX/42XXX 3.0 PIN DESCRIPTIONS 3.1 PA0, PA1 3.9 Shutdown (SHDN) (MCP42XXX devices only) Potentiometer Wiper Connection. The Shutdown pin has a Schmitt Trigger input. Pulling this pin low will put the device in a power-saving mode where A terminal is opened and the B and W terminals are connected for all potentiometers. This pin should not be toggled low when the CS pin is low. In order to minimize power consumption, this pin has an active pull-up circuit.
PAGE 13
MCP41XXX/42XXX 4.0 APPLICATIONS INFORMATION The MCP41XXX/42XXX devices are 256 position single and dual digital potentiometers that can be used in place of standard mechanical pots. Resistance values of 10 kΩ, 50 kΩ and 100 kΩ are available. As shown in Figure 4-1, each potentiometer is made up of a variable resistor and an 8-bit (256 position) data register that determines the wiper position. There is a nominal wiper resistance of 52Ω for the 10 kΩ version, 125Ω for the 50 kΩ and 100 kΩ versions.
PAGE 14
MCP41XXX/42XXX 4.1 Modes of Operation Digital potentiometer applications can be divided into two categories: rheostat mode and potentiometer, or voltage divider, mode. 4.1.1 RHEOSTAT MODE In the rheostat mode, the potentiometer is used as a two-terminal resistive element. The unused terminal should be tied to the wiper, as shown in Figure 4-2. Note that reversing the polarity of the A and B terminals will not affect operation. 4.1.
PAGE 15
MCP41XXX/42XXX 4.2 Typical Applications 4.2.1 PROGRAMMABLE SINGLE-ENDED AMPLIFIERS Potentiometers are often used to adjust system reference levels or gain. Programmable gain circuits using digital potentiometers can be realized in a number of different ways. An example of a single-supply, inverting gain amplifier is shown in Figure 4-4. Due to the high input impedance of the amplifier, the wiper resistance is not included in the transfer function.
PAGE 16
MCP41XXX/42XXX 4.3 1/2 MCP42010 A B VB (SIG -) -IN VA A 1/2 MCP42010 (SIG +) Where: RA VDD + VOUT MCP601 +IN - VSS B VREF RB R AB D n = ----------------256 R AB = Total Resistance of pot D n = Wiper setting forDn = 0 to 255 NOTE: Potentiometer values must be equal FIGURE 4-7: Single Supply programmable differential amplifier using digital potentiometers. PROGRAMMABLE OFFSET TRIM For applications requiring only a programmable voltage reference, the circuit in Figure 4-8 can be used.
PAGE 17
MCP41XXX/42XXX 5.0 SERIAL INTERFACE Communications from the controller to the MCP41XXX/42XXX digital potentiometers is accomplished using the SPI serial interface. This interface allows three commands: 1. 2. 3. Write a new value to the potentiometer data register(s). Cause a channel to enter low power shutdown mode. NOP (No Operation) command. Executing any command is accomplished by setting CS low and then clocking-in a command byte followed by a data byte into the 16-bit shift register.
PAGE 18
MCP41XXX/42XXX Data is always latched in on the rising edge of SCK. Data is always clocked out of the SO pin after the falling edge of SCK. Data Registers are loaded on rising edge of CS. Shift register is loaded with zeros at this time.
PAGE 19
MCP41XXX/42XXX 5.4 Daisy-Chain Configuration Multiple MCP42XXX devices can be connected in a daisy-chain configuration, as shown in Figure 5-4, by connecting the SO pin from one device to the SI pin on the next device. The data on the SO pin is the output of the 16-bit shift register. The daisy-chain configuration allows the system designer to communicate with several devices without using a separate CS line for each device.
PAGE 20
MCP41XXX/42XXX CS SCK SO Microcontroller CS SCK SO SI Device 1 EXAMPLE: CS SCK SI SO Device 2 If you want to load the following command/data into each part in the chain. Device 2 XX01XX10 11110000 c SI Device 3 XX10XX00 10101010 After 16 clocks, Device 2 and Device 3 will both have all zeros clocked in from the previous part’s shift register. Device 1 XX10XX00 10101010 Device 2 00000000 00000000 d Clock-In the command and data for Device 2 (16 more clocks).
PAGE 21
MCP41XXX/42XXX 5.5 Reset (RS) Pin Operation The Reset pin (RS) will automatically set all potentiometer data latches to mid-scale (Code 80h) when pulled low (provided that the pin is held low at least 150 ns and CS is high). The reset will execute regardless of the position of the SCK, SHDN and SI pins. It is possible to toggle RS low and back high while SHDN is low.
PAGE 22
MCP41XXX/42XXX 5.8 Using the MCP41XXX/42XXX in SPI Mode 1,1 It is possible to operate the devices in SPI modes 0,0 and 1,1. The only difference between these two modes is that, when using mode 1,1, the clock idles in the high state, while in mode 0,0, the clock idles in the low state. In both modes, data is clocked into the devices on the rising edge of SCK and data is clocked out the SO pin once the falling edge of SCK. Operations using mode 0,0 are shown in Figure 5-1.
PAGE 23
MCP41XXX/42XXX 6.0 PACKAGING INFORMATION 6.1 Package Marking Information 8-Lead PDIP (300 mil) Example: XXXXXXXX XXXXXNNN YYWW MCP41010 I/P256 0313 8-Lead SOIC (150 mil) Example: XXXXXXXX XXXXYYWW NNN MCP41050 I/SN0313 256 14-Lead PDIP (300 mil) Example: XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN 14-Lead SOIC (150 mil) MCP42010 I/P 0313256 Example: 42050ISL XXXXXXXXXXX 0313256 XXXXXXXXXXX XXXXXXXXXXX YYWWNNN 14-Lead TSSOP (4.4mm) * Example: XXXXXXXX YYWW 0313 NNN 256 Legend: XX...
PAGE 24
MCP41XXX/42XXX 8-Lead Plastic Dual In-line (P) – 300 mil (PDIP) E1 D 2 n 1 α E A2 A L c A1 β B1 p eB B Units Dimension Limits n p Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D L c § B1 B
PAGE 25
MCP41XXX/42XXX 8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 h α 45° c A2 A φ β L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D h L φ c B α β MIN .053 .052 .004 .228 .146 .189 .010 .
PAGE 26
MCP41XXX/42XXX 14-Lead Plastic Dual In-line (P) – 300 mil (PDIP) E1 D 2 n 1 α E A2 A L c A1 B1 β eB p B Units Dimension Limits n p MIN INCHES* NOM 14 .100 .155 .130 MAX MILLIMETERS NOM 14 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 18.80 19.05 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 MIN Number of Pins Pitch Top to Seating Plane A .140 .170 Molded Package Thickness A2 .115 .145 Base to Seating Plane A1 .015 Shoulder to Shoulder Width E .300 .313 .
PAGE 27
MCP41XXX/42XXX 14-Lead Plastic Small Outline (SL) – Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 α h 45° c A2 A φ A1 L β Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D h L φ c B α β MIN .053 .052 .004 .228 .150 .337 .010 .
PAGE 28
MCP41XXX/42XXX 14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP) E E1 p D 2 1 n B α A c φ β A1 L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Molded Package Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D L φ c B α β MIN .033 .002 .246 .169 .193 .020 0 .004 .
PAGE 29
MCP41XXX/42XXX PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO.
PAGE 30
MCP41XXX/42XXX NOTES: DS11195C-page 30  2003 Microchip Technology Inc.
PAGE 31
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PAGE 32
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