Datasheet

ManualsBrandsMicrochip ManualsMemory ICsSRAM SPI 1MB 2.5 ... 5.5V SOIC

 2012 Microchip Technology Inc. Preliminary DS25156A-page 1

23LCV1024

Device Selection Table

Features:

• SPI-Compatible Bus Interface:

- 20 MHz Clock rate

- SPI/SDI mode

• Low-Power CMOS Technology:

- Read Current: 3 mA at 5.5V, 20 MHz

- Standby Current: 4 A at +85°C

• Unlimited Read and Write Cycles

• External Battery Backup Support

• Zero Write Time

• 128K x 8-bit Organization:

- 32-byte page

• Byte, Page and Sequential mode for Reads and

Writes

• High Reliability

• Temperature Range Supported:

• Pb-Free and RoHS Compliant, Halogen Free

• 8-Lead SOIC, TSSOP and PDIP Packages

Pin Function Table

Description:

The Microchip Technology Inc. 23LCV1024 is a 1 Mbit

Serial SRAM device. The memory is accessed via a

simple Serial Peripheral Interface (SPI) compatible

serial bus. The bus signals required are a clock input

(SCK) plus separate data in (SI) and data out (SO)

lines. Access to the device is controlled through a Chip

Select (CS

) input. Additionally, SDI (Serial Dual Inter-

face) is supported if your application needs faster data

rates.

This device also supports unlimited reads and writes to

the memory array, and supports data backup via an

external battery/coin cell connected to V

BAT (pin 7).

The 23LCV1024 is available in standard packages

including 8-lead SOIC, PDIP and advanced 8-lead

TSSOP.

Package Types (not to scale)

Part

Number

CC Range

Dual I/O

(SDI)

Battery

Backup

Max. Clock

Frequency

Packages

23LCV1024 2.5-5.5V Yes Yes 20 MHz SN, ST, P

- Industrial (I): -40Cto +85C

Name Function

CS Chip Select Input

SO/SIO1 Serial Output/SDI Pin

Vss Ground

SI/SIO0 Serial Input/SDI Pin

SCK Serial Clock

BAT External Backup Supply Input

Vcc Power Supply

SO/SIO1

Vss

Vcc

VBAT

SCK

SI/SIO0

SOIC/TSSOP/PDIP

1 Mbit SPI Serial SRAM with Battery Backup and SDI Interface

Summary of content (30 pages)

PAGE 1
23LCV1024 1 Mbit SPI Serial SRAM with Battery Backup and SDI Interface Device Selection Table Part Number 23LCV1024 VCC Range Dual I/O (SDI) Battery Backup Max. Clock Frequency 2.5-5.5V Yes Yes 20 MHz Packages SN, ST, P Features: Description: • SPI-Compatible Bus Interface: - 20 MHz Clock rate - SPI/SDI mode • Low-Power CMOS Technology: - Read Current: 3 mA at 5.
PAGE 2
3LCV1024 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (†) VCC .............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS ......................................................................................................... -0.3V to VCC +0.3V Storage temperature ...............................................................................
PAGE 3
23LCV1024 TABLE 1-2: AC CHARACTERISTICS AC CHARACTERISTICS Param. Sym. No. Industrial (I): Characteristic TA = -40°C to +85°C Min. Max.
PAGE 4
23LCV1024 FIGURE 1-1: SERIAL INPUT TIMING (SPI MODE) 4 CS 2 7 8 3 11 SCK 5 SI 6 MSB in LSB in High-Impedance SO FIGURE 1-2: SERIAL OUTPUT TIMING (SPI MODE) CS 9 3 10 SCK 12 SO SI DS25156A-page 4 13 MSB out 14 LSB out Don’t Care Preliminary  2012 Microchip Technology Inc.
PAGE 5
23LCV1024 2.0 FUNCTIONAL DESCRIPTION 2.1 Principles of Operation The 23LCV1024 is an 1 Mbit Serial SRAM designed to interface directly with the Serial Peripheral Interface (SPI) port of many of today’s popular microcontroller families, including Microchip’s PIC® microcontrollers. It may also interface with microcontrollers that do not have a built-in SPI port by using discrete I/O lines programmed properly in firmware to match the SPI protocol.
PAGE 6
23LCV1024 TABLE 2-1: INSTRUCTION SET Instruction Format Hex Code Description READ 0000 0011 0x03 Read data from memory array beginning at selected address WRITE 0000 0010 0x02 Write data to memory array beginning at selected address EDIO 0011 1011 0x3B Enter Dual I/O access RSTIO 1111 1111 0xFF Reset Dual I/O access RDMR 0000 0101 0x05 Read Mode Register WRMR 0000 0001 0x01 Write Mode Register Instruction Name FIGURE 2-1: BYTE READ SEQUENCE (SPI MODE) CS 0 1 2 3 4 5 6 7
PAGE 7
23LCV1024 FIGURE 2-3: PAGE READ SEQUENCE (SPI MODE) CS 0 1 2 0 0 0 3 4 5 6 7 8 9 10 11 29 30 31 32 33 34 35 36 37 38 39 SCK Instruction SI 0 0 24-bit Address 0 1 2 1 23 22 21 20 1 0 Page X, Word Y Page X, Word Y High-Impedance SO 7 6 5 4 3 2 1 0 CS 40 41 42 43 44 45 46 47 SCK SI Page X, Word Y+1 7 SO 6 FIGURE 2-4: 5 4 3 2 1 Page X, Word 31 0 7 6 5 4 3 2 Page X, Word 0 1 0 7 6 5 4 3 2 1 0 PAGE WRITE SEQUENCE (SPI MODE) CS 0 1 2 0 0 0 3 4 5
PAGE 8
23LCV1024 FIGURE 2-5: SEQUENTIAL READ SEQUENCE (SPI MODE) CS 0 1 2 0 0 0 3 4 5 6 7 8 9 10 11 29 30 31 32 33 34 35 36 37 38 39 SCK Instruction SI 0 0 24-bit Address 0 1 1 23 22 21 20 2 1 0 Page X, Word Y 7 SO 6 5 4 3 2 1 0 CS SCK SI Page X, Word 31 SO 7 6 5 4 3 2 Page X+1, Word 0 1 0 7 6 5 4 3 2 1 Page X+1, Word 1 0 7 6 5 4 3 2 1 0 CS SCK SI Page X+1, Word 31 SO 7 DS25156A-page 8 6 5 4 3 2 Page X+n, Word 1 1 0 7 6 5 4 3 2 Preliminary
PAGE 9
23LCV1024 FIGURE 2-6: SEQUENTIAL WRITE SEQUENCE (SPI MODE) CS 0 1 2 3 4 5 6 7 8 9 10 11 29 30 31 32 33 34 35 36 37 38 39 SCK Instruction SI 0 0 0 0 0 24-bit Address 0 1 Data Byte 1 2 0 23 22 21 20 1 0 7 6 5 4 3 2 1 0 CS 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 SCK Data Byte 2 SI 7 6 5 4  2012 Microchip Technology Inc.
PAGE 10
23LCV1024 2.5 Read Mode Register Instruction (RDMR) The mode bits indicate the operating mode of the SRAM. The possible modes of operation are: 0 0 = Byte mode The Read Mode Register instruction (RDMR) provides access to the MODE register. The MODE register may be read at any time. The MODE register is formatted as follows: TABLE 2-2: 1 0 = Page mode 0 1 = Sequential mode (default operation) 1 1 = Reserved Bits 0 through 5 are reserved and should always be set to ‘0’.
PAGE 11
23LCV1024 2.6 Write Mode Register Instruction (WRMR) The Write Mode Register instruction (WRMR) allows the user to write to the bits in the MODE register as shown in Table 2-2. This allows for setting of the Device operating mode. Several of the bits in the MODE register must be cleared to ‘0’. See Figure 2-8 for the WRMR timing sequence.
PAGE 12
23LCV1024 3.0 PIN DESCRIPTIONS 3.6 The descriptions of the pins are listed in Table 3-1. TABLE 3-1: Name The VBAT pin is used as an input for external backup supply to maintain SRAM data when VCC is below the VTRIP point. If the VBAT function is not being used it is recommended to connect this pin to VSS. PIN FUNCTION TABLE SOIC/ PDIP TSSOP VBAT Supply Input Function 3.
PAGE 13
23LCV1024 4.0 DUAL SERIAL MODE 4.1 The 23LCV1024 supports SDI (Serial Dual) mode of operation. To enter SDI mode the EDIO command must be clocked in (Figure 4-1). It should be noted that if the MCU resets before the SRAM, the user will need to determine the serial mode of operation of the SRAM and reset it accordingly. Byte read and write sequence in SDI mode is shown in Figure 4-2 and Figure 4-3. The 23LCV1024 also supports SDI (Serial Dual) mode of operation when used with compatible master devices.
PAGE 14
23LCV1024 FIGURE 4-3: BYTE WRITE MODE SDI CS 0 1 2 3 4 5 6 13 14 15 16 17 18 19 SCK SIO0 0 0 0 0 22 20 18 Instruction SIO1 Note: 4.2 0 0 0 4 2 0 6 5 2 0 Data In 24-Bit Address 1 23 21 19 4 3 1 7 5 3 1 Page and Sequential mode are similar in that additional bytes can be clocked in before CS is brought high. Exit SDI Mode To exit from SDI mode, the RSTIO command must be issued.
PAGE 15
23LCV1024 5.0 VBAT The VBAT trip point is the point at which the internal switch operates the device from the VBAT supply and is typically 1.8V (VTRIP specification D012). When VCC falls below the VTRIP point the system will continue to maintain the SRAM contents. The 23LCV1024 features an internal switch that will maintain the SRAM contents. In the event that the VCC supply is not available, the voltage applied to the VBAT pin serves as the backup supply.
PAGE 16
23LCV1024 6.0 PACKAGING INFORMATION 6.1 Package Marking Information 8-Lead PDIP (300 mil) Example XXXXXXXX XXXXXNNN 23LCVB I/P e3 1L7 0528 YYWW 8-Lead SOIC (3.90 mm) Example: XXXXXXXT XXXXYYWW NNN 23LCVBI SN e3 0528 1L7 Example: 8-Lead TSSOP 3LVB XXXX TYWW NNN Legend: XX...
PAGE 17
23LCV1024 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 N NOTE 1 E1 1 3 2 D E A2 A L A1 c e eB b1 b 6 &! ' ! 9 ' &! 7"') % ! 7,8. 7 7 & ; < & & 7: 1 , = = - 1 ! & & = = .
PAGE 18
23LCV1024 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS25156A-page 18 Preliminary  2012 Microchip Technology Inc.
PAGE 19
23LCV1024 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2012 Microchip Technology Inc.
PAGE 20
23LCV1024 ! "" #$ %& ! ' 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 DS25156A-page 20 Preliminary  2012 Microchip Technology Inc.
PAGE 21
23LCV1024 () )" * ! ( +%+ ( ! 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 D N E E1 NOTE 1 1 2 b e c A φ A2 A1 L L1 6 &! ' ! 9 ' &! 7"') % ! 99 . . 7 7 7: ; < & : 8 & = = < = # # 4 4 !! & # %% ? 1 , : > #& . # # 4 > #& .
PAGE 22
23LCV1024 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS25156A-page 22 Preliminary  2012 Microchip Technology Inc.
PAGE 23
LCV1024 APPENDIX A: REVISION HISTORY Revision A (09/2012) Initial release.  2012 Microchip Technology Inc.
PAGE 24
23LCV1024 NOTES: DS25156A-page 24 Preliminary  2012 Microchip Technology Inc.
PAGE 25
23LCV1024 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
PAGE 26
23LCV1024 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
PAGE 27
23LCV1024 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Not all possible ordering options are shown below.. PART NO. X Device Tape & Reel – X /XX Temp Range Package Examples: a) b) Device: 23LCV1024= 1 Mbit, 2.5 - 5.5V, SPI Serial SRAM Tape & Reel: Blank T = = Standard packaging (tube) Tape & Reel Temperature Range: I = -40C to+85C Package: SN ST P = = = Plastic SOIC (3.
PAGE 28
23LCV1024 NOTES: DS25156A-page 28 Preliminary  2012 Microchip Technology Inc.
PAGE 29
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PAGE 30
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