Datasheet

ManualsBrandsMicrochip ManualsEEPROMEEPROM 64KB 900ns PDIP

 2003 Microchip Technology Inc. DS21189H-page 1

24AA64/24LC64

Device Selection Table

Features

• Single supply with operation down to 1.8V

• Low-power CMOS technology

- 1 mA active current typical

-1µA standby current (max.) (I-temp)

• Organized as 8 blocks of 8K bit (64K bit)

• 2-wire serial interface bus, I

C™ compatible

• Cascadable for up to eight devices

• Schmitt Trigger inputs for noise suppression

• Output slope control to eliminate ground bounce

• 100 kHz (24AA64) and 400 kHz (24LC64)

compatibility

• Self-timed write cycle (including auto-erase)

• Page write buffer for up to 32 bytes

• 2 ms typical write cycle time for page write

• Hardware write-protect for entire memory

• Can be operated as a serial ROM

• Factory programming (QTP) available

• ESD protection > 4,000V

• 1,000,000 erase/write cycles

• Data retention > 200 years

• 8-lead PDIP, SOIC, TSSOP and MSOP packages

• Standard and Pb-free finishes available

• Available temperature ranges:

- Industrial (I): -40°C to +85°C

- Automotive (E): -40°C to +125°C

Description

The Microchip Technology Inc. 24AA64/24LC64

(24XX64*) is a 64 Kbit Electrically Erasable PROM.

The device is organized as eight blocks of 1K x 8-bit

memory with a 2-wire serial interface. Low-voltage

design permits operation down to 1.8V, with standby

and active currents of only 1 µA and 1 mA,

respectively. It has been developed for advanced, low-

power applications such as personal communications

or data acquisition. The 24XX64 also has a page write

capability for up to 32 bytes of data. Functional address

lines allow up to eight devices on the same bus, for up

to 512 Kbits address space. The 24XX64 is available in

the standard 8-pin PDIP, surface mount SOIC, TSSOP

and MSOP packages.

Package Types

Block Diagram

Part

Number

VCC

Range

Max Clock

Frequency

Temp

Ranges

24AA64 1.8-5.5 400 kHz

(1)

24LC64 2.5-5.5 400 kHz I, E

Note 1: 100 kHz for VCC <2.5V

24XX64

Vss

Vcc

SCL

SDA

PDIP/SOIC/TSSOP

24XX64X

Vcc

SCL

SDA

Vss

(24AA64X/24LC64X)

ROTATED TSSOP

/MSOP

EEPROM

Array

Page

YDEC

XDEC

Sense Amp.

Memory

Control

Logic

I/O

Control

Logic

I/O

SDA

SCL

VSS

R/W Control

Latches

Generator

64K I

™

Serial EEPROM

* 24XX64 is used in this document as a generic part number for the 24AA64/24LC64 devices.

Summary of content (27 pages)

PAGE 1
24AA64/24LC64 64K I2C™ Serial EEPROM Device Selection Table Description Part Number VCC Range Max Clock Frequency Temp Ranges 24AA64 1.8-5.5 400 kHz(1) I 24LC64 2.5-5.5 400 kHz I, E Note 1: 100 kHz for VCC <2.5V Features Package Types PDIP/SOIC/TSSOP /MSOP A2 3 Vss 4 ROTATED TSSOP (24AA64X/24LC64X) 8 Vcc WP 7 WP Vcc 6 SCL A0 5 SDA A1 1 2 3 4 24XX64X A0 1 A1 2 24XX64 • Single supply with operation down to 1.
PAGE 2
4AA64/24LC64 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (†) VCC .............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS ......................................................................................................... -0.3V to VCC +1.0V Storage temperature ...........................................................................
PAGE 3
24AA64/24LC64 TABLE 1-2: AC CHARACTERISTICS VCC = +1.8V to +5.5V Industrial (I): TA = -40°C to +85°C Automotive (E): TA = -40°C to +125°C AC CHARACTERISTICS Param. No. Sym Characteristic Min Max Units Conditions 1 FCLK Clock frequency — — 400 100 kHz 2.5V ≤ VCC ≤ 5.5V 1.8V ≤ VCC < 2.5V (24AA64) 2 THIGH Clock high time 600 4000 — — ns 2.5V ≤ VCC ≤ 5.5V 1.8V ≤ VCC < 2.5V (24AA64) 3 TLOW Clock low time 1300 4700 — — ns 2.5V ≤ VCC ≤ 5.5V 1.8V ≤ VCC < 2.
PAGE 4
24AA64/24LC64 FIGURE 1-1: BUS TIMING DATA 5 4 2 3 SCL 7 SDA IN 8 10 9 6 14 12 11 SDA OUT FIGURE 1-2: BUS TIMING START/STOP D4 SCL 6 7 10 SDA Start DS21189H-page 4 Stop  2003 Microchip Technology Inc.
PAGE 5
24AA64/24LC64 2.0 FUNCTIONAL DESCRIPTION The 24XX64 supports a bidirectional, 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as transmitter, while a device receiving data is defined as a receiver. The bus has to be controlled by a master device which generates the serial clock (SCL), controls the bus access and generates the Start and Stop conditions, while the 24XX64 works as slave.
PAGE 6
24AA64/24LC64 3.6 FIGURE 3-2: Device Addressing A control byte is the first byte received following the Start condition from the master device (Figure 3-2). The control byte consists of a four-bit control code. For the 24XX64, this is set as ‘1010’ binary for read and write operations. The next three bits of the control byte are the Chip Select bits (A2, A1, A0). The Chip Select bits allow the use of up to eight 24XX64 devices on the same bus and are used to select which device is accessed.
PAGE 7
24AA64/24LC64 4.0 WRITE OPERATIONS 4.1 Byte Write Following the Start condition from the master, the control code (four bits), the Chip Select (three bits) and the R/W bit (which is a logic low) are clocked onto the bus by the master transmitter. This indicates to the addressed slave receiver that the address high byte will follow once it has generated an Acknowledge bit during the ninth clock cycle.
PAGE 8
24AA64/24LC64 FIGURE 4-1: BYTE WRITE BUS ACTIVITY MASTER SDA LINE S T A CONTROL BYTE R T AA S1 0 1 0A 210 0 ADDRESS HIGH BYTE S T O P DATA XXX P A C K A C K A C K A C K BUS ACTIVITY ADDRESS LOW BYTE X = don’t care bit FIGURE 4-2: PAGE WRITE S T BUS ACTIVITY A CONTROL BYTE MASTER R T AA SDA LINE S 10 1 0A 2100 BUS ACTIVITY ADDRESS HIGH BYTE ADDRESS LOW BYTE DATA BYTE 0 S T O P DATA BYTE 31 XXX A C K P A C K A C K A C K A C K X = don’t care bit DS21189H-page 8  2003 Microchip T
PAGE 9
24AA64/24LC64 5.0 ACKNOWLEDGE POLLING Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the Stop condition for a Write command has been issued from the master, the device initiates the internally-timed write cycle and ACK polling can then be initiated immediately. This involves the master sending a Start condition followed by the control byte for a Write command (R/W = 0).
PAGE 10
24AA64/24LC64 6.0 READ OPERATION Read operations are initiated in the same way as write operations, with the exception that the R/W bit of the control byte is set to one. There are three basic types of read operations: current address read, random read, and sequential read. 6.1 Current Address Read The 24XX64 contains an address counter that maintains the address of the last word accessed, internally incremented by one.
PAGE 11
24AA64/24LC64 FIGURE 6-2: RANDOM READ S BUS ACTIVITY T MASTER A CONTROL R BYTE T AA SDA LINE S1 0 1 0A 2100 ADDRESS HIGH BYTE ADDRESS LOW BYTE CONTROL BYTE A C K A C K P N O A C K A C K X = Don’t Care Bit FIGURE 6-3: S T O P DATA BYTE S 1 0 1 0 A A A1 210 XXX A C K BUS ACTIVITY S T A R T SEQUENTIAL READ BUS ACTIVITY CONTROL MASTER BYTE DATA n DATA n + 1 DATA n + 2 DATA n + X SDA LINE BUS ACTIVITY  2003 Microchip Technology Inc.
PAGE 12
24AA64/24LC64 7.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 7-1. TABLE 7-1: PIN FUNCTION TABLE Name PDIP SOIC TSSOP MSOP ROTATED TSSOP A0 1 1 1 1 3 Chip Address Input A1 2 2 2 2 4 Chip Address Input A2 3 3 3 3 5 Chip Address Input VSS 4 4 4 4 6 Ground SDA 5 5 5 5 7 Serial Address/Data I/O 7.1 SCL 6 6 6 6 8 Serial Clock WP 7 7 7 7 1 Write-Protect Input VCC 8 8 8 8 2 +1.8V to 5.
PAGE 13
24AA64/24LC64 8.0 PACKAGING INFORMATION 8.
PAGE 14
24AA64/24LC64 8-Lead Plastic Dual In-line (P) – 300 mil (PDIP) E1 D 2 n 1 α E A2 A L c A1 β B1 p eB B Units Dimension Limits n p Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D L c § B1 B e
PAGE 15
24AA64/24LC64 8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 α h 45° c A2 A φ β L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D h L φ c B α β MIN .053 .052 .004 .228 .146 .189 .010 .
PAGE 16
24AA64/24LC64 8-Lead Plastic Small Outline (SM) – Medium, 208 mil (SOIC) E E1 p D 2 1 n B α c A2 A φ β L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom A A2 A1 E E1 D L φ c B α β MIN .070 .069 .002 .300 .201 .202 .020 0 .008 .014 0 0 INCHES* NOM 8 .050 .075 .074 .005 .313 .208 .205 .025 4 .009 .
PAGE 17
24AA64/24LC64 8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP) E E1 p D 2 1 n B α A c φ β A1 A2 L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Molded Package Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D L φ c B α β MIN INCHES NOM MAX 8 .026 .033 .002 .246 .169 .114 .
PAGE 18
24AA64/24LC64 8-Lead Plastic Micro Small Outline Package (MS) (MSOP) E E1 p D 2 B n 1 α A2 A c φ A1 (F) L β Units Dimension Limits n p MIN INCHES NOM MAX MILLIMETERS* NOM 8 0.65 BSC 0.75 0.85 0.00 4.90 BSC 3.00 BSC 3.00 BSC 0.40 0.60 0.95 REF 0° 0.08 0.22 5° 5° - MIN 8 Number of Pins Pitch .026 BSC A .043 Overall Height A2 Molded Package Thickness .030 .033 .037 A1 .000 .006 Standoff E Overall Width .193 TYP. E1 .118 BSC Molded Package Width D .118 BSC Overall Length L .016 .024 .
PAGE 19
24AA64/24LC64 APPENDIX A: REVISION HISTORY Revision H Corrections to Section 1.0, Electrical Characteristics.  2003 Microchip Technology Inc.
PAGE 20
24AA64/24LC64 NOTES: DS21189H-page 20  2003 Microchip Technology Inc.
PAGE 21
24AA64/24LC64 ON-LINE SUPPORT Microchip provides on-line support on the Microchip World Wide Web site. The web site is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape® or Microsoft® Internet Explorer. Files are also available for FTP download from our FTP site.
PAGE 22
24AA64/24LC64 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
PAGE 23
24AA64/24LC64 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X /XX Temperature Package Range X Lead Finish Examples: a) b) Device: 1.8V, 64 Kbit I2C Serial EEPROM 1.8V, 64 Kbit I2C Serial EEPROM (Tape and Reel) 24AA64X 1.8V, 64 Kbit I2C Serial EEPROM in rotated pinout (ST only) 24AA64XT 1.8V, 64 Kbit I2C Serial EEPROM in rotated pinout (ST only) 24LC64: 2.
PAGE 24
AA64/24LC64 NOTES: DS21189H-page 24  2003 Microchip Technology Inc.
PAGE 25
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PAGE 26
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PAGE 27
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