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25LC1024

Device Selection Table

Features:

• 20 MHz max. Clock Speed

• Byte and Page-level Write Operations:

- 256 byte page

- 6 ms max. write cycle time

- No page or sector erase required

• Low-Power CMOS Technology:

- Max. Write current: 5 mA at 5.5V, 20 MHz

- Read current: 7 mA at 5.5V, 20 MHz

- Standby current: 1μA at 2.5V

(Deep power-down)

• Electronic Signature for Device ID

• Self-Timed Erase and Write Cycles:

- Page Erase (6 ms max.)

- Sector Erase (10 ms max.)

- Chip Erase (10 ms max.)

• Sector Write Protection (32K byte/sector):

- Protect none, 1/4, 1/2 or all of array

• Built-In Write Protection:

- Power-on/off data protection circuitry

- Write enable latch

- Write-protect pin

• High Reliability:

- Endurance: 1M erase/write cycles

- Data Retention: >200 years

- ESD Protection: >4000V

• Temperature Ranges Supported:

• Pb-free and RoHS Compliant

Pin Function Table

Description:

The Microchip Technology Inc. 25LC1024 is a 1024

Kbit serial EEPROM memory with byte-level and page-

level serial EEPROM functions. It also features Page,

Sector and Chip erase functions typically associated

with Flash-based products. These functions are not

required for byte or page write operations. The memory

is accessed via a simple Serial Peripheral Interface

(SPI) compatible serial bus. The bus signals required

are a clock input (SCK) plus separate data in (SI) and

data out (SO) lines. Access to the device is controlled

by a Chip Select (CS

) input.

Communication to the device can be paused via the

hold pin (HOLD

). While the device is paused, transi-

tions on its inputs will be ignored, with the exception of

Chip Select, allowing the host to service higher priority

interrupts.

The 25LC1024 is available in standard packages

including 8-lead PDIP and SOIJ, and advanced 8-lead

DFN package. All devices are Pb-free.

Package Types (not to scale)

Part Number VCC Range Page Size Temp. Ranges Packages

25LC1024 2.5-5.5V 256 Byte I,E P, SM, MF

- Industrial (I): -40°Cto +85°C

- Automotive (E): -40°C to +125°C

Name Function

Chip Select Input

SO Serial Data Output

Write-Protect

VSS Ground

SI Serial Data Input

SCK Serial Clock Input

HOLD

Hold Input

VCC Supply Voltage

25LC1024

HOLD

SCK

PDIP/SOIJ

(P, SM)

DFN

VSS

HOLD

SCK

25LC1024

VCC

(MF)

1 Mbit SPI Bus Serial EEPROM

Summary of content (32 pages)

PAGE 1
25LC1024 1 Mbit SPI Bus Serial EEPROM Device Selection Table Part Number VCC Range Page Size Temp. Ranges Packages 25LC1024 2.5-5.5V 256 Byte I,E P, SM, MF Features: Description: • 20 MHz max. Clock Speed • Byte and Page-level Write Operations: - 256 byte page - 6 ms max. write cycle time - No page or sector erase required • Low-Power CMOS Technology: - Max. Write current: 5 mA at 5.5V, 20 MHz - Read current: 7 mA at 5.5V, 20 MHz - Standby current: 1μA at 2.
PAGE 2
5LC1024 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (†) VCC .............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V Storage temperature ................................................................................
PAGE 3
25LC1024 TABLE 1-2: AC CHARACTERISTICS Industrial (I): Automotive (E): AC CHARACTERISTICS Param. No. Sym. Characteristic TA = -40°C to +85°C TA = -40°C to +125°C Min. Max. Units VCC = 2.5V to 5.5V VCC = 2.5V to 5.5V Conditions 1 FCLK Clock frequency — — 20 10 MHz MHz 4.5V ≤ VCC ≤ 5.5V (I) 2.5V ≤ VCC < 5.5V (I, E) 2 TCSS CS setup time 25 50 — — ns ns 4.5V ≤ VCC ≤ 5.5V (I) 2.5V ≤ VCC < 5.5V (I, E) 3 TCSH CS hold time 50 100 — — ns ns 4.5V ≤ VCC ≤ 5.5V (I) 2.5V ≤ VCC < 5.
PAGE 4
25LC1024 TABLE 1-2: AC CHARACTERISTICS (CONTINUED) Industrial (I): Automotive (E): AC CHARACTERISTICS Param. No. 25 Sym. — Characteristic Endurance TA = -40°C to +85°C TA = -40°C to +125°C Min. Max. 1M — Units VCC = 2.5V to 5.5V VCC = 2.5V to 5.5V Conditions E/W (Note 2) Per Page Cycles Note 1: This parameter is periodically sampled and not 100% tested. 2: This parameter is not tested but established by characterization and qualification.
PAGE 5
25LC1024 FIGURE 1-1: HOLD TIMING CS 17 16 17 16 SCK 18 SO n+2 SI n+2 n+1 n 19 High-Impedance n 5 Don’t Care n+1 n-1 n n n-1 HOLD FIGURE 1-2: SERIAL INPUT TIMING 4 CS 2 7 Mode 1,1 12 11 8 3 SCK Mode 0,0 5 SI 6 MSB in LSB in High-Impedance SO FIGURE 1-3: SERIAL OUTPUT TIMING CS 9 3 10 Mode 1,1 SCK Mode 0,0 13 14 SO MSB out SI © 2008 Microchip Technology Inc.
PAGE 6
25LC1024 2.0 FUNCTIONAL DESCRIPTION 2.1 Principles of Operation BLOCK DIAGRAM STATUS Register The 25LC1024 is a 131,072 byte Serial EEPROM designed to interface directly with the Serial Peripheral Interface (SPI) port of many of today’s popular microcontroller families, including Microchip’s PIC® microcontrollers. It may also interface with microcontrollers that do not have a built-in SPI port by using discrete I/O lines programmed properly in firmware to match the SPI protocol.
PAGE 7
25LC1024 Read Sequence The device is selected by pulling CS low. The 8-bit READ instruction is transmitted to the 25LC1024 followed by the 24-bit address, with seven MSBs of the address being “don’t care” bits. After the correct READ instruction and address are sent, the data stored in the memory at the selected address is shifted out on the SO pin. FIGURE 2-1: The data stored in the memory at the next address can be read sequentially by continuing to provide clock pulses.
PAGE 8
25LC1024 2.2 Write Sequence Prior to any attempt to write data to the 25LC1024, the write enable latch must be set by issuing the WREN instruction (Figure 2-4). This is done by setting CS low and then clocking out the proper instruction into the 25LC1024. After all eight bits of the instruction are transmitted, the CS must be brought high to set the write enable latch.
PAGE 9
25LC1024 FIGURE 2-3: PAGE WRITE SEQUENCE CS 0 1 2 0 0 0 3 4 5 6 7 8 9 10 11 29 30 31 32 33 34 35 36 37 38 39 SCK Instruction SI 0 0 24-bit Address 0 1 0 23 22 21 20 Data Byte 1 2 1 0 7 6 5 4 3 2 1 0 CS 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 SCK Data Byte 2 SI 7 6 5 4 © 2008 Microchip Technology Inc.
PAGE 10
25LC1024 2.3 Write Enable (WREN) and Write Disable (WRDI) The following is a list of conditions under which the write enable latch will be reset: • • • • • • • The 25LC1024 contains a write enable latch. See Table 2-4 for the Write-Protect Functionality Matrix. This latch must be set before any write operation will be completed internally. The WREN instruction will set the latch, and the WRDI will reset the latch.
PAGE 11
25LC1024 2.4 Read Status Register Instruction (RDSR) The Write Enable Latch (WEL) bit indicates the status of the write enable latch and is read-only. When set to a ‘1’, the latch allows writes to the array, when set to a ‘0’, the latch prohibits writes to the array. The state of this bit can always be updated via the WREN or WRDI commands regardless of the state of write protection on the STATUS register. These commands are shown in Figure 2-4 and Figure 2-5.
PAGE 12
25LC1024 2.5 Write Status Register Instruction (WRSR) The Write-Protect Enable (WPEN) bit is a nonvolatile bit that is available as an enable bit for the WP pin. The Write-Protect (WP) pin and the Write-Protect Enable (WPEN) bit in the STATUS register control the programmable hardware write-protect feature. Hardware write protection is enabled when WP pin is low and the WPEN bit is high. Hardware write protection is disabled when either the WP pin is high or the WPEN bit is low.
PAGE 13
25LC1024 2.6 Data Protection 2.
PAGE 14
25LC1024 2.8 PAGE ERASE The Page Erase function will erase all bits (FFh) inside the given page. A Write Enable (WREN) instruction must be given prior to attempting a Page Erase. This is done by setting CS low and then clocking out the proper instruction into the 25LC1024. After all eight bits of the instruction are transmitted, the CS must be brought high to set the write enable latch. CS must then be driven high after the last bit if the address or the Page Erase will not execute.
PAGE 15
25LC1024 2.9 SECTOR ERASE CS must then be driven high after the last bit if the address or the Sector Erase will not execute. Once the CS is driven high, the self-timed Sector Erase cycle is started. The WIP bit in the STATUS register can be read to determine when the Sector Erase cycle is complete. The Sector Erase function will erase all bits (FFh) inside the given sector. A Write Enable (WREN) instruction must be given prior to attempting a Sector Erase.
PAGE 16
25LC1024 2.10 CHIP ERASE The Chip Erase function will erase all bits (FFh) in the array. A Write Enable (WREN) instruction must be given prior to executing a Chip Erase. This is done by setting CS low and then clocking out the proper instruction into the 25LC1024. After all eight bits of the instruction are transmitted, the CS must be brought high to set the write enable latch.
PAGE 17
25LC1024 2.11 DEEP POWER-DOWN MODE Deep Power-Down mode of the 25LC1024 is its lowest power consumption state. The device will not respond to any of the Read or Write commands while in Deep Power-Down mode, and therefore it can be used as an additional software write protection feature. All instructions given during Deep Power-Down mode are ignored except the Read Electronic Signature Command (RDID).
PAGE 18
25LC1024 2.12 RELEASE FROM DEEP POWER-DOWN AND READ ELECTRONIC SIGNATURE Release from Deep Power-Down mode and Read Electronic Signature is entered by driving CS low, followed by the RDID instruction code (Figure 2-12) and then a dummy address of 24 bits (A23-A0). After the last bit of the dummy address is clocked in, the 8-bit Electronic signature is clocked out on the SO pin.
PAGE 19
25LC1024 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 3-1. TABLE 3-1: PIN FUNCTION TABLE Name Pin Number CS 1 Chip Select Input SO 2 Serial Data Output WP 3 Write-Protect Pin VSS 4 Ground SI 5 Serial Data Input SCK 6 Serial Clock Input HOLD 7 Hold Input VCC 8 Supply Voltage The WP pin function is blocked when the WPEN bit in the STATUS register is low.
PAGE 20
25LC1024 4.0 PACKAGING INFORMATION 4.1 Package Marking Information 8-Lead DFN XXXXXXX T/XXXXX YYWW NNN 5LC1024 I/MF e3 0328 1L7 8-Lead PDIP Example: XXXXXXXX T/XXXNNN YYWW 25LC1024 I/P e3 1L7 0328 8-Lead SOIJ Example: XXXXXXXX T/XXXXXX YYWWNNN 25LC1024 I/SM e3 07281L7 Legend: XX...
PAGE 21
25LC1024 $ ! "# 3 & ' !& " & + && 244*** ' '4 # * !( + ! ! & + % & & # & e D L b N N K E2 E EXPOSED PAD NOTE 1 1 2 2 NOTE 1 1 D2 BOTTOM VIEW TOP VIEW A A3 A1 NOTE 2 5 &! ' ! 6 ' &! 7"') % ! 66 - - 7 7 ; & 9 : & 8 78 0 1 : :/ & # %% / 1 & & + !! ,
PAGE 22
25LC1024 $ 3 & ' !& " & + && 244*** ' '4 DS22064B-page 22 # * !( + ! ! & + % & & # & © 2008 Microchip Technology Inc.
PAGE 23
25LC1024 $ %& & '(( ! % # 3 & ' !& " & + && 244*** ' '4 # * !( + ! ! & + % & & # & N NOTE 1 E1 1 3 2 D E A2 A L A1 c e eB b1 b 5 &! ' ! 6 ' &! 7"') % ! 71;- 7 7 78 9 : & 0 1 & & > > / , / / > > " # & " # < #& - , , / # # + - / : , : , /
PAGE 24
25LC1024 $ " ) & " *+ !")%,# 3 & ' !& " & + && 244*** ' '4 # * !( + ! ! & + % & & # & D N E E1 1 2 e b α A2 A c φ β A1 5 &! ' ! 6 ' &! 7"') % ! 66 - - 7 7 + !! & # %% ? 8 9 0 1 ; & # # + 78 : & 8 L < #& > / > , : / > / : - > - / > / ,: / , > /
PAGE 26
25LC1024 APPENDIX A: REVISION HISTORY Revision A (10/2007) Original release. Revision B (5/2008) Modified parameter D006 in Table 1-1; Revised Package Marking Information; Replaced Package Drawings. DS22064B-page 26 © 2008 Microchip Technology Inc.
PAGE 27
25LC1024 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
PAGE 28
25LC1024 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
PAGE 29
25LC1024 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X Device Tape & Reel – X /XX Temp Range Package Examples: a) b) Device: 25LC1024 1 Mbit, 2.
PAGE 31
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PAGE 32
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