Datasheet

17
1921D–MICRO–6/08
AT89C55WD
The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the timers
overflow. The values are then polled by the circuitry in the next cycle. However, the Timer 2 flag,
TF2, is set at S2P2 and is polled in the same cycle in which the timer overflows.
Figure 15-1. Interrupt Sources
Table 15-1. Interrupt Enable (IE) Register
(MSB) (LSB)
EA – ET2 ES ET1 EX1 ET0 EX0
Enable Bit = 1 enables the interrupt.
Enable Bit = 0 disables the interrupt.
Symbol Position Function
EA IE.7
Disables all interrupts. If EA = 0, no interrupt is acknowledged. If EA
= 1, each interrupt source is individually enabled or disabled by
setting or clearing its enable bit.
– IE.6 Reserved.
ET2 IE.5 Timer 2 interrupt enable bit.
ES IE.4 Serial Port interrupt enable bit.
ET1 IE.3 Timer 1 interrupt enable bit.
EX1 IE.2 External interrupt 1 enable bit.
ET0 IE.1 Timer 0 interrupt enable bit.
EX0 IE.0 External interrupt 0 enable bit.
User software should never write 1s to reserved bits, because they may be used in future AT89
products.
IE1
IE0
1
1
0
0
TF1
TF0
INT1
INT0
TI
RI
TF2
EXF2