Datasheet

25
1921D–MICRO–6/08
AT89C55WD
23. Flash Programming and Verification Waveforms
24. Lock Bit Programming
25. Parallel Chip Erase Mode
t
GLGH
t
GHSL
t
AVGL
t
SHGL
t
DVGL
t
GHAX
t
AVQV
t
GHDX
t
EHSH
t
ELQV
t
WC
BUSY
READY
t
GHBL
t
EHQZ
P1.0 - P1.7
P2.0 - P2.5
P3.4
ALE/PROG
PORT 0
LOGIC 1
LOGIC 0
EA/V
PP
V
PP
P2.7
(ENABLE)
P3.0
(RDY/BSY)
PROGRAMMING
ADDRESS
VERIFICATION
ADDRESS
DATA I N
DATA O UT
Test Conditions
Setup
Lockbit_1, 2 or 3
Data Setup
ALE/PROG
V
CC
= 6.5V
V
CC
= 4.5V to 5.5V
Wait 10 ms to reload
new lock bit status
100 µs
10 ms
Test Conditions
Setup
Test Conditions Setup
ALE/PROG
P3<0>
Erase
DC
Erase
Erase
V
CC
= 4.5V to 5.5V
Wait 10 ms before
reprogramming
V
CC
= 6.5V
DC
Erase
200 ns
200 ns