SAM3X / SAM3A Series Atmel | SMART ARM-based MCU DATASHEET Description The Atmel | SMART SAM3X/A series is a member of a family of Flash microcontrollers based on the high performance 32-bit ARM Cortex-M3 RISC processor. It operates at a maximum speed of 84 MHz and features up to 512 Kbytes of Flash and up to 100 Kbytes of SRAM.
1. 2 Features Core ̶ ARM Cortex-M3 revision 2.0 running at up to 84 MHz ̶ Memory Protection Unit (MPU) ̶ Thumb-2 instruction set ̶ 24-bit SysTick Counter ̶ Nested Vector Interrupt Controller Memories ̶ 256 to 512 Kbytes embedded Flash, 128-bit wide access, memory accelerator, dual bank ̶ 32 to 100 Kbytes embedded SRAM with dual banks ̶ 16 Kbytes ROM with embedded bootloader routines (UART, USB) and IAP routines ̶ Static Memory Controller (SMC): SRAM, NOR, NAND support.
1.1 Packages ̶ 100-lead LQFP – 14 x 14 mm, pitch 0.5 mm ̶ 100-ball TFBGA – 9 x 9 mm, pitch 0.8 mm ̶ 144-lead LQFP – 20 x 20 mm, pitch 0.5 mm ̶ 144-ball LFBGA – 10 x 10 mm, pitch 0.8 mm Configuration Summary The SAM3X/A series devices differ in memory sizes, package and features list. Table 1-1 summarizes the configurations. Table 1-1.
SAM3X/A Block Diagram ND NA AN A G DA VD N DO DI VD VD UT SAM3A4/8C (100 pins) Block Diagram TD TDI O TM /TR S A TC /SW CE K/ D SW SW IO O CL K Figure 2-1. JT AG SE L 2.
DO UT VD DA G N ND A AN A VD VD DI N JT AG SE L TD TDI O TM /TR S A TC /SW CE K/ D SW SW IO O CL K SAM3X4/8C (100 pins) Block Diagram Voltage Regulator System Controller TST PCK0-PCK2 JTAG & Serial Wire PLLA UPLL XIN XOUT PMC OSC 12M In-circuit Emulator 24-bit N Cortex-M3 Processor SysTick Counter V fmax 84 MHz I C WDT RC 12/8/4 M SM MPU SUPC FWUP XIN32 XOUT32 I/D OSC 32K Flash 2x256 Kbytes 2x128 Kbytes 2x64 Kbytes SRAM1 SRAM0 ROM 64 Kbytes 32 Kbytes 32 Kbytes 32 Kbytes 16 Kbytes 16
UT D G AN ND A AN A DO VD VD JT VD AG DI N SE L SAM3X4/8E (144 pins) Block Diagram TD I TD O TM /TR S AC TC /SW ES K/ D I W SW O O CL K Figure 2-3.
N ND A AN A UT G DA VD DO DI VD VD N JT AG SE L TD I TD O TM /TR S A TC /S CE K/ WD SW SW IO O CL K SAM3X8H (217 pins) Block Diagram (not commercially available) Voltage Regulator System Controller TST PCK0-PCK2 JTAG & Serial Wire PLLA UPLL XIN XOUT PMC In-Circuit Emulator OSC WDT RC 12/8/4 M SHDN FWUP XIN32 XOUT32 SM 24-bit N Cortex-M3 Processor SysTick Counter V fmax 84 MHz I C MPU SUPC I/D OSC 32K Flash SRAM0 2x256 Kbytes 2x128 Kbytes 2x64 Kbytes 64 Kbytes 32 Kbytes 16 Kbytes
3. Signal Description Table 3-1 gives details on the signal names classified by peripheral. Table 3-1. Signal Description List Signal Name Function Type Active Level Voltage Reference Comments Power Supplies VDDIO Peripherals I/O Lines Power Supply Power 1.62V to 3.6V VDDUTMI USB UTMI+ Interface Power Supply Power 3.0V to 3.
Table 3-1.
Table 3-1.
Table 3-1.
Table 3-1.
4. 5. 6. 7. 3.1 PIOC: Schmitt Trigger on all, except PC2 to PC9, PC15 to PC24 PIOD: Schmitt Trigger on all, except PD10 to PD30 PIOE: Schmitt Trigger on all, except PE0 to PE4, PE15, PE17, PE19, PE21, PE23, PE25, PE29 PIOF: Schmitt Trigger on all PIOs Design Considerations To facilitate schematic capture when using a SAM3X/A design, refer to the application note Atmel AT03462: ATSAM3X and ATSAM3A Series - Checklist (literature No. 42187) available on www.atmel.com.
4. Package and Pinout 4.1 SAM3A4/8C and SAM3X4/8C Package and Pinout The SAM3A4/8C and SAM3X4/8C are available in 100-lead LQFP and 100-ball TFBGA packages. 4.1.1 100-lead LQFP Package Outline Figure 4-1. Orientation of the 100-lead LQFP Package 51 75 76 50 100 26 25 1 4.1.2 100-ball TFBGA Package Outline Figure 4-2.
4.1.3 100-lead LQFP Pinout Table 4-1.
4.1.4 100-ball TFBGA Pinout Table 4-2.
4.2 SAM3X4/8E Package and Pinout The SAM3X4/8E is available in 144-lead LQFP and 144-ball LFBGA packages. 4.2.1 144-lead LQFP Package Outline Figure 4-3. Orientation of the 144-lead LQFP Package 73 108 109 72 144 37 36 1 4.2.2 144-ball LFBGA Package Outline The 144-ball LFBGA package has a 0.8 mm ball pitch and respects Green Standards. Its dimensions are 10 x 10 x 1.4 mm. Figure 4-4.
4.2.3 144-lead LQFP Pinout Table 4-3.
4.2.4 144-ball LFBGA Pinout Table 4-4.
5. Power Considerations 5.1 Power Supplies The SAM3X/A series product has several types of power supply pins: VDDCORE pins: Power the core, the embedded memories and the peripherals; voltage ranges from 1.62V to 1.95V. VDDIO pins: Power the peripherals I/O lines; voltage ranges from 1.62V to 3.6V. VDDIN pin: Powers the voltage regulator VDDOUT pin: Output of the voltage regulator VDDBU pin: Powers the Slow Clock oscillator and a part of the System Controller; voltage ranges from 1.
Figure 5-1. VDDCORE and VDDIO Constraints at Startup Supply (V) VDDIO VDDIO(min) VDDCORE VDDCORE(min) VT+ Time (t) tRST Core supply POR output SLCK 5.2.2 VDDIO Versus VDDIN At power-up, VDDIO needs to reach 0.6 V before VDDIN reaches 1.0 V. VDDIO voltage needs to be equal to or below (VDDIN voltage + 0.5 V). 5.3 Voltage Regulator The SAM3X/A series embeds a voltage regulator that is managed by the Supply Controller.
5.4 Typical Powering Schematics The SAM3X/A series supports a 1.62–3.6 V single supply mode. The internal regulator input connected to the source and its output feeds VDDCORE. Figure 5-2 shows the power schematics. Figure 5-2. Single Supply VDDBU VDDUTMI VDDANA VDDIO Main Supply (1.62–3.6 V) VDDIN Voltage Regulator VDDOUT VDDCORE VDDPLL Note: 22 Restrictions For USB, VDDUTMI needs to be greater than 3.0V. For ADC, VDDANA needs to be greater than 2.0V. For DAC, VDDANA needs to be greater than 2.
Figure 5-3. Core Externally Supplied VDDBU VDDUTMI VDDANA Main Supply (1.62–3.6 V) VDDIO VDDIN Voltage Regulator VDDOUT VDDCORE Supply (1.62–1.95 V) VDDCORE VDDPLL Note: Restrictions For USB, VDDUTMI needs to be greater than 3.0V. For ADC, VDDANA needs to be greater than 2.0V. For DAC, VDDANA needs to be greater than 2.4V.
Figure 5-4. Backup Batteries Used FWUP SHDN Backup Batteries VDDBU VDDUTMI VDDANA VDDIO VDDIN Main Supply (1.62–3.6 V) Voltage Regulator VDDOUT VDDCORE VDDPLL Note: 1. 2. 24 Restrictions For USB, VDDUTMI needs to be greater than 3.0V. For ADC, VDDANA needs to be greater than 2.0V. For DAC, VDDANA needs to be greater than 2.4V. VDDUTMI and VDDANA cannot be left unpowered.
5.5 Active Mode Active mode is the normal running mode with the core clock running from the fast RC oscillator, the main crystal oscillator or the PLLA. The power management controller can be used to adapt the frequency and to disable the peripheral clocks. 5.6 Low Power Modes The SAM3X/A devices provide the following low-power modes: Backup, Wait, and Sleep. 5.6.
Note: 5.6.3 Internal Main clock resynchronization cycles are necessary between the writing of MOSCRCEN bit and the effective entry in Wait mode. Depending on the user application, Waiting for MOSCRCEN bit to be cleared is recommended to ensure that the core will not execute undesired instructions. Sleep Mode The purpose of sleep mode is to optimize power consumption of the device versus response time. In this mode, only the core clock is stopped. The peripheral clocks can be enabled.
Table 5-1.
5.7 Wake-up Sources The wake-up events allow the device to exit the backup mode. When a wake-up event is detected, the Supply Controller performs a sequence which automatically reenables the core power supply. See Figure 16-7, "Wake Up Source" on page 277. 5.8 Fast Startup The SAM3X/A series allows the processor to restart in a few microseconds while the processor is in wait mode. A fast start up can occur upon detection of a low level on one of the 19 wake-up inputs (WKUP0–15 + RTC + RTT + USB).
6.2 System I/O Lines Table 6-1 lists the SAM3X/A system I/O lines shared with PIO lines. These pins are software configurable as general purpose I/O or system pins. At startup, the default function of these pins is always used. Table 6-1. System I/O Configuration Pin List CCFG_SYSIO Bit No.
6.4 NRST Pin The NRST pin is bidirectional. It is handled by the on-chip reset controller and can be driven low to provide a reset signal to the external components, or asserted low externally to reset the microcontroller. It will reset the Core and the peripherals except the Backup region (RTC, RTT and Supply Controller). There is no constraint on the length of the reset pulse, and the reset controller can guarantee a minimum pulse length.
7. Memories 7.1 Product Mapping Figure 7-1.
7.2 Embedded Memories 7.2.1 Internal SRAM Table 7-1 shows the embedded high-speed SRAM for the various devices. Table 7-1. Embedded High-speed SRAM per Device Device Pin Count SRAM0 (KB) SRAM1 (KB) NFC SRAM (KB) Total SRAM (KB) 144 64 32 4 100 100 64 32 – 96 144 32 32 4 68 100 32 32 – 64 SAM3X8E SAM3X8H(1) SAM3A8C SAM3X8C SAM3X4E SAM3A4C SAM3X4C Note: 1. This device is not commercially available. Mounted only on the SAM3X-EK evaluation kit.
7.2.3.3 Enhanced Embedded Flash Controller The Enhanced Embedded Flash Controller (EEFC) manages accesses performed by the masters of the system. It enables reading the Flash and writing the write buffer. It also contains a User Interface, mapped within the Memory Controller on the APB. The EEFC ensures the interface of the Flash block with the 32-bit internal bus. Its 128-bit wide memory interface increases performance.
7.2.3.8 Fast Flash Programming Interface (FFPI) The FFPI allows device programming through multiplexed fully-handshaked parallel port. It allows gang programming with market-standard industrial programmers. The FFPI supports read, page program, page erase, full erase, lock, unlock and protect commands. The FFPI is enabled and the Fast Programming Mode is entered when TST, PA0, PA1 are set to high, PA2 and PA3 are set to low and NRST is toggled from 0 to 1.
7.2.3.10 GPNVM Bits The SAM3X/A series features three GPNVM bits that can be cleared or set respectively through the “Clear GPNVM Bit” and “Set GPNVM Bit” commands of the EEFC0 User Interface. There is no GPNVM bit on Flash 1. The GPNVM0 is the security bit. The GPNVM1 is used to select the boot mode (boot always at 0x00) on ROM or Flash. The GPNVM2 is used only to swap the Flash 0 and Flash 1. If GPNVM2 is ENABLE, the Flash 1 is mapped at address 0x0008_0000 (Flash 1 and Flash 0 are continuous).
Multiple device adaptability ̶ 7.3.3 7.3.
8. System Controller The System Controller is a set of peripherals which allow handling of key elements of the system such as but not limited to power, resets, clocks, time, interrupts, and watchdog. The System Controller User Interface also embeds the registers allowing to configure the Matrix and a set of registers configuring the SDR-SDRAM chip select assignment. 8.1 System Controller and Peripherals Mapping Please refer to Figure 7-1 “SAM3X/A Product Mapping” on page 31 .
9. Peripherals 9.1 Peripheral Identifiers Table 9-1 defines the Peripheral Identifiers of the SAM3X/A series. A peripheral identifier is required for the control of the peripheral interrupt with the Nested Vectored Interrupt Controller and for the control of the peripheral clock with the Power Management Controller. Note that some peripherals are always clocked. Please refer to the table below. Table 9-1.
Table 9-1.
9.3.1 PIO Controller A Multiplexing Table 9-2.
9.3.2 PIO Controller B Multiplexing Table 9-3.
5. DAC0 is selected when DACC_CHER.CH0 is set. DAC1 is selected when DACC_CHER.CH1 is set. See Section 44.7.3 “DACC Channel Enable Register”. 6. WKUPx can be used if PIO controller defines the I/O line as "input".
9.3.3 PIO Controller C Multiplexing Table 9-4.
9.3.4 PIO Controller D Multiplexing Table 9-5.
9.3.5 PIO Controller E Multiplexing Table 9-6.
9.3.6 PIO Controller F Multiplexing Table 9-7.
10. ARM Cortex® M3 Processor 10.1 About this section This section provides the information required for application and system-level software development. It does not provide information on debug components, features, or operation. This material is for microcontroller software and hardware engineers, including those who have no experience of ARM products. Note: The information in this section is reproduced from source material provided to Atmel by ARM Ltd.
Figure 10-1. Typical Cortex-M3 implementation Cortex-M3 Processor NVIC Debug Access Port Processor Core Memory Protection Unit Flash Patch Serial Wire Viewer Data Watchpoints Bus Matrix Code Interface SRAM and Peripheral Interface The Cortex-M3 processor is built on a high-performance processor core, with a 3-stage pipeline Harvard architecture, making it ideal for demanding embedded applications.
10.3.2 Integrated configurable debug The Cortex-M3 processor implements a complete hardware debug solution. This provides high system visibility of the processor and memory through either a traditional JTAG port or a 2-pin Serial Wire Debug (SWD) port that is ideal for microcontrollers and other small package devices. For system trace the processor integrates an Instrumentation Trace Macrocell (ITM) alongside data watchpoints and a profiling unit.
10.4 Programmers model This section describes the Cortex-M3 programmers model. In addition to the individual core register descriptions, it contains information about the processor modes and privilege levels for software execution and stacks. 10.4.1 Processor mode and privilege levels for software execution The processor modes are: 10.4.1.1 Thread mode Used to execute application software. The processor enters Thread mode when it comes out of reset. 10.4.1.2 Handler mode Used to handle exceptions.
10.4.3 Core registers The processor core registers are: ? @ QY\^` ^ Qjq @ ! @q ! ! ;Q@q } @ Q{ `@ Q{ Q ` " # $ %#' * # $ <|j ^ @ {Q q ^ j QY ;# < " =>* = Table 10-2.
10.4.3.1 General-purpose registers R0-R12 are 32-bit general-purpose registers for data operations. 10.4.3.2 Stack Pointer The Stack Pointer (SP) is register R13. In Thread mode, bit[1] of the CONTROL register indicates the stack pointer to use: 0 = Main Stack Pointer (MSP). This is the reset value. 1 = Process Stack Pointer (PSP). On reset, the processor loads the MSP with the value from address 0x00000000. 10.4.3.3 Link Register The Link Register (LR) is register R14.
• EPSR: 31 30 29 28 27 26 Reserved 23 22 25 24 ICI/IT 21 20 T 19 18 17 16 11 10 9 8 Reserved 15 14 13 12 ICI/IT 7 6 5 Reserved 4 3 2 26 1 0 25 24 Reserved The PSR bit assignments are: 31 30 29 28 27 N Z C V Q 23 22 21 20 ICI/IT 19 18 11 10 T 17 16 Reserved 15 14 13 12 ICI/IT 7 6 5 4 3 2 9 8 Reserved ISR_NUMBER 1 0 ISR_NUMBER Access these registers individually or as a combination of any two or all three registers, using the register
10.4.3.6 Application Program Status Register The APSR contains the current state of the condition flags from previous instruction executions. See the register summary in Table 10-2 on page 51 for its attributes. The bit assignments are: • N Negative or less than flag: 0 = operation result was positive, zero, greater than, or equal 1 = operation result was negative or less than. • Z Zero flag: 0 = operation result was not zero 1 = operation result was zero.
7-10 = Reserved 11 = SVCall 12 = Reserved for Debug 13 = Reserved 14 = PendSV 15 = SysTick 16 = IRQ0 45 = IRQ29 see “Exception types” on page 71 for more information. 10.4.3.8 Execution Program Status Register The EPSR contains the Thumb state bit, and the execution state bits for either the: If-Then (IT) instruction Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store multiple instruction.
10.4.3.11 Exception mask registers The exception mask registers disable the handling of exceptions by the processor. Disable exceptions where they might impact on timing critical tasks. To access the exception mask registers use the MSR and MRS instructions, or the CPS instruction to change the value of PRIMASK or FAULTMASK. See “MRS” on page 146, “MSR” on page 147, and “CPS” on page 143 for more information.
10.4.3.12 Priority Mask Register The PRIMASK register prevents activation of all exceptions with configurable priority. See the register summary in Table 10-2 on page 51 for its attributes. The bit assignments are: 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 4 Reserved 0 PRIMASK • PRIMASK 0: no effect 1: prevents the activation of all exceptions with configurable priority.
10.4.3.13 Fault Mask Register The FAULTMASK register prevents activation of all exceptions. See the register summary in Table 10-2 on page 51 for its attributes. The bit assignments are: 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 4 Reserved • FAULTMASK 0: no effect 1: prevents the activation of all exceptions.
10.4.3.14 Base Priority Mask Register The BASEPRI register defines the minimum priority for exception processing. When BASEPRI is set to a nonzero value, it prevents the activation of all exceptions with same or lower priority level as the BASEPRI value. See the register summary in Table 10-2 on page 51 for its attributes.
10.4.3.15 CONTROL register The CONTROL register controls the stack used and the privilege level for software execution when the processor is in Thread mode. See the register summary in Table 10-2 on page 51 for its attributes.
10.4.4 Exceptions and interrupts The Cortex-M3 processor supports interrupts and system exceptions. The processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. An exception changes the normal flow of software control. The processor uses handler mode to handle all exceptions except for reset. See “Exception entry” on page 76 and “Exception return” on page 76 for more information. The NVIC registers control interrupt handling.
10.5 Memory model This section describes the processor memory map, the behavior of memory accesses, and the bit-banding features. The processor has a fixed memory map that provides up to 4GB of addressable memory. The memory map is: [)))))))) 9HQGRU VSHFLILF PHPRU\ 0% [( [( ))))) 3ULYDWH SHULSKHUDO 0% EXV [( ['))))))) ([WHUQDO GHYLFH *% [$ [ ))))))) ([WHUQDO 5$0 [ )))))) *% 0% %LW EDQG DOLDV [ [ ))))))) [ [ ))))) 0% %LW EDQG UHJL
10.5.1.1 Normal The processor can re-order transactions for efficiency, or perform speculative reads. 10.5.1.2 Device The processor preserves transaction order relative to other transactions to Device or Strongly-ordered memory. 10.5.1.3 Strongly-ordered The processor preserves transaction order relative to all other transactions.
10.5.3 Behavior of memory accesses The behavior of accesses to each region in the memory map is: Table 10-4. Memory access behavior Address range Memory region Memory type XN Description 0x000000000x1FFFFFFF Code Normal (1) - Executable region for program code. You can also put data here. Executable region for data. You can also put code here.
10.5.3.1 Additional memory access constraints for shared memory When a system includes shared memory, some memory regions have additional access constraints, and some regions are subdivided, as Table 10-5 shows: Table 10-5.
10.5.4.2 DSB The Data Synchronization Barrier (DSB) instruction ensures that outstanding memory transactions complete before subsequent instructions execute. See “DSB” on page 144. 10.5.4.3 ISB The Instruction Synchronization Barrier (ISB) ensures that the effect of all completed memory transactions is recognizable by subsequent instructions. See “ISB” on page 145.
Table 10-6. SRAM memory bit-banding regions Address range Memory region 0x20000000- SRAM bit-band region Direct accesses to this memory range behave as SRAM memory accesses, but this region is also bit addressable through bit-band alias. SRAM bit-band alias Data accesses to this region are remapped to bit band region. A write operation is performed as read-modify-write. Instruction accesses are not remapped. 0x200FFFFF 0x220000000x23FFFFFF Table 10-7.
Figure 10-2.
10.5.6.1 Little-endian format In little-endian format, the processor stores the least significant byte of a word at the lowest-numbered byte, and the most significant byte at the highest-numbered byte. For example: 0HPRU\ 5HJLVWHU 10.5.7 $GGUHVV $ % $ % $ % $ % OVE\WH % % % % PVE\WH Synchronization primitives The Cortex-M3 instruction set includes pairs of synchronization primitives.
If the returned status bit from the second step indicates that the Store-Exclusive succeeded then the software has claimed the semaphore. However, if the Store-Exclusive failed, another process might have claimed the semaphore after the software performed the first step. The Cortex-M3 includes an exclusive access monitor, that tags the fact that the processor has executed a LoadExclusive instruction.
10.6.1.3 Active An exception that is being serviced by the processor but has not completed. An exception handler can interrupt the execution of another exception handler. In this case both exceptions are in the active state. 10.6.1.4 Active and pending The exception is being serviced by the processor and there is a pending exception from the same source. 10.6.2 Exception types The exception types are: 10.6.2.1 Reset Reset is invoked on power up or a warm reset.
10.6.2.7 SVCall A supervisor call (SVC) is an exception that is triggered by the SVC instruction. In an OS environment, applications can use SVC instructions to access OS kernel functions and device drivers. 10.6.2.8 PendSV PendSV is an interrupt-driven request for system-level service. In an OS environment, use PendSV for context switching when no other exception is active. 10.6.2.9 SysTick A SysTick exception is an exception the system timer generates when it reaches zero.
Privileged software can disable the exceptions that Table 10-9 on page 72 shows as having configurable priority, see: “System Handler Control and State Register” on page 180 “Interrupt Clear-enable Registers” on page 156. For more information about hard faults, memory management faults, bus faults, and usage faults, see “Fault handling” on page 78. 10.6.3 Exception handlers The processor handles exceptions using: 10.6.3.
Figure 10-3. Vector table Exception number IRQ number 45 29 . . . 18 2 17 1 16 0 15 -1 14 -2 13 Vector Offset IRQ29 0x00B4 . . . 0x004C . . .
For example, assigning a higher priority value to IRQ[0] and a lower priority value to IRQ[1] means that IRQ[1] has higher priority than IRQ[0]. If both IRQ[1] and IRQ[0] are asserted, IRQ[1] is processed before IRQ[0]. If multiple pending exceptions have the same priority, the pending exception with the lowest exception number takes precedence. For example, if both IRQ[0] and IRQ[1] are pending and have the same priority, then IRQ[0] is processed before IRQ[1].
exception. State saving is not affected by late arrival because the state saved is the same for both exceptions. Therefore the state saving continues uninterrupted. The processor can accept a late arriving exception until the first instruction of the exception handler of the original exception enters the execute stage of the processor. On return from the exception handler of the late-arriving exception, the normal tail-chaining rules apply. 10.6.7.
The processor sets EXC_RETURN bits[31:4] to 0xFFFFFFF. When this value is loaded into the PC it indicates to the processor that the exception is complete, and the processor initiates the exception return sequence. Table 10-10. Exception return behavior EXC_RETURN[3:0] Description bXXX0 Reserved. Return to Handler mode. b0001 Exception return gets state from MSP. Execution uses MSP after return. b0011 Reserved. b01X1 Reserved. Return to Thread mode. b1001 Exception return gets state from MSP.
10.7 Fault handling Faults are a subset of the exceptions, see “Exception model” on page 70. The following generate a fault: ̶ 10.7.1 a bus error on: ̶ an instruction fetch or vector table load ̶ a data access an internally-detected error such as an undefined instruction or an attempt to change state with a BX instruction attempting to execute an instruction from a memory region marked as Non-Executable (XN).
10.7.2 Fault escalation and hard faults All faults exceptions except for hard fault have configurable exception priority, see “System Handler Priority Registers” on page 177. Software can disable execution of the handlers for these faults, see “System Handler Control and State Register” on page 180.
10.8 Power management The Cortex-M3 processor sleep modes reduce power consumption: Backup Mode Wait Mode Sleep Mode The SLEEPDEEP bit of the SCR selects which sleep mode is used, see “System Control Register” on page 174. For more information about the behavior of the sleep modes see “Low Power Modes” in the PMC section of the datasheet. This section describes the mechanisms for entering sleep mode, and the conditions for waking up from sleep mode. 10.8.
10.8.2.2 Wakeup from WFE The processor wakes up if: it detects an exception with sufficient priority to cause exception entry In addition, if the SEVONPEND bit in the SCR is set to 1, any new pending interrupt triggers an event and wakes up the processor, even if the interrupt is disabled or has insufficient priority to cause exception entry. For more information about the SCR see “System Control Register” on page 174. 10.8.
Table 10-13.
Table 10-13.
Table 10-13.
10.10 Intrinsic functions ANSI cannot directly access some Cortex-M3 instructions. This section describes intrinsic functions that can generate these instructions, provided by the CMIS and that might be provided by a C compiler. If a C compiler does not support an appropriate intrinsic function, you might have to use inline assembler to access some instructions. The CMSIS provides the following intrinsic functions to generate instructions that ANSI cannot directly access: Table 10-14.
10.11 About the instruction descriptions The following sections give more information about using the instructions: “Operands” on page 86 “Restrictions when using PC or SP” on page 86 “Flexible second operand” on page 86 “Shift Operations” on page 87 “Address alignment” on page 90 “PC-relative expressions” on page 90 “Conditional execution” on page 91 “Instruction width selection” on page 92. 10.11.
produced by shifting an 8-bit value. These instructions do not affect the carry flag if Operand2 is any other constant. 10.11.3.2 Instruction substitution Your assembler might be able to produce an equivalent instruction in cases where you specify a constant that is not permitted. For example, an assembler might assemble the instruction CMP Rd, #0xFFFFFFFE as the equivalent instruction CMN Rd, #0x2. 10.11.3.
10.11.4.1 ASR Arithmetic shift right by n bits moves the left-hand 32-n bits of the register Rm, to the right by n places, into the right-hand 32-n bits of the result. And it copies the original bit[31] of the register into the left-hand n bits of the result. See Figure 10-4 on page 88. You can use the ASR #n operation to divide the value in the register Rm by 2n, with the result being rounded towards negative-infinity.
10.11.4.3 LSL Logical shift left by n bits moves the right-hand 32-n bits of the register Rm, to the left by n places, into the left-hand 32-n bits of the result. And it sets the right-hand n bits of the result to 0. See Figure 10-6 on page 89. You can use he LSL #n operation to multiply the value in the register Rm by 2n, if the value is regarded as an unsigned integer or a two’s complement signed integer. Overflow can occur without warning.
10.11.4.5 RRX Rotate right with extend moves the bits of the register Rm to the right by one bit. And it copies the carry flag into bit[31] of the result. See Figure 10-8 on page 90. When the instruction is RRXS or when RRX is used in Operand2 with the instructions MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to bit[0] of the register Rm. Figure 10-8. RRX &DUU\ )ODJ 10.11.
10.11.7 Conditional execution Most data processing instructions can optionally update the condition flags in the Application Program Status Register (APSR) according to the result of the operation, see “Application Program Status Register” on page 54. Some instructions update all flags, and some only update a subset. If a flag is not updated, the original value is preserved. See the instruction descriptions for the flags they affect.
10.11.7.2 Condition code suffixes The instructions that can be conditional have an optional condition code, shown in syntax descriptions as {cond}. Conditional execution requires a preceding IT instruction. An instruction with a condition code is only executed if the condition code flags in the APSR meet the specified condition. Table 10-16 shows the condition codes to use. You can use conditional execution with the IT instruction to reduce the number of branch instructions in code.
If you specify an instruction width suffix and the assembler cannot generate an instruction encoding of the requested width, it generates an error. In some cases it might be necessary to specify the .W suffix, for example if the operand is the label of an instruction or literal data, as in the case of branch instructions. This is because the assembler might not automatically generate the right size encoding. 10.11.8.
10.12 Memory access instructions Table 10-17 shows the memory access instructions: Table 10-17.
10.12.1 ADR Load PC-relative address. 10.12.1.1 Syntax ADR{cond} Rd, label where: cond is an optional condition code, see “Conditional execution” on page 91. Rd is the destination register. label is a PC-relative expression. See “PC-relative expressions” on page 90. 10.12.1.2 Operation ADR determines the address by adding an immediate value to the PC, and writes the result to the destination register. ADR produces position-independent code, because the address is PC-relative.
10.12.2 LDR and STR, immediate offset Load and Store with immediate offset, pre-indexed immediate offset, or post-indexed immediate offset. 10.12.2.
The value to load or store can be a byte, halfword, word, or two words. Bytes and halfwords can either be signed or unsigned. See “Address alignment” on page 90. Table 10-18 shows the ranges of offset for immediate, pre-indexed and post-indexed forms. Table 10-18.
10.12.3 LDR and STR, register offset Load and Store with register offset. 10.12.3.1 Syntax op{type}{cond} Rt, [Rn, Rm {, LSL #n}] where: op is one of: LDR Load Register. STR Store Register. type is one of: B unsigned byte, zero extend to 32 bits on loads. SB signed byte, sign extend to 32 bits (LDR only). H unsigned halfword, zero extend to 32 bits on loads. SH signed halfword, sign extend to 32 bits (LDR only). - omit, for word.
10.12.3.
10.12.4 LDR and STR, unprivileged Load and Store with unprivileged access. 10.12.4.1 Syntax op{type}T{cond} Rt, [Rn {, #offset}] ; immediate offset where: op is one of: LDR Load Register. STR Store Register. type is one of: B unsigned byte, zero extend to 32 bits on loads. SB signed byte, sign extend to 32 bits (LDR only). H unsigned halfword, zero extend to 32 bits on loads. SH signed halfword, sign extend to 32 bits (LDR only). - omit, for word.
10.12.5 LDR, PC-relative Load register from memory. 10.12.5.1 Syntax LDR{type}{cond} Rt, label LDRD{cond} Rt, Rt2, label ; Load two words where: type is one of: B unsigned byte, zero extend to 32 bits. SB signed byte, sign extend to 32 bits. H unsigned halfword, zero extend to 32 bits. SH signed halfword, sign extend to 32 bits. - omit, for word. cond is an optional condition code, see “Conditional execution” on page 91. Rt is the register to load or store.
10.12.5.
10.12.6 LDM and STM Load and Store Multiple registers. 10.12.6.1 Syntax op{addr_mode}{cond} Rn{!}, reglist where: op is one of: LDM Load Multiple registers. STM Store Multiple registers. addr_mode is any one of the following: IA Increment address After each access. This is the default. DB Decrement address Before each access. cond is an optional condition code, see “Conditional execution” on page 91. Rn is the register on which the memory addresses are based.
10.12.6.3 Restrictions In these instructions: Rn must not be PC reglist must not contain SP in any STM instruction, reglist must not contain PC in any LDM instruction, reglist must not contain PC if it contains LR reglist must not contain Rn if you specify the writeback suffix.
10.12.7 PUSH and POP Push registers onto, and pop registers off a full-descending stack. 10.12.7.1 Syntax PUSH{cond} reglist POP{cond} reglist where: cond is an optional condition code, see “Conditional execution” on page 91. reglist is a non-empty list of registers, enclosed in braces. It can contain register ranges. It must be comma separated if it contains more than one register or register range.
10.12.8 LDREX and STREX Load and Store Register Exclusive. 10.12.8.1 Syntax LDREX{cond} Rt, [Rn {, #offset}] STREX{cond} Rd, Rt, [Rn {, #offset}] LDREXB{cond} Rt, [Rn] STREXB{cond} Rd, Rt, [Rn] LDREXH{cond} Rt, [Rn] STREXH{cond} Rd, Rt, [Rn] where: cond is an optional condition code, see “Conditional execution” on page 91. Rd is the destination register for the returned status. Rt is the register to load or store. Rn is the register on which the memory address is based.
10.12.8.5 Examples MOV R1, #0x1 ; Initialize the ‘lock taken’ value LDREX CMP ITT STREXEQ CMPEQ BNE ....
10.12.9 CLREX Clear Exclusive. 10.12.9.1 Syntax CLREX{cond} where: cond is an optional condition code, see “Conditional execution” on page 91. 10.12.9.2 Operation Use CLREX to make the next STREX, STREXB, or STREXH instruction write 1 to its destination register and fail to perform the store.
10.13 General data processing instructions Table 10-20 shows the data processing instructions: Table 10-20.
10.13.1 ADD, ADC, SUB, SBC, and RSB Add, Add with carry, Subtract, Subtract with carry, and Reverse Subtract. 10.13.1.1 Syntax op{S}{cond} {Rd,} Rn, Operand2 op{cond} {Rd,} Rn, #imm12 ; ADD and SUB only where: op is one of: ADD Add. ADC Add with Carry. SUB Subtract. SBC Subtract with Carry. RSB Reverse Subtract. S is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation, see “Conditional execution” on page 91.
̶ you must not specify the S suffix ̶ Rm must not be PC and must not be SP ̶ if the instruction is conditional, it must be the last instruction in the IT block with the exception of the ADD{cond} PC, PC, Rm instruction, Rn can be PC only in ADD and SUB, and only with the additional restrictions: ̶ you must not specify the S suffix ̶ the second operand must be a constant in the range 0 to 4095.
10.13.1.6 Multiword arithmetic examples 10.13.1.7 64-bit addition The example below shows two instructions that add a 64-bit integer contained in R2 and R3 to another 64-bit integer contained in R0 and R1, and place the result in R4 and R5. ADDS ADC R4, R0, R2 R5, R1, R3 ; add the least significant words ; add the most significant words with carry 10.13.1.8 96-bit subtraction Multiword values do not have to use consecutive registers.
10.13.2 AND, ORR, EOR, BIC, and ORN Logical AND, OR, Exclusive OR, Bit Clear, and OR NOT. 10.13.2.1 Syntax op{S}{cond} {Rd,} Rn, Operand2 where: op is one of: AND logical AND. ORR logical OR, or bit set. EOR logical Exclusive OR. BIC logical AND NOT, or bit clear. ORN logical OR NOT. S is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation, see “Conditional execution” on page 91.
10.13.3 ASR, LSL, LSR, ROR, and RRX Arithmetic Shift Right, Logical Shift Left, Logical Shift Right, Rotate Right, and Rotate Right with Extend. 10.13.3.1 Syntax op{S}{cond} Rd, Rm, Rs op{S}{cond} Rd, Rm, #n RRX{S}{cond} Rd, Rm where: op is one of: ASR Arithmetic Shift Right. LSL Logical Shift Left. LSR Logical Shift Right. ROR Rotate Right. S is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation, see “Conditional execution” on page 91.
10.13.3.
10.13.4 CLZ Count Leading Zeros. 10.13.4.1 Syntax CLZ{cond} Rd, Rm where: cond is an optional condition code, see “Conditional execution” on page 91. Rd is the destination register. Rm is the operand register. 10.13.4.2 Operation The CLZ instruction counts the number of leading zeros in the value in Rm and returns the result in Rd. The result value is 32 if no bits are set in the source register, and zero if bit[31] is set. 10.13.4.3 Restrictions Do not use SP and do not use PC. 10.13.4.
10.13.5 CMP and CMN Compare and Compare Negative. 10.13.5.1 Syntax CMP{cond} Rn, Operand2 CMN{cond} Rn, Operand2 where: cond is an optional condition code, see “Conditional execution” on page 91. Rn is the register holding the first operand. Operand2 is a flexible second operand. See “Flexible second operand” on page 86 for details of the options. 10.13.5.2 Operation These instructions compare the value in a register with Operand2.
10.13.6 MOV and MVN Move and Move NOT. 10.13.6.1 Syntax MOV{S}{cond} Rd, Operand2 MOV{cond} Rd, #imm16 MVN{S}{cond} Rd, Operand2 where: S is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation, see “Conditional execution” on page 91. cond is an optional condition code, see “Conditional execution” on page 91. Rd is the destination register. Operand2 is a flexible second operand. See “Flexible second operand” on page 86 for details of the options.
10.13.6.4 Condition flags If S is specified, these instructions: update the N and Z flags according to the result can update the C flag during the calculation of Operand2, see “Flexible second operand” on page 86 do not affect the V flag. 10.13.6.
10.13.7 MOVT Move Top. 10.13.7.1 Syntax MOVT{cond} Rd, #imm16 where: cond is an optional condition code, see “Conditional execution” on page 91. Rd is the destination register. imm16 is a 16-bit immediate constant. 10.13.7.2 Operation MOVT writes a 16-bit immediate value, imm16, to the top halfword, Rd[31:16], of its destination register. The write does not affect Rd[15:0]. The MOV, MOVT instruction pair enables you to generate any 32-bit constant. 10.13.7.
10.13.8 REV, REV16, REVSH, and RBIT Reverse bytes and Reverse bits. 10.13.8.1 Syntax op{cond} Rd, Rn where: op is any of: REV Reverse byte order in a word. REV16 Reverse byte order in each halfword independently. REVSH Reverse byte order in the bottom halfword, and sign extend to 32 bits. RBIT Reverse the bit order in a 32-bit word. cond is an optional condition code, see “Conditional execution” on page 91. Rd is the destination register. Rn is the register holding the operand. 10.13.8.
10.13.9 TST and TEQ Test bits and Test Equivalence. 10.13.9.1 Syntax TST{cond} Rn, Operand2 TEQ{cond} Rn, Operand2 where: cond is an optional condition code, see “Conditional execution” on page 91. Rn is the register holding the first operand. Operand2 is a flexible second operand. See “Flexible second operand” on page 86 for details of the options. 10.13.9.2 Operation These instructions test the value in a register against Operand2.
10.14 Multiply and divide instructions Table 10-21 shows the multiply and divide instructions: Table 10-21.
10.14.1 MUL, MLA, and MLS Multiply, Multiply with Accumulate, and Multiply with Subtract, using 32-bit operands, and producing a 32-bit result. 10.14.1.1 Syntax MUL{S}{cond} {Rd,} Rn, Rm ; Multiply MLA{cond} Rd, Rn, Rm, Ra ; Multiply with accumulate MLS{cond} Rd, Rn, Rm, Ra ; Multiply with subtract where: cond is an optional condition code, see “Conditional execution” on page 91. S is an optional suffix.
10.14.2 UMULL, UMLAL, SMULL, and SMLAL Signed and Unsigned Long Multiply, with optional Accumulate, using 32-bit operands and producing a 64-bit result. 10.14.2.1 Syntax op{cond} RdLo, RdHi, Rn, Rm where: op is one of: UMULL Unsigned Long Multiply. UMLAL Unsigned Long Multiply, with Accumulate. SMULL Signed Long Multiply. SMLAL Signed Long Multiply, with Accumulate. cond is an optional condition code, see “Conditional execution” on page 91. RdHi, RdLo are the destination registers.
10.14.3 SDIV and UDIV Signed Divide and Unsigned Divide. 10.14.3.1 Syntax SDIV{cond} {Rd,} Rn, Rm UDIV{cond} {Rd,} Rn, Rm where: cond is an optional condition code, see “Conditional execution” on page 91. Rd is the destination register. If Rd is omitted, the destination register is Rn. Rn is the register holding the value to be divided. Rm is a register holding the divisor. 10.14.3.2 Operation SDIV performs a signed integer division of the value in Rn by the value in Rm.
10.15 Saturating instructions This section describes the saturating instructions, SSAT and USAT. 10.15.1 SSAT and USAT Signed Saturate and Unsigned Saturate to any bit position, with optional shift before saturating. 10.15.1.1 Syntax op{cond} Rd, #n, Rm {, shift #s} where: op is one of: SSAT Saturates a signed value to a signed range. USAT Saturates a signed value to an unsigned range. cond is an optional condition code, see “Conditional execution” on page 91. Rd is the destination register.
10.15.1.4 Condition flags These instructions do not affect the condition code flags. If saturation occurs, these instructions set the Q flag to 1. 10.15.1.
10.16 Bitfield instructions Table 10-22 shows the instructions that operate on adjacent sets of bits in registers or bitfields: Table 10-22.
10.16.1 BFC and BFI Bit Field Clear and Bit Field Insert. 10.16.1.1 Syntax BFC{cond} Rd, #lsb, #width BFI{cond} Rd, Rn, #lsb, #width where: cond is an optional condition code, see “Conditional execution” on page 91. Rd is the destination register. Rn is the source register. lsb is the position of the least significant bit of the bitfield. lsb must be in the range 0 to 31. width is the width of the bitfield and must be in the range 1 to 32−lsb. 10.16.1.
10.16.2 SBFX and UBFX Signed Bit Field Extract and Unsigned Bit Field Extract. 10.16.2.1 Syntax SBFX{cond} Rd, Rn, #lsb, #width UBFX{cond} Rd, Rn, #lsb, #width where: cond is an optional condition code, see “Conditional execution” on page 91. Rd is the destination register. Rn is the source register. lsb is the position of the least significant bit of the bitfield. lsb must be in the range 0 to 31. width is the width of the bitfield and must be in the range 1 to 32−lsb. 10.16.2.
10.16.3 SXT and UXT Sign extend and Zero extend. 10.16.3.1 Syntax SXTextend{cond} {Rd,} Rm {, ROR #n} UXTextend{cond} {Rd}, Rm {, ROR #n} where: extend is one of: B Extends an 8-bit value to a 32-bit value. H Extends a 16-bit value to a 32-bit value. cond is an optional condition code, see “Conditional execution” on page 91. Rd is the destination register. Rm is the register holding the value to extend. ROR #n is one of: ROR #8 Value from Rm is rotated right 8 bits.
10.17 Branch and control instructions Table 10-23 shows the branch and control instructions: Table 10-23.
10.17.1 B, BL, BX, and BLX Branch instructions. 10.17.1.1 Syntax B{cond} label BL{cond} label BX{cond} Rm BLX{cond} Rm where: B is branch (immediate). BL is branch with link (immediate). BX is branch indirect (register). BLX is branch indirect with link (register). cond is an optional condition code, see “Conditional execution” on page 91. label is a PC-relative expression. See “PC-relative expressions” on page 90. Rm is a register that indicates an address to branch to.
Bcond is the only conditional instruction that is not required to be inside an IT block. However, it has a longer branch range when it is inside an IT block. 10.17.1.4 Condition flags These instructions do not change the flags. 10.17.1.5 Examples B BLE B.W BEQ BEQ.
10.17.2 CBZ and CBNZ Compare and Branch on Zero, Compare and Branch on Non-Zero. 10.17.2.1 Syntax CBZ Rn, label CBNZ Rn, label where: Rn is the register holding the operand. label is the branch destination. 10.17.2.2 Operation Use the CBZ or CBNZ instructions to avoid changing the condition code flags and to reduce the number of instructions.
10.17.3 IT If-Then condition instruction. 10.17.3.1 Syntax IT{x{y{z}}} cond where: x specifies the condition switch for the second instruction in the IT block. y specifies the condition switch for the third instruction in the IT block. z specifies the condition switch for the fourth instruction in the IT block. cond specifies the condition for the first instruction in the IT block. The condition switch for the second, third and fourth instruction in the IT block can be either: T Then.
do not branch to any instruction inside an IT block, except when returning from an exception handler all conditional instructions except Bcond must be inside an IT block. Bcond can be either outside or inside an IT block but has a larger branch range if it is inside one each instruction inside the IT block must specify a condition code suffix that is either the same or logical inverse as for the other instructions in the block.
10.17.4 TBB and TBH Table Branch Byte and Table Branch Halfword. 10.17.4.1 Syntax TBB [Rn, Rm] TBH [Rn, Rm, LSL #1] where: Rn is the register containing the address of the table of branch lengths. If Rn is PC, then the address of the table is the address of the byte immediately following the TBB or TBH instruction. Rm is the index register. This contains an index into the table. For halfword tables, LSL #1 doubles the value in Rm to form the right offset into the table. 10.17.4.
10.17.4.5 Examples ADR.
10.18 Miscellaneous instructions Table 10-25 shows the remaining Cortex-M3 instructions: Table 10-25.
10.18.1 BKPT Breakpoint. 10.18.1.1 Syntax BKPT #imm where: imm is an expression evaluating to an integer in the range 0-255 (8-bit value). 10.18.1.2 Operation The BKPT instruction causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached. imm is ignored by the processor. If required, a debugger can use it to store additional information about the breakpoint.
10.18.2 CPS Change Processor State. 10.18.2.1 Syntax CPSeffect iflags where: effect is one of: IE Clears the special purpose register. ID Sets the special purpose register. iflags is a sequence of one or more flags: i Set or clear PRIMASK. f Set or clear FAULTMASK. 10.18.2.2 Operation CPS changes the PRIMASK and FAULTMASK special register values. See “Exception mask registers” on page 56 for more information about these registers. 10.18.2.
10.18.3 DMB Data Memory Barrier. 10.18.3.1 Syntax DMB{cond} where: cond is an optional condition code, see “Conditional execution” on page 91. 10.18.3.2 Operation DMB acts as a data memory barrier. It ensures that all explicit memory accesses that appear, in program order, before the DMB instruction are completed before any explicit memory accesses that appear, in program order, after the DMB instruction. DMB does not affect the ordering or execution of instructions that do not access memory. 10.18.3.
10.18.5 ISB Instruction Synchronization Barrier. 10.18.5.1 Syntax ISB{cond} where: cond is an optional condition code, see “Conditional execution” on page 91. 10.18.5.2 Operation ISB acts as an instruction synchronization barrier. It flushes the pipeline of the processor, so that all instructions following the ISB are fetched from memory again, after the ISB instruction has been completed. 10.18.5.3 Condition flags This instruction does not change the flags. 10.18.5.
10.18.6 MRS Move the contents of a special register to a general-purpose register. 10.18.6.1 Syntax MRS{cond} Rd, spec_reg where: cond is an optional condition code, see “Conditional execution” on page 91. Rd is the destination register. spec_reg can be any of: APSR, IPSR, EPSR, IEPSR, IAPSR, EAPSR, PSR, MSP, PSP, PRIMASK, BASEPRI, BASEPRI_MAX, FAULTMASK, or CONTROL. 10.18.6.
10.18.7 MSR Move the contents of a general-purpose register into the specified special register. 10.18.7.1 Syntax MSR{cond} spec_reg, Rn where: cond is an optional condition code, see “Conditional execution” on page 91. Rn is the source register. spec_reg can be any of: APSR, IPSR, EPSR, IEPSR, IAPSR, EAPSR, PSR, MSP, PSP, PRIMASK, BASEPRI, BASEPRI_MAX, FAULTMASK, or CONTROL. 10.18.7.2 Operation The register access operation in MSR depends on the privilege level.
10.18.8 NOP No Operation. 10.18.8.1 Syntax NOP{cond} where: cond is an optional condition code, see “Conditional execution” on page 91. 10.18.8.2 Operation NOP does nothing. NOP is not necessarily a time-consuming NOP. The processor might remove it from the pipeline before it reaches the execution stage. Use NOP for padding, for example to place the following instruction on a 64-bit boundary. 10.18.8.3 Condition flags This instruction does not change the flags. 10.18.8.
10.18.10 SVC Supervisor Call. 10.18.10.1 Syntax SVC{cond} #imm where: cond is an optional condition code, see “Conditional execution” on page 91. imm is an expression evaluating to an integer in the range 0-255 (8-bit value). 10.18.10.2 Operation The SVC instruction causes the SVC exception. imm is ignored by the processor. If required, it can be retrieved by the exception handler to determine what service is being requested. 10.18.10.3 Condition flags This instruction does not change the flags. 10.
10.18.11 WFE Wait For Event. 10.18.11.1 Syntax WFE{cond} where: cond is an optional condition code, see “Conditional execution” on page 91. 10.18.11.2 Operation WFE is a hint instruction.
10.18.12 WFI Wait for Interrupt. 10.18.12.1 Syntax WFI{cond} where: cond is an optional condition code, see “Conditional execution” on page 91. 10.18.12.2 Operation WFI is a hint instruction that suspends execution until one of the following events occurs: an exception a Debug Entry request, regardless of whether Debug is enabled. 10.18.12.3 Condition flags This instruction does not change the flags. 10.18.12.
10.19 About the Cortex-M3 peripherals The address map of the Private peripheral bus (PPB) is: Table 10-26.
The processor automatically stacks its state on exception entry and unstacks this state on exception exit, with no instruction overhead. This provides low latency exception handling. The hardware implementation of the NVIC registers is: Table 10-27.
Table 10-28. Mapping of interrupts to the interrupt variables CMSIS array elements (1) Interrupts Set-enable Clear-enable Set-pending Clear-pending Active Bit 0-29 ISER[0] ICER[0] ISPR[0] ICPR[0] IABR[0] 30-63 ISER[1] ICER[1] ISPR[1] ICPR[1] IABR[1] 1. 154 Each array element corresponds to a single NVIC register, for example the element ICER[0] corresponds to the ICER0 register.
10.20.2 Interrupt Set-enable Registers The ISER0-ISER1 register enables interrupts, and show which interrupts are enabled. See: the register summary in Table 10-27 on page 153 for the register attributes Table 10-28 on page 154 for which interrupts are controlled by each register.
10.20.3 Interrupt Clear-enable Registers The ICER0-ICER1 register disables interrupts, and shows which interrupts are enabled. See: the register summary in Table 10-27 on page 153 for the register attributes Table 10-28 on page 154 for which interrupts are controlled by each register The bit assignments are: 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CLRENA 23 22 21 20 CLRENA 15 14 13 12 CLRENA 7 6 5 4 CLRENA • CLRENA Interrupt clear-enable bits.
10.20.4 Interrupt Set-pending Registers The ISPR0-ISPR1 register forces interrupts into the pending state, and shows which interrupts are pending. See: the register summary in Table 10-27 on page 153 for the register attributes Table 10-28 on page 154 for which interrupts are controlled by each register.
10.20.5 Interrupt Clear-pending Registers The ICPR0-ICPR1 register removes the pending state from interrupts, and show which interrupts are pending. See: the register summary in Table 10-27 on page 153 for the register attributes Table 10-28 on page 154 for which interrupts are controlled by each register.
10.20.6 Interrupt Active Bit Registers The IABR0-IABR1 register indicates which interrupts are active. See: the register summary in Table 10-27 on page 153 for the register attributes Table 10-28 on page 154 for which interrupts are controlled by each register.
10.20.7 Interrupt Priority Registers The IPR0-IPR7 registers provide a 4-bit priority field for each interrupt (See the “Peripheral Identifiers” section of the datasheet for more details). These registers are byte-accessible. See the register summary in Table 10-27 on page 153 for their attributes. Each register holds four priority fields, that map up to four elements in the CMSIS interrupt priority array IP[0] to IP[29], as shown: 10.20.7.
10.20.7.5 IPR1 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 IP[7] 23 22 21 20 IP[6] 15 14 13 12 IP[5] 7 6 5 4 IP[4] 10.20.7.6 IPR0 31 30 29 28 IP[3] 23 22 21 20 IP[2] 15 14 13 12 IP[1] 7 6 5 4 IP[0] • Priority, byte offset 3 • Priority, byte offset 2 • Priority, byte offset 1 • Priority, byte offset 0 Each priority field holds a priority value, 0-15.
10.20.8 Software Trigger Interrupt Register Write to the STIR to generate a Software Generated Interrupt (SGI). See the register summary in Table 10-27 on page 153 for the STIR attributes. When the USERSETMPEND bit in the SCR is set to 1, unprivileged software can access the STIR, see “System Control Register” on page 174. Only privileged software can enable unprivileged access to the STIR.
10.20.9 Level-sensitive interrupts The processor supports level-sensitive interrupts. A level-sensitive interrupt is held asserted until the peripheral deasserts the interrupt signal. Typically this happens because the ISR accesses the peripheral, causing it to clear the interrupt request. When the processor enters the ISR, it automatically removes the pending state from the interrupt, see “Hardware and software control of interrupts” .
10.20.10 NVIC design hints and tips Ensure software uses correctly aligned register accesses. The processor does not support unaligned accesses to NVIC registers. See the individual register descriptions for the supported access sizes. A interrupt can enter pending state even it is disabled. Before programming VTOR to relocate the vector table, ensure the vector table entries of the new vector table are setup for fault handlers and all enabled exception like interrupts.
10.21 System control block The System control block (SCB) provides system implementation information, and system control. This includes configuration, control, and reporting of the system exceptions. The system control block registers are: Table 10-30.
10.21.2 Auxiliary Control Register The ACTLR provides disable bits for the following processor functions: IT folding write buffer use for accesses to the default memory map interruption of multi-cycle instructions. See the register summary in Table 10-30 on page 165 for the ACTLR attributes.
10.21.3 CPUID Base Register The CPUID register contains the processor part number, version, and implementation information. See the register summary in Table 10-30 on page 165 for its attributes.
10.21.4 Interrupt Control and State Register The ICSR: provides: ̶ set-pending and clear-pending bits for the PendSV and SysTick exceptions indicates: ̶ the exception number of the exception being processed ̶ whether there are preempted active exceptions ̶ the exception number of the highest priority pending exception ̶ whether any interrupts are pending. See the register summary in Table 10-30 on page 165, and the Type descriptions in Table 10-33 on page 192, for the ICSR attributes.
• PENDSTSET RW SysTick exception set-pending bit. Write: 0: no effect 1: changes SysTick exception state to pending. Read: 0: SysTick exception is not pending 1: SysTick exception is pending. • PENDSTCLR WO SysTick exception clear-pending bit. Write: 0: no effect 1: removes the pending state from the SysTick exception. This bit is WO. On a register read its value is Unknown. • Reserved for Debug use RO This bit is reserved for Debug use and reads-as-zero when the processor is not in Debug.
• VECTACTIVE RO Contains the active exception number: 0: Thread mode Nonzero = The exception number (1) of the currently active exception. Subtract 16 from this value to obtain the IRQ number required to index into the Interrupt Clear-Enable, Set-Enable, ClearPending, Set-Pending, or Priority Registers, see “Interrupt Program Status Register” on page 54.
10.21.5 Vector Table Offset Register The VTOR indicates the offset of the vector table base address from memory address 0x00000000. See the register summary in Table 10-30 on page 165 for its attributes. The bit assignments are: 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved 23 TBLOFF 22 21 20 TBLOFF 15 14 13 12 TBLOFF 7 6 5 TBLOFF 4 Reserved • TBLOFF Vector table base offset field.
10.21.6 Application Interrupt and Reset Control Register The AIRCR provides priority grouping control for the exception model, endian status for data accesses, and reset control of the system. See the register summary in Table 10-30 on page 165 and Table 10-33 on page 192 for its attributes. To write to this register, you must write 0x05FA to the VECTKEY field, otherwise the processor ignores the write.
• VECTCLRACTIVE WO Reserved for Debug use. This bit reads as 0. When writing to the register you must write 0 to this bit, otherwise behavior is Unpredictable. • VECTRESET WO Reserved for Debug use. This bit reads as 0. When writing to the register you must write 0 to this bit, otherwise behavior is Unpredictable. 10.21.6.
10.21.7 System Control Register The SCR controls features of entry to and exit from low power state. See the register summary in Table 10-30 on page 165 for its attributes.
10.21.8 Configuration and Control Register The CCR controls entry to Thread mode and enables: the handlers for hard fault and faults escalated by FAULTMASK to ignore bus faults trapping of divide by zero and unaligned accesses access to the STIR by unprivileged software, see “Software Trigger Interrupt Register” on page 162. See the register summary in Table 10-30 on page 165 for the CCR attributes.
• USERSETMPEND Enables unprivileged software access to the STIR, see “Software Trigger Interrupt Register” on page 162: 0: disable 1: enable. • NONEBASETHRDENA Indicates how the processor enters Thread mode: 0: processor can enter Thread mode only when no exception is active. 1: processor can enter Thread mode from any level under the control of an EXC_RETURN value, see “Exception return” on page 76.
10.21.9 System Handler Priority Registers The SHPR1-SHPR3 registers set the priority level, 0 to 15 of the exception handlers that have configurable priority. SHPR1-SHPR3 are byte accessible. See the register summary in Table 10-30 on page 165 for their attributes. The system fault handlers and the priority field and register for each handler are: Table 10-32.
10.21.9.
10.21.9.2 System Handler Priority Register 2 The bit assignments are: 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 PRI_11 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 4 Reserved • PRI_11 Priority of system handler 11, SVCall 10.21.9.
10.21.10 System Handler Control and State Register The SHCSR enables the system handlers, and indicates: the pending status of the bus fault, memory management fault, and SVC exceptions the active status of the system handlers. See the register summary in Table 10-30 on page 165 for the SHCSR attributes.
• MONITORACT Debug monitor active bit, reads as 1 if Debug monitor is active • SVCALLACT SVC call active bit, reads as 1 if SVC call is active • USGFAULTACT Usage fault exception active bit, reads as 1 if exception is active • BUSFAULTACT Bus fault exception active bit, reads as 1 if exception is active • MEMFAULTACT Memory management fault exception active bit, reads as 1 if exception is active If you disable a system handler and the corresponding fault occurs, the processor treats the fault as a hard faul
10.21.11 Configurable Fault Status Register The CFSR indicates the cause of a memory management fault, bus fault, or usage fault. See the register summary in Table 10-30 on page 165 for its attributes.
10.21.11.1 Memory Management Fault Status Register The flags in the MMFSR indicate the cause of memory access faults. The bit assignments are: 7 MMARVALID 6 5 Reserved 4 3 2 1 0 MSTKERR MUNSTKERR Reserved DACCVIOL IACCVIOL • MMARVALID Memory Management Fault Address Register (MMAR) valid flag: 0: value in MMAR is not a valid fault address 1: MMAR holds a valid fault address.
10.21.11.2 Bus Fault Status Register The flags in the BFSR indicate the cause of a bus access fault. The bit assignments are: 7 6 BFRVALID 5 Reserved 4 3 2 1 0 STKERR UNSTKERR IMPRECISERR PRECISERR IBUSERR • BFARVALID Bus Fault Address Register (BFAR) valid flag: 0: value in BFAR is not a valid fault address 1: BFAR holds a valid fault address. The processor sets this bit to 1 after a bus fault where the address is known.
• PRECISERR Precise data bus error: 0: no precise data bus error 1: a data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused the fault. When the processor sets this bit is 1, it writes the faulting address to the BFAR. • IBUSERR Instruction bus error: 0: no instruction bus error 1: instruction bus error.
10.21.11.3 Usage Fault Status Register The UFSR indicates the cause of a usage fault. The bit assignments are: 15 14 13 12 11 10 Reserved 7 6 5 4 Reserved 9 8 DIVBYZERO UNALIGNED 3 2 1 0 NOCP INVPC INVSTATE UNDEFINSTR • DIVBYZERO Divide by zero usage fault: 0: no divide by zero fault, or divide by zero trapping not enabled 1: the processor has executed an SDIV or UDIV instruction with a divisor of 0.
• UNDEFINSTR Undefined instruction usage fault: 0: no undefined instruction usage fault 1: the processor has attempted to execute an undefined instruction. When this bit is set to 1, the PC value stacked for the exception return points to the undefined instruction. An undefined instruction is an instruction that the processor cannot decode. The UFSR bits are sticky. This means as one or more fault occurs, the associated bits are set to 1.
10.21.12 Hard Fault Status Register The HFSR gives information about events that activate the hard fault handler. See the register summary in Table 10-30 on page 165 for its attributes. This register is read, write to clear. This means that bits in the register read normally, but writing 1 to any bit clears that bit to 0.
10.21.13 Memory Management Fault Address Register The MMFAR contains the address of the location that generated a memory management fault. See the register summary in Table 10-30 on page 165 for its attributes.
10.21.14 Bus Fault Address Register The BFAR contains the address of the location that generated a bus fault. See the register summary in Table 1030 on page 165 for its attributes.
10.21.15 System control block design hints and tips Ensure software uses aligned accesses of the correct size to access the system control block registers: except for the CFSR and SHPR1-SHPR3, it must use aligned word accesses for the CFSR and SHPR1-SHPR3 it can use byte or aligned halfword or word accesses. The processor does not support unaligned accesses to system control block registers. In a fault handler. to determine the true faulting address: Read and save the MMFAR or BFAR value.
10.22 System timer, SysTick The processor has a 24-bit system timer, SysTick, that counts down from the reload value to zero, reloads (wraps to) the value in the LOAD register on the next clock edge, then counts down on subsequent clocks. When the processor is halted for debugging the counter does not decrement. The system timer registers are: Table 10-33.
10.22.1 SysTick Control and Status Register The SysTick CTRL register enables the SysTick features. See the register summary in Table 10-33 on page 192 for its attributes. The bit assignments are: 31 30 29 28 27 26 25 19 18 17 24 Reserved 23 22 21 20 Reserved 15 14 13 12 16 COUNTFLAG 11 10 9 8 Reserved 7 6 5 4 3 Reserved 2 1 0 CLKSOURCE TICKINT ENABLE • COUNTFLAG Returns 1 if timer counted to 0 since last time this was read.
10.22.2 SysTick Reload Value Register The LOAD register specifies the start value to load into the VAL register. See the register summary in Table 10-33 on page 192 for its attributes. The bit assignments are: 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved 23 22 21 20 RELOAD 15 14 13 12 RELOAD 7 6 5 4 -RELOAD • RELOAD Value to load into the VAL register when the counter is enabled and when it reaches 0, see “Calculating the RELOAD value” . 10.22.2.
10.22.3 SysTick Current Value Register The VAL register contains the current value of the SysTick counter. See the register summary in Table 10-33 on page 192 for its attributes. The bit assignments are: 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved 23 22 21 20 CURRENT 15 14 13 12 CURRENT 7 6 5 4 CURRENT • CURRENT Reads return the current value of the SysTick counter. A write of any value clears the field to 0, and also clears the SysTick CTRL.
10.22.4 SysTick Calibration Value Register The CALIB register indicates the SysTick calibration properties. See the register summary in Table 10-33 on page 192 for its attributes. The bit assignments are: 31 30 NOREF SKEW 23 22 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved 21 20 TENMS 15 14 13 12 TENMS 7 6 5 4 TENMS • NOREF Reads as zero. • SKEW Reads as zero • TENMS Read as 0x0002904.
10.23 Memory protection unit This section describes the Memory protection unit (MPU). The MPU divides the memory map into a number of regions, and defines the location, size, access permissions, and memory attributes of each region. It supports: independent attribute settings for each region overlapping regions export of memory attributes to the system. The memory attributes affect the behavior of memory accesses to the region.
Use the MPU registers to define the MPU regions and their attributes. The MPU registers are: Table 10-35.
10.23.1 MPU Type Register The TYPE register indicates whether the MPU is present, and if so, how many regions it supports. See the register summary in Table 10-35 on page 198 for its attributes. The bit assignments are: 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 Reserved 23 22 21 20 IREGION 15 14 13 12 DREGION 7 6 5 4 Reserved 0 SEPARATE • IREGION Indicates the number of supported MPU instruction regions. Always contains 0x00.
10.23.2 MPU Control Register The MPU CTRL register: enables the MPU enables the default memory map background region enables use of the MPU when in the hard fault, Non-maskable Interrupt (NMI), and FAULTMASK escalated handlers. See the register summary in Table 10-35 on page 198 for the MPU CTRL attributes.
When the ENABLE bit is set to 1, at least one region of the memory map must be enabled for the system to function unless the PRIVDEFENA bit is set to 1. If the PRIVDEFENA bit is set to 1 and no regions are enabled, then only privileged software can operate. When the ENABLE bit is set to 0, the system uses the default memory map. This has the same memory attributes as if the MPU is not implemented, see Table 10-34 on page 197.
10.23.3 MPU Region Number Register The RNR selects which memory region is referenced by the RBAR and RASR registers. See the register summary in Table 10-35 on page 198 for its attributes. The bit assignments are: 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 4 REGION • REGION Indicates the MPU region referenced by the RBAR and RASR registers.
10.23.4 MPU Region Base Address Register The RBAR defines the base address of the MPU region selected by the RNR, and can update the value of the RNR. See the register summary in Table 10-35 on page 198 for its attributes. Write RBAR with the VALID bit set to 1 to change the current region number and update the RNR.
10.23.5 MPU Region Attribute and Size Register The RASR defines the region size and memory attributes of the MPU region specified by the RNR, and enables that region and any subregions. See the register summary in Table 10-35 on page 198 for its attributes. RASR is accessible using word or halfword accesses: the most significant halfword holds the region attributes the least significant halfword holds the region size and the region and subregion enable bits.
10.23.5.1 SIZE field values The SIZE field defines the size of the MPU memory region specified by the RNR. as follows: (Region size in bytes) = 2(SIZE+1) The smallest permitted region size is 32B, corresponding to a SIZE value of 4. Table 10-36 gives example SIZE values, with the corresponding region size and value of N in the RBAR. Table 10-36.
10.23.6 MPU access permission attributes This section describes the MPU access permission attributes. The access permission bits, TEX, C, B, S, AP, and XN, of the RASR, control access to the corresponding memory region. If an access is made to an area of memory without the required permissions, then the MPU generates a permission fault. Table 10-37 shows the encodings for the TEX, C, B, and S access permission bits. Table 10-37.
Table 10-39 shows the AP encodings that define the access permissions for privileged and unprivileged software. Table 10-39.
Software must use memory barrier instructions: before MPU setup if there might be outstanding memory transfers, such as buffered writes, that might be affected by the change in MPU settings after MPU setup if it includes memory transfers that must use the new MPU settings.
a subregion means another region overlapping the disabled range matches instead. If no other enabled region overlaps the disabled subregion the MPU issues a fault. Regions of 32, 64, and 128 bytes do not support subregions, With regions of these sizes, you must set the SRD field to 0x00, otherwise the MPU behavior is Unpredictable. 10.23.8.4 Example of SRD use Two regions with the same base address overlap. Region one is 128KB, and region two is 512KB.
10.24 Glossary This glossary describes some of the terms used in technical documents from ARM. Abort A mechanism that indicates to a processor that the value associated with a memory access is invalid. An abort can be caused by the external or internal memory system as a result of attempting to access invalid instruction or data memory. Aligned A data item stored at an address that is divisible by the number of bytes that defines the data size is said to be aligned.
Doubleword A 64-bit data item. The contents are taken as being an unsigned integer unless otherwise stated. Doubleword-aligned A data item having a memory address that is divisible by eight. Endianness Byte ordering. The scheme that determines the order that successive bytes of a data word are stored in memory. An aspect of the system’s memory mapping. See also “Little-endian (LE)” Exception An event that interrupts program execution.
Interrupt handler A program that control of the processor is passed to when an interrupt occurs. Interrupt vector One of a number of fixed addresses in low memory, or in high memory if high vectors are configured, that contains the first instruction of the corresponding interrupt handler. Little-endian (LE) Byte ordering scheme in which bytes of increasing significance in a data word are stored at increasing addresses in memory.
Thread-safe In a multi-tasking environment, thread-safe functions use safeguard mechanisms when accessing shared resources, to ensure correct operation without the risk of shared access conflicts. Thumb instruction One or two halfwords that specify an operation for a processor to perform. Thumb instructions must be halfwordaligned. Unaligned A data item stored at an address that is not divisible by the number of bytes that defines the data size is said to be unaligned.
11. Debug and Test Features 11.1 Description The SAM3 Series microcontrollers feature a number of complementary debug and test capabilities. The Serial Wire/JTAG Debug Port (SWJ-DP) combining a Serial Wire Debug Port (SW-DP) and JTAG Debug (JTAG-DP) port is used for standard debugging functions, such as downloading code and single-stepping through programs. It also embeds a serial wire trace. 11.
11.3 Application Examples 11.3.1 Debug Environment Figure 11-2 shows a complete debug environment example. The SWJ-DP interface is used for standard debugging functions, such as downloading code and single-stepping through the program and viewing core and peripheral registers. Figure 11-2. Application Debug Environment Example Host Debugger PC SWJ-DP Emulator/Probe SWJ-DP Connector SAM3 SAM3-based Application Board 11.3.
Figure 11-3. Application Test Environment Example Test Adaptor Tester JTAG Probe JTAG Connector Chip n SAM3 Chip 2 Chip 1 SAM3-based Application Board In Test 11.4 Debug and Test Pin Description Table 11-1.
11.5 Functional Description 11.5.1 Test Pin One dedicated pin, TST, is used to define the device operating mode. When this pin is at low level during powerup, the device is in normal operating mode. When at high level, the device is in test mode or FFPI mode. The TST pin integrates a permanent pull-down resistor of about 15 kΩ,so that it can be left unconnected for normal operation.
Table 11-2. SWJ-DP Pin List Pin Name JTAG Port Serial Wire Debug Port TMS/SWDIO TMS SWDIO TCK/SWCLK TCK SWCLK TDI TDI – TDO/TRACESWO TDO TRACESWO (optional: trace) SW-DP or JTAG-DP mode is selected when JTAGSEL is low. It is not possible to switch directly between SWJ-DP and JTAG boundary scan operations. A chip reset must be performed after JTAGSEL is changed. 11.5.3.1 SW-DP and JTAG-DP Selection Mechanism Debug port selection mechanism is done by sending specific SWDIOTMS sequence.
The DWT contains counters for the following items: Clock cycle (CYCCNT) Folded instructions Load Store Unit (LSU) operations Sleep Cycles CPI (all instruction cycles except for the first cycle) Interrupt overhead 11.5.6 ITM (Instrumentation Trace Macrocell) The ITM is an application driven trace source that supports printf style debugging to trace Operating System (OS) and application events, and emits diagnostic system information.
11.5.6.3 5.4.3. How to Configure the TPIU This example only concerns the asynchronous trace mode. Set the TRCENA bit to 1 into the Debug Exception and Monitor Register (0xE000EDFC) to enable the use of trace and debug blocks.
11.5.8 ID Code Register Access: Read-only 31 30 29 28 27 VERSION 23 22 26 25 24 PART NUMBER 21 20 19 18 17 16 10 9 8 PART NUMBER 15 14 13 12 11 PART NUMBER 7 6 MANUFACTURER IDENTITY 5 4 3 2 1 MANUFACTURER IDENTITY 0 1 • VERSION[31:28]: Product Version Number Set to 0x0. • PART NUMBER[27:12]: Product Part Number Chip Name Chip ID SAM3X 0x05B2B • MANUFACTURER IDENTITY[11:1] Set to 0x01F. • Bit[0] Required by IEEE Std. 1149.1. Set to 0x1.
12. Reset Controller (RSTC) 12.1 Description The Reset Controller (RSTC), based on power-on reset cells, handles all the resets of the system without any external components. It reports which reset occurred last. The Reset Controller also drives independently or simultaneously the external reset and the peripheral and processor resets. 12.
12.4 Functional Description 12.4.1 Reset Controller Overview The Reset Controller is made up of an NRST Manager and a Reset State Manager. It runs at Slow Clock and generates the following reset signals: proc_nreset: Processor reset line. It also resets the Watchdog Timer. periph_nreset: Affects the whole set of embedded peripherals. nrst_out: Drives the NRST pin. These reset signals are asserted by the Reset Controller, either on external events or on software action.
12.4.2.2 NRST External Reset Control The Reset State Manager asserts the signal ext_nreset to assert the NRST pin. When this occurs, the “nrst_out” signal is driven low by the NRST Manager for a time programmed by the field ERSTL in RSTC_MR. This assertion duration, named EXTERNAL_RESET_LENGTH, lasts 2(ERSTL+1) Slow Clock cycles. This gives the approximate duration of an assertion between 60 µs and 2 seconds. Note that ERSTL at 0 defines a two-cycle duration for the NRST pulse.
12.4.4.2 Backup Reset A Backup reset occurs when the chip returns from Backup mode. The core_backup_reset signal is asserted by the Supply Controller when a Backup reset occurs. The field RSTTYP in RSTC_SR is updated to report a Backup Reset. 12.4.4.3 User Reset The User Reset is entered when a low level is detected on the NRST pin and the bit URSTEN in RSTC_MR is at 1. The NRST input signal is resynchronized with SLCK to insure proper behavior of the system.
12.4.4.4 Software Reset The Reset Controller offers several commands used to assert the different reset signals. These commands are performed by writing the Control Register (RSTC_CR) with the following bits at 1: PROCRST: Writing PROCRST at 1 resets the processor and the watchdog timer. PERRST: Writing PERRST at 1 resets all the embedded peripherals, including the memory system, and, in particular, the Remap Command. The Peripheral Reset is generally used for debug purposes.
12.4.4.5 Watchdog Reset The Watchdog Reset is entered when a watchdog fault occurs. This state lasts 3 Slow Clock cycles. When in Watchdog Reset, assertion of the reset signals depends on the WDRPROC bit in WDT_MR: If WDRPROC is 0, the Processor Reset and the Peripheral Reset are asserted. The NRST line is also asserted, depending on the programming of the field ERSTL. However, the resulting low level on NRST does not result in a User Reset state.
12.4.5 Reset State Priorities The Reset State Manager manages the following priorities between the different reset sources, given in descending order: General Reset Backup Reset Watchdog Reset Software Reset User Reset Particular cases are listed below: When in User Reset: ̶ ̶ A watchdog event is impossible because the Watchdog Timer is being reset by the proc_nreset signal. A software reset is impossible, since the processor reset is being activated.
Figure 12-7.
12.5 Reset Controller (RSTC) User Interface Table 12-1.
12.5.1 Reset Controller Control Register Name: RSTC_CR Address: 0x400E1A00 Access: Write-only 31 30 29 28 27 26 25 24 KEY 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 – 7 – 6 – 5 – 4 – 3 EXTRST 2 PERRST 1 – 0 PROCRST • PROCRST: Processor Reset 0: No effect. 1: If KEY is correct, resets the processor. • PERRST: Peripheral Reset 0: No effect. 1: If KEY is correct, resets the peripherals. • EXTRST: External Reset 0: No effect.
12.5.2 Reset Controller Status Register Name: RSTC_SR Address: 0x400E1A04 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 SRCMP 16 NRSTL 15 – 14 – 13 – 12 – 11 – 10 9 RSTTYP 8 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 URSTS • URSTS: User Reset Status 0: No high-to-low edge on NRST happened since the last read of RSTC_SR. 1: At least one high-to-low transition of NRST has been detected since the last read of RSTC_SR.
12.5.3 Reset Controller Mode Register Name: RSTC_MR Address: 0x400E1A08 Access: Read-write 31 30 29 28 27 26 25 24 17 – 16 – 9 8 1 – 0 URSTEN KEY 23 – 22 – 21 – 20 – 19 – 18 – 15 – 14 – 13 – 12 – 11 10 7 – 6 – 5 4 URSTIEN 3 – ERSTL 2 – • URSTEN: User Reset Enable 0: The detection of a low level on the pin NRST does not generate a User Reset. 1: The detection of a low level on the pin NRST triggers a User Reset.
13. Real-time Timer (RTT) 13.1 Description The Real-time Timer is built around a 32-bit counter used to count roll-over events of the programmable 16-bit prescaler which enables counting elapsed seconds from a 32 kHz slow clock source. It generates a periodic interrupt and/or triggers an alarm on a programmed value. 13.2 13.3 Embedded Characteristics 32-bit Free-running Counter on prescaled slow clock 16-bit Configurable Prescaler Interrupt on Alarm Block Diagram Figure 13-1.
13.4 Functional Description The Real-time Timer can be used to count elapsed seconds. It is built around a 32-bit counter fed by Slow Clock divided by a programmable 16-bit value. The value can be programmed in the field RTPRES of the Real-time Mode Register (RTT_MR). Programming RTPRES at 0x00008000 corresponds to feeding the real-time counter with a 1 Hz signal (if the Slow Clock is 32.768 kHz). The 32-bit counter can count up to 232 seconds, corresponding to more than 136 years, then roll over to 0.
Figure 13-2. RTT Counting APB cycle APB cycle SCLK RTPRES - 1 Prescaler 0 RTT 0 ...
13.5 Real-time Timer (RTT) User Interface Table 13-1.
13.5.1 Real-time Timer Mode Register Name: RTT_MR Address: 0x400E1A30 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 RTTRST 17 RTTINCIEN 16 ALMIEN 15 14 13 12 11 10 9 8 3 2 1 0 RTPRES 7 6 5 4 RTPRES • RTPRES: Real-time Timer Prescaler Value Defines the number of SLCK periods required to increment the Real-time timer. RTPRES is defined as follows: RTPRES = 0: The prescaler period is equal to 216 * SCLK period.
13.5.2 Real-time Timer Alarm Register Name: RTT_AR Address: 0x400E1A34 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ALMV 23 22 21 20 ALMV 15 14 13 12 ALMV 7 6 5 4 ALMV • ALMV: Alarm Value Defines the alarm value (ALMV+1) compared with the Real-time Timer.
13.5.3 Real-time Timer Value Register Name: RTT_VR Address: 0x400E1A38 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CRTV 23 22 21 20 CRTV 15 14 13 12 CRTV 7 6 5 4 CRTV • CRTV: Current Real-time Value Returns the current value of the Real-time Timer.
13.5.4 Real-time Timer Status Register Name: RTT_SR Address: 0x400E1A3C Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 RTTINC 0 ALMS • ALMS: Real-time Alarm Status 0 = The Real-time Alarm has not occurred since the last read of RTT_SR. 1 = The Real-time Alarm occurred since the last read of RTT_SR.
14. Real-time Clock (RTC) 14.1 Description The Real-time Clock (RTC) peripheral is designed for very low power consumption. It combines a complete time-of-day clock with alarm and a two-hundred-year Gregorian calendar, complemented by a programmable periodic interrupt. The alarm and calendar registers are accessed by a 32-bit data bus. The time and calendar values are coded in binary-coded decimal (BCD) format. The time format can be 24-hour mode or 12-hour mode with an AM/PM indicator.
14.5 Functional Description The RTC provides a full binary-coded decimal (BCD) clock that includes century (19/20), year (with leap years), month, date, day, hours, minutes and seconds. The valid year range is 1900 to 2099 in Gregorian mode, a two-hundred-year calendar. The RTC can operate in 24-hour mode or in 12-hour mode with an AM/PM indicator. Corrections for leap years are included (all years divisible by 4 being leap years). This is correct up to the year 2099. 14.5.
14.5.4 Error Checking Verification on user interface data is performed when accessing the century, year, month, date, day, hours, minutes, seconds and alarms. A check is performed on illegal BCD entries such as illegal date of the month with regard to the year and century configured. If one of the time fields is not correct, the data is not loaded into the register/counter and a flag is set in the validity register. The user can not reset this flag. It is reset as soon as an acceptable value is programmed.
Figure 14-2.
14.6 Real-time Clock (RTC) User Interface Table 14-1.
14.6.1 RTC Control Register Name: RTC_CR Address: 0x400E1A60 Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 – – – – – – 15 14 13 12 11 10 – – – – – – 16 CALEVSEL 9 8 TIMEVSEL 7 6 5 4 3 2 1 0 – – – – – – UPDCAL UPDTIM This register can only be written if the WPEN bit is cleared in “RTC Write Protect Mode Register” on page 259. • UPDTIM: Update Request Time Register 0: No effect. 1: Stops the RTC time counting.
14.6.2 RTC Mode Register Name: RTC_MR Address: 0x400E1A64 Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – HRMOD • HRMOD: 12-/24-hour Mode 0: 24-hour mode is selected. 1: 12-hour mode is selected. All non-significant bits read zero.
14.6.3 RTC Time Register Name: RTC_TIMR Address: 0x400E1A68 Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – AMPM 15 14 10 9 8 2 1 0 HOUR 13 12 – 7 11 MIN 6 5 – 4 3 SEC • SEC: Current Second The range that can be set is 0 - 59 (BCD). The lowest four bits encode the units. The higher bits encode the tens. • MIN: Current Minute The range that can be set is 0 - 59 (BCD). The lowest four bits encode the units.
14.6.4 RTC Calendar Register Name: RTC_CALR Address: 0x400E1A6C Access: Read-write 31 30 – – 23 22 29 28 27 21 20 19 DAY 15 14 26 25 24 18 17 16 DATE MONTH 13 12 11 10 9 8 3 2 1 0 YEAR 7 6 5 – 4 CENT • CENT: Current Century The range that can be set is 19 - 20 (BCD). The lowest four bits encode the units. The higher bits encode the tens. • YEAR: Current Year The range that can be set is 00 - 99 (BCD). The lowest four bits encode the units.
14.6.5 RTC Time Alarm Register Name: RTC_TIMALR Address: 0x400E1A70 Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 21 20 19 18 17 16 10 9 8 2 1 0 23 22 HOUREN AMPM 15 14 HOUR 13 12 MINEN 7 11 MIN 6 5 SECEN 4 3 SEC This register can only be written if the WPEN bit is cleared in “RTC Write Protect Mode Register” on page 259. • SEC: Second Alarm This field is the alarm field corresponding to the BCD-coded second counter.
14.6.6 RTC Calendar Alarm Register Name: RTC_CALALR Address: 0x400E1A74 Access: Read-write 31 30 DATEEN – 29 28 27 26 25 24 18 17 16 DATE 23 22 21 MTHEN – – 20 19 15 14 13 12 11 10 9 8 – – – – – – – – MONTH 7 6 5 4 3 2 1 0 – – – – – – – – This register can only be written if the WPEN bit is cleared in “RTC Write Protect Mode Register” on page 259. • MONTH: Month Alarm This field is the alarm field corresponding to the BCD-coded month counter.
14.6.7 RTC Status Register Name: RTC_SR Address: 0x400E1A78 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – CALEV TIMEV SEC ALARM ACKUPD • ACKUPD: Acknowledge for Update 0: Time and calendar registers cannot be updated. 1: Time and calendar registers can be updated. • ALARM: Alarm Flag 0: No alarm matching condition occurred.
14.6.8 RTC Status Clear Command Register Name: RTC_SCCR Address: 0x400E1A7C Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – CALCLR TIMCLR SECCLR ALRCLR ACKCLR • ACKCLR: Acknowledge Clear 0: No effect. 1: Clears corresponding status flag in the Status Register (RTC_SR). • ALRCLR: Alarm Clear 0: No effect.
14.6.9 RTC Interrupt Enable Register Name: RTC_IER Address: 0x400E1A80 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – CALEN TIMEN SECEN ALREN ACKEN • ACKEN: Acknowledge Update Interrupt Enable 0: No effect. 1: The acknowledge for update interrupt is enabled. • ALREN: Alarm Interrupt Enable 0: No effect.
14.6.10 RTC Interrupt Disable Register Name: RTC_IDR Address: 0x400E1A84 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – CALDIS TIMDIS SECDIS ALRDIS ACKDIS • ACKDIS: Acknowledge Update Interrupt Disable 0: No effect. 1: The acknowledge for update interrupt is disabled. • ALRDIS: Alarm Interrupt Disable 0: No effect.
14.6.11 RTC Interrupt Mask Register Name: RTC_IMR Address: 0x400E1A88 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – CAL TIM SEC ALR ACK • ACK: Acknowledge Update Interrupt Mask 0: The acknowledge for update interrupt is disabled. 1: The acknowledge for update interrupt is enabled.
14.6.12 RTC Valid Entry Register Name: RTC_VER Address: 0x400E1A8C Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – NVCALALR NVTIMALR NVCAL NVTIM • NVTIM: Non-valid Time 0: No invalid data has been detected in RTC_TIMR (Time Register). 1: RTC_TIMR has contained invalid data since it was last programmed.
14.6.13 RTC Write Protect Mode Register Name: RTC_WPMR Address: 0x400E1B44 Access: 31 Read-write 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 — — — — — — — WPEN • WPEN: Write Protect Enable 0: Disables the Write Protect if WPKEY corresponds to 0x525443 (“RTC” in ASCII). 1: Enables the Write Protect if WPKEY corresponds to 0x525443 (“RTC” in ASCII).
15. Watchdog Timer (WDT) 15.1 Description The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It features a 12-bit down counter that allows a watchdog period of up to 16 seconds (slow clock at 32.768 kHz). It can generate a general reset or a processor reset only. In addition, it can be stopped while the processor is in debug mode or idle mode. 15.
15.4 Functional Description The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It is supplied with VDDCORE. It restarts with initial values on processor reset. The Watchdog is built around a 12-bit down counter, which is loaded with the value defined in the field WDV of the Mode Register (WDT_MR). The Watchdog Timer uses the Slow Clock divided by 128 to establish the maximum Watchdog period to be 16 seconds (with a typical Slow Clock of 32.768 kHz).
Figure 15-2.
15.5 Watchdog Timer (WDT) User Interface Table 15-1.
15.5.1 Watchdog Timer Control Register Name: WDT_CR Address: 0x400E1A50 Access: Write-only 31 30 29 28 27 26 25 24 KEY 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 WDRSTT • WDRSTT: Watchdog Restart 0: No effect. 1: Restarts the Watchdog. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation.
15.5.2 Watchdog Timer Mode Register Name: WDT_MR Address: 0x400E1A54 Access: Read-write Once 31 23 30 29 WDIDLEHLT 28 WDDBGHLT 27 21 20 19 11 22 26 25 24 18 17 16 10 9 8 1 0 WDD WDD 15 WDDIS 14 13 12 WDRPROC WDRSTEN WDFIEN 7 6 5 4 WDV 3 2 WDV • WDV: Watchdog Counter Value Defines the value loaded in the 12-bit Watchdog Counter. • WDFIEN: Watchdog Fault Interrupt Enable 0: A Watchdog fault (underflow or error) has no effect on interrupt.
• WDDIS: Watchdog Disable 0: Enables the Watchdog Timer. 1: Disables the Watchdog Timer.
15.5.3 Watchdog Timer Status Register Name: WDT_SR Address: 0x400E1A58 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 WDERR 0 WDUNF • WDUNF: Watchdog Underflow 0: No Watchdog underflow occurred since the last read of WDT_SR. 1: At least one Watchdog underflow occurred since the last read of WDT_SR.
16. Supply Controller (SUPC) 16.1 Description The Supply Controller (SUPC) controls the supply voltage of the Core of the system and manages the Backup Low Power Mode. In this mode, the current consumption is reduced to a few microamps for Backup power retention. Exit from this mode is possible on multiple wake-up sources including events on FWUP or WKUP pins, or a Clock alarm. The SUPC also generates the Slow Clock by selecting either the Low Power RC oscillator or the Low Power Crystal oscillator. 16.
16.3 Block Diagram Figure 16-1.
16.4 Supply Controller Functional Description 16.4.
16.4.2 Slow Clock Generator The Supply Controller embeds a slow clock generator that is supplied with the VDDBU power supply. As soon as the VDDBU is supplied, both the crystal oscillator and the embedded RC oscillator are powered up, but only the embedded RC oscillator is enabled. This allows the slow clock to be valid in a short time (about 100 µs). The user can select the crystal oscillator to be the source of the slow clock, as it provides a more accurate frequency.
Figure 16-2. Separated Backup Supply Powering Scheme FWUP SHDN Backup Batteries VDDBU VDDUTMI VDDANA VDDIO VDDIN Voltage Regulator Main Supply (1.8V-3.6V) VDDOUT VDDCORE VDDPLL Note: Restrictions: With Main Supply < 3V, some peripherals such as USB and ADC might not be operational. Refer to the DC Characteristics of the product for actual possible ranges for such peripherals.
Figure 16-3. No Separated Backup Supply Powering Scheme VDDBU VDDUTMI VDDANA VDDIO Main Supply (1.8V-3.6V) VDDIN Voltage Regulator VDDOUT VDDCORE VDDPLL Note: Restrictions: With Main Supply < 3V, some peripherals such as USB and ADC might not be operational. Refer to the DC Characteristics of the product for actual possible ranges for such peripherals. 16.4.
Waking up the core power supply when a supply monitor detection occurs can be enabled by programming the SMEN bit to 1 in the Supply Controller Wake Up Mode Register (SUPC_WUMR).
16.4.6 Backup Power Supply Reset 16.4.6.1 Raising the Backup Power Supply As soon as the backup voltage VDDUTMI rises, the RC oscillator is powered up and the zero-power power-on reset cell maintains its output low as long as VDDUTMI has not reached its target voltage. During this time, the Supply Controller is entirely reset. When the VDDUTMI voltage becomes valid and zero-power power-on reset signal is released, a counter is started for 5 slow clock cycles.
The NRSTB pin does not need to be driven during power-up phase to allow a reset of the system, it is done by the zero-power power-on cell. Figure 16-6. NRSTB Reset 30 Slow Clock Cycles = about 1ms between 2 and 3 Slow Clock Cycles NRSTB 32 kHz Low Power Crystal Oscillator output SHDN / vr_standby bodcore_in vddcore_nreset Note: periph_nreset, ice_reset and proc_nreset are not shown, but are asserted low thanks to the vddcore_nreset signal controlling the Reset controller. 16.4.6.
16.4.8 Wake Up Sources The wake up events allow the device to exit backup mode. When a wake up event is detected, the Supply Controller performs a sequence which automatically reenables the core power supply. Figure 16-7.
All the resulting signals are wired-ORed to trigger a debounce counter, which can be programmed with the WKUPDBC field in the Supply Controller Wake Up Mode Register (SUPC_WUMR). The WKUPDBC field can select a debouncing period of 3, 32, 512, 4,096 or 32,768 slow clock cycles. This corresponds respectively to about 100 µs, about 1 ms, about 16 ms, about 128 ms and about 1 second (for a typical slow clock frequency of 32 kHz). Programming WKUPDBC to 0x0 selects an immediate wake up, i.e.
16.5 Supply Controller (SUPC) User Interface The User Interface of the Supply Controller is part of the System Controller User Interface. 16.5.1 System Controller (SYSC) User Interface Table 16-1. System Controller Registers Offset System Controller Peripheral Name 0x00-0x0c Reset Controller RSTC 0x10-0x2C Supply Controller SUPC 0x30-0x3C Real Time Timer RTT 0x50-0x5C Watchdog WDT 0x60-0x7C Real Time Clock RTC 0x90-0xDC General Purpose Backup Register GPBR 16.5.
16.5.3 Supply Controller Control Register Name: SUPC_CR Address: 0x400E1A10 Access: Write-only 31 30 29 28 27 26 25 24 KEY 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 – 7 – 6 – 5 – 4 – 3 XTALSEL 2 VROFF 1 – 0 – • VROFF: Voltage Regulator Off 0 (NO_EFFECT) = no effect. 1 (STOP_VREG) = if KEY is correct, asserts vddcore_nreset and stops the voltage regulator. • XTALSEL: Crystal Oscillator Select 0 (NO_EFFECT) = no effect.
16.5.4 Supply Controller Supply Monitor Mode Register Name: SUPC_SMMR Address: 0x400E1A14 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 SMIEN 12 SMRSTEN 11 – 10 9 SMSMPL 8 7 – 6 – 5 – 4 – 3 2 1 0 SMTH • SMTH: Supply Monitor Threshold Value Name Description 0x0 1_9V 1.9 V 0x1 2_0V 2.0 V 0x2 2_1V 2.1 V 0x3 2_2V 2.2 V 0x4 2_3V 2.3 V 0x5 2_4V 2.4 V 0x6 2_5V 2.5 V 0x7 2_6V 2.
• SMSMPL: Supply Monitor Sampling Period Value Name Description 0x0 SMD Supply Monitor disabled 0x1 CSM Continuous Supply Monitor 0x2 32SLCK Supply Monitor enabled one SLCK period every 32 SLCK periods 0x3 256SLCK Supply Monitor enabled one SLCK period every 256 SLCK periods 0x4 2048SLCK Supply Monitor enabled one SLCK period every 2,048 SLCK periods 0x5-0x7 Reserved Reserved • SMRSTEN: Supply Monitor Reset Enable 0 (NOT_ENABLE) = the core reset signal “vddcore_nreset” is not affected w
16.5.5 Supply Controller Mode Register Name: SUPC_MR Address: 0x400E1A18 Access: Read-write 31 30 29 28 27 26 25 24 KEY 23 – 22 – 21 – 20 OSCBYPASS 19 – 18 – 17 – 16 – 15 14 VDDIORDY ONREG 13 12 11 10 9 8 BODDIS BODRSTEN – – – – 5 – 4 – 3 – 2 – 1 – 0 – – 7 – 6 – • BODRSTEN: Brownout Detector Reset Enable 0 (NOT_ENABLE) = the core reset signal “vddcore_nreset” is not affected when a brownout detection occurs.
16.5.6 Supply Controller Wake Up Mode Register Name: SUPC_WUMR Address: 0x400E1A1C Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 13 WKUPDBC 12 11 – 10 9 FWUPDBC 8 7 – 6 – 5 – 4 – 3 RTCEN 2 RTTEN 1 SMEN 0 FWUPEN • FWUPEN: Force Wake Up Enable 0 (NOT_ENABLE) = the Force Wake Up pin has no wake up effect. 1 (ENABLE) = the Force Wake Up pin low forces the wake up of the core power supply.
• WKUPDBC: Wake Up Inputs Debouncer Period Value Name Description 0 IMMEDIATE 1 3_SCLK WKUPx shall be in its active state for at least 3 SLCK periods 2 32_SCLK WKUPx shall be in its active state for at least 32 SLCK periods 3 512_SCLK WKUPx shall be in its active state for at least 512 SLCK periods 4 4096_SCLK WKUPx shall be in its active state for at least 4,096 SLCK periods 5 32768_SCLK WKUPx shall be in its active state for at least 32,768 SLCK periods 6 Reserved Reserved 7 Reserv
16.5.
16.5.
• SMOS: Supply Monitor Output Status 0 (HIGH) = the supply monitor detected VDDUTMI higher than its threshold at its last measurement. 1 (LOW) = the supply monitor detected VDDUTMI lower than its threshold at its last measurement. • OSCSEL: 32-kHz Oscillator Selection Status 0 (RC) = the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator. 1 (CRYST) = the slow clock, SLCK is generated by the 32-kHz crystal oscillator. • FWUPIS: FWUP Input Status 0 (LOW) = FWUP input is tied low.
17. General Purpose Backup Registers (GPBR) 17.1 Description The System Controller embeds Eight general-purpose backup registers. 17.
17.3 General Purpose Backup Registers (GPBR) User Interface Table 17-1. Offset 0x0 ... 0x1c 290 Register Mapping Register Name General Purpose Backup Register 0 SYS_GPBR0 ... ... General Purpose Backup Register 7 SYS_GPBR7 SAM3X / SAM3A [DATASHEET] Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15 Access Reset Read-write – ... ...
17.3.1 General Purpose Backup Register x Name: SYS_GPBRx Address: 0x400E1A90 [0] ..
18. Enhanced Embedded Flash Controller (EEFC) 18.1 Description The Enhanced Embedded Flash Controller (EEFC) ensures the interface of the Flash block with the 32-bit internal bus. Its 128-bit or 64-bit wide memory interface increases performance. It also manages the programming, erasing, locking and unlocking sequences of the Flash using a full set of commands.
18.4 Functional Description 18.4.1 Embedded Flash Organization The embedded Flash interfaces directly with the 32-bit internal bus. The embedded Flash is composed of: One memory plane organized in several pages of the same size. Two 128-bit or 64-bit read buffers used for code read optimization. One 128-bit or 64-bit read buffer used for data read optimization. One write buffer that manages page programming. The write buffer size is equal to the page size.
18.4.2 Read Operations An optimized controller manages embedded Flash reads, thus increasing performance when the processor is running in Thumb2 mode by means of the 128- or 64- bit wide memory interface. The Flash memory is accessible through 8-, 16- and 32-bit reads. As the Flash block size is smaller than the address space reserved for the internal memory area, the embedded Flash wraps around the address space and appears to be repeated within it.
Figure 18-3.
Commands and read operations can be performed in parallel only on different memory planes. Code can be fetched from one memory plane while a write or an erase operation is performed on another. Table 18-2.
Figure 18-5. Command State Chart Read Status: MC_FSR No Check if FRDY flag Set Yes Write FCMD and PAGENB in Flash Command Register Read Status: MC_FSR No Check if FRDY flag Set Yes Check if FLOCKE flag Set Yes Locking region violation No Check if FCMDE flag Set Yes Bad keyword violation No Command Successfull 18.4.3.1 Getting Embedded Flash Descriptor This command allows the system to learn about the Flash organization. The system can take full advantage of this information.
Table 18-3. Flash Descriptor Definition Symbol Word Index Description FL_ID 0 Flash Interface Description FL_SIZE 1 Flash size in bytes FL_PAGE_SIZE 2 Page size in bytes FL_NB_PLANE 3 Number of planes. FL_PLANE[0] 4 Number of bytes in the first plane. FL_PLANE[FL_NB_PLANE-1] 4 + FL_NB_PLANE - 1 Number of bytes in the last plane. FL_NB_LOCK 4 + FL_NB_PLANE Number of lock bits. A bit is associated with a lock region.
By using the WP command, a page can be programmed in several steps if it has been erased before (see Figure 18-6). Figure 18-6. Example of Partial Page Programming 32-bit wide X words X words FF FF FF FF FF FF FF FF FF FF X words FF FF FF FF FF X words 32-bit wide FF FF FF FF FF FF FF FF FF FF FF FF FF FF ... FF FF FF FF FF CA FE FF FF CA FE CA FE FF FF ... FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF ... FF FF FF FF FF FF FF FF FF FF FF FF FF ... Step 1.
One error can be detected in the EEFC_FSR register after a programming sequence: a Command Error: a bad keyword has been written in the EEFC_FCR register. It is possible to clear lock bits previously set. Then the locked region can be erased or programmed. The unlock sequence is: The Clear Lock command (CLB) and a page number to be unprotected are written in the Flash Command Register. When the unlock completes, the FRDY bit in the Flash Programming Status Register (EEFC_FSR) rises.
The status of GPNVM bits can be returned by the Enhanced Embedded Flash Controller (EEFC). The sequence is: Start the Get GPNVM bit command by writing the Flash Command Register with GGPB. The FARG field is meaningless. GPNVM bits can be read by the software application in the EEFC_FRR register. The first word read corresponds to the 32 first GPNVM bits, following reads provide the next 32 GPNVM bits as long as it is meaningful. Extra reads to the EEFC_FRR register return 0.
18.4.3.8 Unique Identifier Each part is programmed with a 128-bit Unique Identifier. It can be used to generate keys for example. To read the Unique Identifier the sequence is: Send the Start Read unique Identifier command (STUI) by writing the Flash Command Register with the STUI command. When the Unique Identifier is ready to be read, the FRDY bit in the Flash Programming Status Register (EEFC_FSR) falls. The Unique Identifier is located in the first 128 bits of the Flash memory mapping.
18.5 Enhanced Embedded Flash Controller (EEFC) User Interface The User Interface of the Enhanced Embedded Flash Controller (EEFC) is integrated within the System Controller with base address 0x400E0A00 and 0x400E0C00. Table 18-4.
18.5.1 EEFC Flash Mode Register Name: EEFC_FMR Address: 0x400E0A00 (0), 0x400E0C00 (1) Access: Read-write Offset: 0x00 31 30 29 28 27 26 25 24 – – – – – – – FAM 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – 7 6 – FWS 5 4 3 2 1 0 – – – – – FRDY • FRDY: Ready Interrupt Enable 0: Flash Ready does not generate an interrupt. 1: Flash Ready (to accept a new command) generates an interrupt.
18.5.2 EEFC Flash Command Register Name: EEFC_FCR Address: 0x400E0A04 (0), 0x400E0C04 (1) Access: Write-only Offset: 0x04 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 FKEY 23 22 21 20 FARG 15 14 13 12 FARG 7 6 5 4 FCMD • FCMD: Flash Command This field defines the flash commands. Refer to “Flash Commands” on page 295. • FARG: Flash Command Argument Erase command For erase all command, this field is meaningless.
18.5.3 EEFC Flash Status Register Name: EEFC_FSR Address: 0x400E0A08 (0), 0x400E0C08 (1) Access: Read-only Offset: 0x08 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – FLOCKE FCMDE FRDY • FRDY: Flash Ready Status 0: The Enhanced Embedded Flash Controller (EEFC) is busy.
18.5.4 EEFC Flash Result Register Name: EEFC_FRR Address: 0x400E0A0C (0), 0x400E0C0C (1) Access: Read-only Offset: 0x0C 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 FVALUE 23 22 21 20 FVALUE 15 14 13 12 FVALUE 7 6 5 4 FVALUE • FVALUE: Flash Result Value The result of a Flash command is returned in this register. If the size of the result is greater than 32 bits, then the next resulting value is accessible at the next register read.
19. Fast Flash Programming Interface (FFPI) 19.1 Description The Fast Flash Programming Interface provides solutions for high-volume programming using a standard gang programmer. The parallel interface is fully handshaked and the device is considered to be a standard EEPROM. Additionally, the parallel protocol offers an optimized access to all the embedded Flash functionalities.
Table 19-1. Signal Name Signal Description List Function Type Active Level Comments Power VDDIO I/O Lines Power Supply Power Apply external 3.0V-3.6V VDDBU Backup I/O Lines Power Supply Power Apply external 3.0V-3.6V VDDUTMI UTMI+ Interface Power Supply Power Apply external 3.0V-3.6V VDDANA ADC Analog Power Supply Power Apply external 3.0V-3.6V VDDIN Voltage Regulator Input Power Apply external 3.0V-3.6V VDDCORE Core Power Supply Power Apply external 1.65V-1.
The table below shows the signal assignment of the PIO lines in FFPI mode Table 19-2. FFPI PIO Assignment FFPI Signal PIO Used PGMNCMD PA0 PGMRDY PA1 PGMNOE PA2 PGMNVALID PA3 PGMM[0] PA4 PGMM[1] PA5 PGMM[2] PA6 PGMM[3] PA7 PGMD[0] PA8 PGMD[1] PA9 PGMD[2] PA10 PGMD[3] PA11 PGMD[4] PA12 PGMD[5] PA13 PGMD[6] PA14 PGMD[7] PA15 PGMD[8] PA16 PGMD[9] PA17 PGMD[10] PA18 PGMD[11] PA19 PGMD[12] PA20 PGMD[13] PA21 PGMD[14] PA22 PGMD[15] PA23 19.2.
Table 19-4.
Figure 19-2. Parallel Programming Timing, Write Sequence NCMD 2 4 3 RDY 5 NOE NVALID DATA[15:0] 1 MODE[3:0] Table 19-5.
19.2.4.2 Read Handshaking For details on the read handshaking sequence, refer to Figure 19-3 and Table 19-6. Figure 19-3. Parallel Programming Timing, Read Sequence NCMD 12 2 3 RDY 13 NOE 9 5 11 7 NVALID 6 4 DATA[15:0] Adress IN Z 8 10 Data OUT X IN 1 MODE[3:0] Table 19-6.
19.2.5.1 Flash Read Command This command is used to read the contents of the Flash memory. The read command can start at any valid address in the memory plane and is optimized for consecutive reads. Read handshaking can be chained; an internal address buffer is automatically increased. Table 19-7.
programmer writes to the first pages of the lock region using Flash write commands and writes to the last page of the lock region using a Flash write and lock command. The Flash command Erase Page and Write (EWP) is equivalent to the Flash Write Command. However, before programming the load buffer, the page is erased. The Flash command Erase Page and Write the Lock (EWPL) combines EWP and WPL commands. 19.2.5.3 Flash Full Erase Command This command is used to erase the Flash memory planes.
Likewise, the Clear GPNVM command (CGPB) is used to clear general-purpose NVM bits. All the generalpurpose NVM bits are also cleared by the EA command. The general-purpose NVM bit is deactivated when the corresponding bit in the pattern value is set to 1. Table 19-12.
19.2.5.7 SAM3X/A Flash Select EEFC Command The commands WPx, EA, xLB, xFB are executed using the current EFC controller. The default EEFC controller is EEFC0. The Select EEFC command (SEFC) allows selection of the current EEFC controller. Table 19-15. Select EFC Command Step Handshake Sequence MODE[3:0] DATA[15:0] 1 Write handshaking CMDE SEFC 2 Write handshaking DATA 0 = Select EEFC0 1 = Select EEFC1 19.2.5.
20. SAM3X/A Boot Program 20.1 Description The SAM-BA Boot Program integrates an array of programs permitting download and/or upload into the different memories of the product. 20.2 Flow Diagram The Boot Program implements the algorithm illustrated in Figure 20-1. Figure 20-1.
20.4 SAM-BA Monitor Once the communication interface is identified, the monitor runs in an infinite loop waiting for different commands as shown in Table 20-1. Table 20-1.
20.4.1 UART Serial Port Communication is performed through the UART initialized to 115200 Baud, 8, n, 1. The Send and Receive File commands use the Xmodem protocol to communicate. Any terminal performing this protocol can be used to send the application file to the target. The size of the binary file to send depends on the SRAM size embedded in the product. In all cases, the size of the binary file must be lower than the SRAM size because the Xmodem protocol requires some SRAM memory to work.
For more details about VID/PID for End Product/Systems, please refer to the Vendor ID form available from the USB Implementers Forum on www.usb.org. Atmel provides an INF example to see the device as a new serial port and also provides another custom driver used by the SAM-BA application: atm6124.sys. Refer to the application note Basic USB Application (Atmel literature number 6123) for more details. 20.4.3.1 Enumeration Process The USB protocol is a master/slave protocol.
IAP software code example: (unsigned int) (*IAP_Function)(unsigned long); void main (void){ unsigned unsigned unsigned unsigned long long long long FlashSectorNum = 200; // flash_cmd = 0; flash_status = 0; EFCIndex = 0; // 0:EEFC0, 1: EEFC1 /* Initialize the function pointer (retrieve function address from NMI vector) */ IAP_Function = ((unsigned long) (*)(unsigned long)) 0x00800008; /* Send your data to the sector here */ /* build the command to send to EEFC */ flash_cmd = (0x5A << 24) | (FlashSectorNu
21. Bus Matrix (MATRIX) 21.1 Description Bus Matrix implements a multi-layer AHB, based on AHB-Lite protocol, that enables parallel access paths between multiple AHB masters and slaves in a system, which increases the overall bandwidth. Bus Matrix interconnects 6 AHB Masters to 9 AHB Slaves. The normal latency to connect a master to a slave is one cycle except for the default master of the accessed slave which is connected directly (zero cycle latency).
21.2.3 Master to Slave Access All the Masters can normally access all the Slaves. However, some paths do not make sense, for example allowing access from the USB High speed DMA to the Internal Peripherals. Thus, these paths are forbidden or simply not wired, and shown as “-” in the following table. Table 21-3.
21.4.3 Fixed Default Master At the end of the current access, if no other request is pending, the slave connects to its fixed default master. Unlike last access master, the fixed master doesn’t change unless the user modifies it by a software action (field FIXED_DEFMSTR of the related MATRIX_SCFG). To change from one kind of default master to another, the Bus Matrix user interface provides the Slave Configuration Registers, one for each slave, that allow to set a default master for each slave.
4. Sixteen beat bursts: predicted end of burst is generated at the end of each sixteen beat boundary inside INCR transfer. This selection can be done through the ULBT field of the Master Configuration Registers (MATRIX_MCFG). 21.5.1.2 Slot Cycle Limit Arbitration The Bus Matrix contains specific logic to break too long accesses such as very long bursts on a very slow slave (e.g. an external low speed memory).
21.6 System I/O Configuration The System I/O Configuration register (CCFG_SYSIO) allows to configure I/O lines in System I/O mode (such as ERASE) or as general purpose I/O lines. Enabling or disabling the corresponding I/O lines in peripheral mode, or in PIO mode (PIO_PER or PIO_PDR registers) in the PIO controller, has no effect. However, the direction (input or output), pull-up and other mode control, is still managed by the PIO controller. 21.
21.8 Bus Matrix (MATRIX) User Interface Table 21-4.
Table 21-4.
21.8.1 Bus Matrix Master Configuration Registers Name: MATRIX_MCFG0..MATRIX_MCFG5 Address: 0x400E0400 Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – ULBT This register can only be written if the WPEN bit is cleared in the “Write Protect Mode Register” .
21.8.2 Bus Matrix Slave Configuration Registers Name: MATRIX_SCFG0..MATRIX_SCFG8 Address: 0x400E0440 Access: Read-write 31 30 29 28 27 26 – – – – – – 23 22 21 20 19 18 – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 FIXED_DEFMSTR 25 24 ARBT 17 16 DEFMSTR_TYPE SLOT_CYCLE This register can only be written if the WPEN bit is cleared in the “Write Protect Mode Register” .
• ARBT: Arbitration Type 0: Round-Robin Arbitration 1: Fixed Priority Arbitration 2: Reserved 3: Reserved 332 SAM3X / SAM3A [DATASHEET] Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
21.8.3 Bus Matrix Priority Registers For Slaves Name: MATRIX_PRAS0..
21.8.4 Bus Matrix Master Remap Control Register Name: MATRIX_MRCR Address: 0x400E0500 Access: Read-write Reset: 0x0000_0000 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – RCB5 RCB4 RCB4 RCB3 RCB2 RCB1 RCB0 This register can only be written if the WPEN bit is cleared in the “Write Protect Mode Register” .
21.8.5 System I/O Configuration Register Name: CCFG_SYSIO Address: 0x400E0514 Access: Read-write Reset: 0x0000_1000 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – SYSIO12 – – – – 7 6 5 4 3 2 1 0 – – – – – – – – • SYSIO12: PC0 or ERASE Assignment 1: ERASE function selected (Default at reset). 0: PC0 function selected.
21.8.6 Write Protect Mode Register Name: MATRIX_WPMR Address: 0x400E05E4 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 – – – – – – – WPEN For more details on MATRIX_WPMR, refer to Section 21.7 “Write Protect Registers” on page 327. • WPEN: Write Protect ENable 0: Disables the Write Protect if WPKEY corresponds to 0x4D4154 (“MAT” in ASCII).
21.8.7 Write Protect Status Register Name: MATRIX_WPSR Address: 0x400E05E8 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 11 10 9 8 WPVSRC 15 14 13 12 WPVSRC 7 6 5 4 3 2 1 0 – – – – – – – WPVS For more details on MATRIX_WPSR, refer to Section 21.7 “Write Protect Registers” on page 327. • WPVS: Write Protect Violation Status 0: No Write Protect Violation has occurred since the last write of MATRIX_WPMR.
22. AHB DMA Controller (DMAC) 22.1 Description The DMA Controller (DMAC) is an AHB-central DMA controller core that transfers data from a source peripheral to a destination peripheral over one or more AMBA buses. One channel is required for each source/destination pair. In the most basic configuration, the DMAC has one master interface and one channel. The master interface reads the data from a source and writes it to a destination. Two AMBA transfers are required for each DMAC data transfer.
The DMA controller can handle the transfer between peripherals and memory and so receives the triggers from the peripherals below. The hardware interface numbers are also given in Table 22-2. Table 22-2.
22.3 Block Diagram Figure 22-1.
22.4 Functional Description 22.4.1 Basic Definitions Source peripheral: Device on an AMBA layer from where the DMAC reads data, which is then stored in the channel FIFO. The source peripheral teams up with a destination peripheral to form a channel. Destination peripheral: Device to which the DMAC writes the stored data from the FIFO (previously read from the source peripheral).
Figure 22-2. DMAC Transfer Hierarchy for Non-Memory Peripheral DMAC Transfer Buffer Buffer Chunk Transfer AMBA Burst Transfer Figure 22-3.
Single-buffer DMAC transfer: Consists of a single buffer. Multi-buffer DMAC transfer: A DMAC transfer may consist of multiple DMAC buffers. Multi-buffer DMAC transfers are supported through buffer chaining (linked list pointers), auto-reloading of channel registers, and contiguous buffers. The source and destination can independently select which method to use.
When the peripheral is not the flow controller, then the last transaction register DMAC_LAST is not used, and the values in these registers are ignored. Chunk Transactions Writing a 1 to the DMAC_CREQ[2x] register starts a source chunk transaction request, where x is the channel number. Writing a 1 to the DMAC_CREQ[2x+1] register starts a destination chunk transfer request, where x is the channel number. Upon completion of the chunk transaction, the hardware clears the DMAC_CREQ[2x] or DMAC_CREQ[2x+1].
The Linked List multi-buffer transfer is initiated by programming DMAC_DSCRx with DSCRx(0) (LLI(0) base address) different from zero. Other fields and registers are ignored and overwritten when the descriptor is retrieved from memory. The last transfer descriptor must be written to memory with its next descriptor address set to 0. Figure 22-4.
22.4.4.3 Ending Multi-buffer Transfers All multi-buffer transfers must end as shown in Row 1 of Table 22-4 on page 345. At the end of every buffer transfer, the DMAC samples the row number, and if the DMAC is in Row 1 state, then the previous buffer transferred was the last buffer and the DMAC transfer is terminated. For rows 2, 3, 4, 5, and 6 (DMAC_CRTLBx.AUTO cleared), the user must set up the last buffer descriptor in memory so that LLI.DMAC_CTRLBx.SRC_DSCR is set to 0. 22.4.
4. After the DMAC selected channel has been programmed, enable the channel by writing a ‘1’ to the DMAC_CHER.ENAx bit, where x is the channel number. Make sure that bit 0 of DMAC_EN.ENABLE register is enabled. 5. Source and destination request single and chunk DMAC transactions to transfer the buffer of data (assuming non-memory peripherals). The DMAC acknowledges at the completion of every transaction (chunk and single) in the buffer and carries out the buffer transfer. 6.
11. Finally, enable the channel by writing a ‘1’ to the DMAC_CHER.ENAx bit, where x is the channel number. The transfer is performed. 12. The DMAC fetches the first LLI from the location pointed to by DMAC_DSCRx(0). Note: The LLI.DMAC_SADDRx, LLI. DMAC_DADDRx, LLI.DMAC_DSCRx, LLI.DMAC_CTRLAx and LLI.DMAC_CTRLBx registers are fetched. The DMAC automatically reprograms the DMAC_SADDRx, DMAC_DADDRx, DMAC_DSCRx, DMAC_CTRLBx and DMAC_CTRLAx channel registers from the DMAC_DSCRx(0). 13.
Figure 22-6. Multi-buffer with Linked Address for Source and Destination Buffers are Contiguous Address of Source Layer Address of Destination Layer Buffer 2 DADDR(3) Buffer 2 Buffer 2 SADDR(3) DADDR(2) Buffer 2 Buffer 1 SADDR(2) DADDR(1) Buffer 1 SADDR(1) Buffer 0 DADDR(0) Buffer 0 SADDR(0) Source Buffers Destination Buffers The DMAC transfer flow is shown in Figure 22-7 on page 350.
Figure 22-7. DMAC Transfer Flow for Source and Destination Linked List Address Channel enabled by software LLI Fetch Hardware reprograms SADDRx, DADDRx, CTRLA/Bx, DSCRx DMAC buffer transfer Writeback of DMAC_CTRLAx register in system memory Chained Buffer Transfer Completed Interrupt generated here Is DMAC in Row 1 of DMAC State Machine Table? DMAC Chained Buffer Transfer Completed Interrupt generated here no yes Channel disabled by hardware 350 ̶ i.
̶ ii. If the hardware handshaking interface is activated for the source or destination peripheral, assign handshaking interface to the source and destination peripheral. This requires programming the SRC_PER and DST_PER bits, respectively. 16. Source and destination request single and chunk DMAC transactions to transfer the buffer of data (assuming non-memory peripherals). The DMAC acknowledges on completion of each chunk/single transaction and carries out the buffer transfer. a.
a. Designate the handshaking interface type (hardware or software) for the source and destination peripherals. This is not required for memory. This step requires programming the SRC_H2SEL/DST_H2SEL bits, respectively. Writing a ‘1’ activates the hardware handshaking interface to handle source/destination requests for the specific channel. Writing a ‘0’ activates the software handshaking interface to handle source/destination requests. b.
Figure 22-8. DMAC Transfer with Linked List Source Address and Contiguous Destination Address Address of Source Layer Address of Destination Layer Buffer 2 SADDR(2) Buffer 2 DADDR(2) Buffer 1 Buffer 1 SADDR(1) DADDR(1) Buffer 0 DADDR(0) Buffer 0 SADDR(0) Source Buffers Destination Buffers The DMAC transfer flow is shown in Figure 22-9 on page 354.
Figure 22-9.
22.4.6 Disabling a Channel Prior to Transfer Completion Under normal operation, the software enables a channel by writing a ‘1’ to the Channel Handler Enable Register, DMAC_CHER.ENAx, and the hardware disables a channel on transfer completion by clearing the DMAC_CHSR.ENAx register bit. The recommended way for software to disable a channel without losing data is to use the SUSPx bit in conjunction with the EMPTx bit in the Channel Handler Status Register. 1.
22.5 356 DMAC Software Requirements There must not be any write operation to Channel registers in an active channel after the channel enable is made HIGH. If any channel parameters must be reprogrammed, this can only be done after disabling the DMAC channel. When the destination peripheral has been defined as the flow controller, source single transfer requests are not serviced until the destination peripheral has asserted its Last Transfer Flag.
22.6 Write Protection Registers To prevent any single software error that may corrupt the DMAC behavior, the DMAC address space can be writeprotected by setting the WPEN bit in the “DMAC Write Protect Mode Register” (DMAC_WPMR). If a write access to anywhere in the DMAC address space is detected, then the WPVS flag in the DMAC Write Protect Status Register (MCI_WPSR) is set, and the WPVSRC field indicates in which register the write access has been attempted.
22.7 AHB DMA Controller (DMAC) User Interface Table 22-5.
22.7.1 DMAC Global Configuration Register Name: DMAC_GCFG Address: 0x400C4000 Access: Read-write Reset: 0x00000010 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 ARB_CFG 3 – 2 – 1 – 0 – Note: Bit fields 0, 1, 2, 3, have a default value of 0. This should not be changed. This register can only be written if the WPEN bit is cleared in “DMAC Write Protect Mode Register” .
22.7.2 DMAC Enable Register Name: DMAC_EN Address: 0x400C4004 Access: Read-write Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 ENABLE This register can only be written if the WPEN bit is cleared in “DMAC Write Protect Mode Register” . • ENABLE 0: DMA Controller is disabled. 1: DMA Controller is enabled.
22.7.3 DMAC Software Single Request Register Name: DMAC_SREQ Address: 0x400C4008 Access: Read-write Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 DSREQ5 10 SSREQ5 9 DSREQ4 8 SSREQ4 7 DSREQ3 6 SSREQ3 5 DSREQ2 4 SSREQ2 3 DSREQ1 2 SSREQ1 1 DSREQ0 0 SSREQ0 • DSREQx: Destination Request Request a destination single transfer on channel i.
22.7.4 DMAC Software Chunk Transfer Request Register Name: DMAC_CREQ Address: 0x400C400C Access: Read-write Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 DCREQ5 10 SCREQ5 9 DCREQ4 8 SCREQ4 7 DCREQ3 6 SCREQ3 5 DCREQ2 4 SCREQ2 3 DCREQ1 2 SCREQ1 1 DCREQ0 0 SCREQ0 • DCREQx: Destination Chunk Request Request a destination chunk transfer on channel i.
22.7.
22.7.6 DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Enable Register Name: DMAC_EBCIER Address: 0x400C4018 Access: Write-only Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 ERR5 20 ERR4 19 ERR3 18 ERR2 17 ERR1 16 ERR0 15 – 14 – 13 CBTC5 12 CBTC4 11 CBTC3 10 CBTC2 9 CBTC1 8 CBTC0 7 – 6 – 5 BTC5 4 BTC4 3 BTC3 2 BTC2 1 BTC1 0 BTC0 • BTCx: Buffer Transfer Completed [5:0] Buffer Transfer Completed Interrupt Enable Register.
22.7.7 DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Disable Register Name: DMAC_EBCIDR Address: 0x400C401C Access: Write-only Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 ERR5 20 ERR4 19 ERR3 18 ERR2 17 ERR1 16 ERR0 15 – 14 – 13 CBTC5 12 CBTC4 11 CBTC3 10 CBTC2 9 CBTC1 8 CBTC0 7 – 6 – 5 BTC5 4 BTC4 3 BTC3 2 BTC2 1 BTC1 0 BTC0 • BTCx: Buffer Transfer Completed [5:0] Buffer transfer completed Disable Interrupt Register.
22.7.
22.7.9 DMAC Error, Buffer Transfer and Chained Buffer Transfer Status Register Name: DMAC_EBCISR Address: 0x400C4024 Access: Read-only Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 ERR5 20 ERR4 19 ERR3 18 ERR2 17 ERR1 16 ERR0 15 – 14 – 13 CBTC5 12 CBTC4 11 CBTC3 10 CBTC2 9 CBTC1 8 CBTC0 7 – 6 – 5 BTC5 4 BTC4 3 BTC3 2 BTC2 1 BTC1 0 BTC0 • BTCx: Buffer Transfer Completed [5:0] When BTC[i] is set, Channel i buffer transfer has terminated.
22.7.10 DMAC Channel Handler Enable Register Name: DMAC_CHER Address: 0x400C4028 Access: Write-only Reset: 0x00000000 31 – 30 – 29 KEEP5 28 KEEP4 27 KEEP3 26 KEEP2 25 KEEP1 24 KEEP0 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 SUSP5 12 SUSP4 11 SUSP3 10 SUSP2 9 SUSP1 8 SUSP0 7 – 6 – 5 ENA5 4 ENA4 3 ENA3 2 ENA2 1 ENA1 0 ENA0 • ENAx: Enable [5:0] When set, a bit of the ENA field enables the relevant channel.
22.7.11 DMAC Channel Handler Disable Register Name: DMAC_CHDR Address: 0x400C402C Access: Write-only Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 RES5 12 RES4 11 RES3 10 RES2 9 RES1 8 RES0 7 – 6 – 5 DIS5 4 DIS4 3 DIS3 2 DIS2 1 DIS1 0 DIS0 • DISx: Disable [5:0] Write one to this field to disable the relevant DMAC Channel. The content of the FIFO is lost and the current AHB access is terminated.
22.7.12 DMAC Channel Handler Status Register Name: DMAC_CHSR Address: 0x400C4030 Access: Read-only Reset: 0x00FF0000 31 – 30 – 29 STAL5 28 STAL4 27 STAL3 26 STAL2 25 STAL1 24 STAL0 23 – 22 – 21 EMPT5 20 EMPT4 19 EMPT3 18 EMPT2 17 EMPT1 16 EMPT0 15 – 14 – 13 SUSP5 12 SUSP4 11 SUSP3 10 SUSP2 9 SUSP1 8 SUSP0 7 – 6 – 5 ENA5 4 ENA4 3 ENA3 2 ENA2 1 ENA1 0 ENA0 • ENAx: Enable [5:0] A one in any position of this field indicates that the relevant channel is enabled.
22.7.13 DMAC Channel x [x = 0..5] Source Address Register Name: DMAC_SADDRx [x = 0..5] Address: 0x400C403C [0], 0x400C4064 [1], 0x400C408C [2], 0x400C40B4 [3], 0x400C40DC [4], 0x400C4104 [5] Access: Read-write Reset: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 SADDR 23 22 21 20 SADDR 15 14 13 12 SADDR 7 6 5 4 SADDR This register can only be written if the WPEN bit is cleared in “DMAC Write Protect Mode Register” .
22.7.14 DMAC Channel x [x = 0..5] Destination Address Register Name: DMAC_DADDRx [x = 0..5] Address: 0x400C4040 [0], 0x400C4068 [1], 0x400C4090 [2], 0x400C40B8 [3], 0x400C40E0 [4], 0x400C4108 [5] Access: Read-write Reset: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 DADDR 23 22 21 20 DADDR 15 14 13 12 DADDR 7 6 5 4 DADDR This register can only be written if the WPEN bit is cleared in “DMAC Write Protect Mode Register” .
22.7.15 DMAC Channel x [x = 0..5] Descriptor Address Register Name: DMAC_DSCRx [x = 0..5] Address: 0x400C4044 [0], 0x400C406C [1], 0x400C4094 [2], 0x400C40BC [3], 0x400C40E4 [4], 0x400C410C [5] Access: Read-write Reset: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 DSCR 23 22 21 20 DSCR 15 14 13 12 DSCR 7 6 5 4 DSCR 0 – This register can only be written if the WPEN bit is cleared in “DMAC Write Protect Mode Register” .
22.7.16 DMAC Channel x [x = 0..5] Control A Register Name: DMAC_CTRLAx [x = 0..
• DCSIZE: Destination Chunk Transfer Size Value Name Description 000 CHK_1 1 data transferred 001 CHK_4 4 data transferred 010 CHK_8 8 data transferred 011 CHK_16 16 data transferred 100 CHK_32 32 data transferred 101 CHK_64 64 data transferred 110 CHK_128 128 data transferred 111 CHK_256 256 data transferred • SRC_WIDTH: Transfer Width for the Source Value Name Description 00 BYTE the transfer size is set to 8-bit width 01 HALF_WORD the transfer size is set to 16-bit widt
22.7.17 DMAC Channel x [x = 0..5] Control B Register Name: DMAC_CTRLBx [x = 0..
• DST_INCR: Incrementing, Decrementing or Fixed Address for the Destination Value Name Description 00 INCREMENTING The destination address is incremented 01 DECREMENTING The destination address is decremented 10 FIXED The destination address remains unchanged • IEN If this bit is cleared, when the buffer transfer is completed, the BTCx flag is set in the EBCISR status register. This bit is active low.
22.7.18 DMAC Channel x [x = 0..5] Configuration Register Name: DMAC_CFGx [x = 0..
• LOCK_IF_L: Master Interface Arbiter Lock 0 (CHUNK): The Master Interface Arbiter is locked by the channel x for a chunk transfer. 1 (BUFFER): The Master Interface Arbiter is locked by the channel x for a buffer transfer. • AHB_PROT: AHB Protection AHB_PROT field provides additional information about a bus access and is primarily used to implement some level of protection.
22.7.19 DMAC Write Protect Mode Register Name: DMAC_WPMR Address: 0x400C41E4 Access: Read-write Reset: See Table 22-5 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 — — — — — — — WPEN • WPEN: Write Protect Enable 0 = Disables the Write Protect if WPKEY corresponds to 0x444D4143 (“DMAC” in ASCII). 1 = Enables the Write Protect if WPKEY corresponds to 0x444D4143 (“DMAC” in ASCII).
22.7.20 DMAC Write Protect Status Register Name: DMAC_WPSR Address: 0x400C41E8 Access: Read-only Reset: See Table 22-5 31 30 29 28 27 26 25 24 — — — — — — — — 23 22 21 20 19 18 17 16 11 10 9 8 WPVSRC 15 14 13 12 WPVSRC 7 6 5 4 3 2 1 0 — — — — — — — WPVS • WPVS: Write Protect Violation Status 0 = No Write Protect Violation has occurred since the last read of the DMAC_WPSR register.
23. External Memory Bus 23.1 Description The external memory bus allows external devices connection to the various embedded memory controllers of the microcontroller. The external memory bus handles control, address and data bus of each embedded memory controllers. The SAM3X embeds a Static Memory/NAND Flash/ECC Controller (SMC/NFC/ECC) and a SDRSDRAM Controller (SDR-SDRAMC).
23.3 Block Diagram Figure 23-1.
23.4 I/O Lines Description Table 23-1.
Table 23-2 details the connections between the two memory controllers and the bus pins. Table 23-2. 23.5 External Memory Bus Pins and Memory Controllers I/O Lines Connections EBI Pins SDRAMC I/O Lines SMC I/O Lines NWR1/NBS1 NBS1 NWR1/NBS1 A0/NBS0 Not Supported A0/NBS0 A1 Not Supported A1 A[11:2] A[9:0] A[11:2] SDA10 A10 Not Supported A12 Not Supported A12 A[14:13] A[12:11] A[14:13] A[23:15] Not Supported A[23:15] D[15:0] D[15:0] D[15:0] Application Example 23.5.
Table 23-3.
23.7 Functional Description The external memory bus transfers data between the internal AHB Bus (handled by the memory controllers) and the external memories or peripheral devices. It controls the waveforms and the parameters of the external address, data and control buses and is composed of the following elements: Static Memory Controller (SMC) NAND Flash Controller (NFC) SDRAM Controller (SDRAMC) ECC Controller (ECC) 23.7.
23.8 Implementation Examples 23.8.1 SDR-SDRAM 23.8.1.1 Software Configuration (2 x 8-bit SDR-SDRAM) The following configuration must be respected: Address lines A[2..11], A[13], BA0, BA1, SDA10, SDCS, SDWE, SDCKE, NBS1, RAS, CAS, and data lines D[0..15] are multiplexed with PIO lines and thus dedicated PIOs must be programmed in peripheral mode in the PIO controller. Initialize the SDRAM Controller depending on the SDRAM device and system bus frequency.
23.8.1.2 Software Configuration (1 x 16-bit SDR-SDRAM) The following configuration must be respected: Address lines A[2..11], A[13-14], BA0, BA1, SDA10, SDCS, SDWE, SDCKE, NBS1, RAS, CAS, and data lines D[0..15] are multiplexed with PIO lines and thus dedicated PIOs must be programmed in peripheral mode in the PIO controller. Initialize the SDRAM Controller depending on the SDRAM device and system bus frequency. The SDRAM initialization sequence is described in Section 24.5.
23.8.2 8-bit and 16-bit NAND Flash 23.8.2.1 Software Configuration (8-bit and 16-bit NAND Flash) The following configuration must be respected: NADNCLE, NANDALE, NANDOE, NANDRDY and NANDWE signals are multiplexed with PIO lines and thus the dedicated PIOs must be programmed in peripheral mode in the PIO controller. D[0:7] or D[0:15] must be programmed in peripheral mode in the PIO controller. Assign the SMC chip select line CSx to the NAND Flash by setting the CSID field in the NFCADDR_CMD Register.
23.8.3 NOR Flash on NCS0 23.8.3.1 Software Configuration (NOR Flash on NCS0) Address lines A[1..22], NCS0, NRD, NWE and data lines D[0..15] are multiplexed with PIO lines and thus dedicated PIOs must be programmed in peripheral mode in the PIO controller. The default configuration for the Static Memory Controller, byte select mode, 16-bit data bus, Read/Write controlled by Chip Select, allows access on 16-bit non-volatile memory at slow clock.
24. AHB SDRAM Controller (SDRAMC) 24.1 Description The SDRAM Controller (SDRAMC) extends the memory capabilities of a chip by providing the interface to an external 16-bit DRAM device. The page size supports ranges from 2048 to 8192 and the number of columns from 256 to 2048. It supports byte (8-bit), half-word (16-bit) and word (32-bit) accesses. The SDRAM Controller supports a read or write burst length of one location.
24.3 I/O Lines Description Table 24-1.
24.4 Application Example 24.4.1 Software Interface The SDRAM address space is organized into banks, rows, and columns. The SDRAM controller allows mapping different memory types according to the values set in the SDRAMC configuration register. The SDRAM Controller’s function is to make the SDRAM device access protocol transparent to the user. Table 242 to Table 24-4 illustrate the SDRAM device memory mapping seen by the user in correlation with the device structure. Various configurations are illustrated.
24.5 Product Dependencies 24.5.1 SDRAM Device Initialization The initialization sequence is generated by software. The SDRAM devices are initialized by the following sequence: 1. SDRAM features must be set in the configuration register: asynchronous timings (TRC, TRAS, etc.), number of columns, rows, CAS latency, and the data bus width. 2. For mobile SDRAM, temperature-compensated self refresh (TCSR), drive strength (DS) and partial array self refresh (PASR) must be set in the Low Power Register. 3.
Figure 24-1. SDRAM Device Initialization Sequence SDCKE tRP tRC tMRD SDCK SDRAMC_A[9:0] A10 SDRAMC_A[12:11] SDCS RAS CAS SDWE NBS Inputs Stable for 200 μsec Precharge All Banks 1st Auto-refresh 8th Auto-refresh MRS Command Valid Command 24.5.2 I/O Lines The pins used for interfacing the SDRAM Controller may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the SDRAM Controller pins to their peripheral function.
24.5.4 Power Management The SDRAM Controller may be clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the SDRAM Controller clock. The SDRAM Controller Clock (not the SDCK pin) is managed by the Static Memory Controller Clock. The SDRAM Clock on SDCK pin will be output as soon as the first access to the SDRAM is done during the initialization phase.
24.6 Functional Description 24.6.1 SDRAM Controller Write Cycle The SDRAM Controller allows burst access or single access. In both cases, the SDRAM controller keeps track of the active row in each bank, thus maximizing performance. To initiate a burst access, the SDRAM Controller uses the transfer type signal provided by the master requesting the access. If the next access is a sequential write access, writing to the SDRAM device is carried out.
24.6.2 SDRAM Controller Read Cycle The SDRAM Controller allows burst access, incremental burst of unspecified length or single access. In all cases, the SDRAM Controller keeps track of the active row in each bank, thus maximizing performance of the SDRAM. If row and bank addresses do not match the previous row/bank address, then the SDRAM controller automatically generates a precharge command, activates the new row and starts the read command.
24.6.3 Border Management When the memory row boundary has been reached, an automatic page break is inserted. In this case, the SDRAM controller generates a precharge command, activates the new row and initiates a read or write command. To comply with SDRAM timing parameters, an additional clock cycle is inserted between the precharge/active (tRP) command and the active/read (tRCD) command. This is described in Figure 24-4 below. Figure 24-4.
24.6.4 SDRAM Controller Refresh Cycles An auto-refresh command is used to refresh the SDRAM device. Refresh addresses are generated internally by the SDRAM device and incremented after each auto-refresh automatically. The SDRAM Controller generates these auto-refresh commands periodically. An internal timer is loaded with the value in the register SDRAMC_TR that indicates the number of clock cycles between refresh cycles.
24.6.5.1 Self-refresh Mode This mode is selected by programming the LPCB field to 1 in the SDRAMC Low Power Register. In self-refresh mode, the SDRAM device retains data without external clocking and provides its own internal clocking, thus performing its own auto-refresh cycles. All the inputs to the SDRAM device become “don’t care” except SDCKE, which remains low. As soon as the SDRAM device is selected, the SDRAM Controller provides a sequence of commands and exits self-refresh mode.
24.6.5.2 Low-power Mode This mode is selected by programming the LPCB field to 2 in the SDRAMC Low Power Register. Power consumption is greater than in self-refresh mode. All the input and output buffers of the SDRAM device are deactivated except SDCKE, which remains low. In contrast to self-refresh mode, the SDRAM device cannot remain in low-power mode longer than the refresh period (64 ms for a whole device refresh operation).
24.6.5.3 Deep Power-down Mode This mode is selected by programming the LPCB field to 3 in the SDRAMC Low Power Register. When this mode is activated, all internal voltage generators inside the SDRAM are stopped and all data is lost. When this mode is enabled, the application must not access to the SDRAM until a new initialization sequence is done (See “SDRAM Device Initialization” on page 395). This is described in Figure 24-8. Figure 24-8.
24.7 AHB SDRAM Controller (SDRAMC) User Interface Table 24-6.
24.7.1 SDRAMC Mode Register Name: SDRAMC_MR Address: 0x400E0200 Access: Read-write Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 1 0 MODE • MODE: SDRAMC Command Mode This field defines the command issued by the SDRAM Controller when the SDRAM device is accessed. Value Name Description 000 NORMAL Normal mode. Any access to the SDRAM is decoded normally.
24.7.2 SDRAMC Refresh Timer Register Name: SDRAMC_TR Address: 0x400E0204 Access: Read-write Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 10 9 8 7 6 5 4 1 0 COUNT 3 2 COUNT • COUNT: SDRAMC Refresh Timer Count This 12-bit field is loaded into a timer that generates the refresh pulse. Each time the refresh pulse is generated, a refresh burst is initiated.
24.7.3 SDRAMC Configuration Register Name: SDRAMC_CR Address: 0x400E0208 Access: Read-write Reset: 0x852372C0 31 30 29 28 27 26 TXSR 23 22 21 20 19 18 TRCD 15 13 12 11 10 TRC_TRFC 6 17 16 9 8 TWR 5 4 NB CAS 3 2 NR Warning: bit 7 (DBW) must always be set to 1 when programming the SDRAMC_CR register. • NC: Number of Column Bits Reset value is 8 column bits.
• CAS: CAS Latency Reset value is two cycles. In the SDRAMC, only a CAS latency of one, two and three cycles are managed. Value Name Description 01 LATENCY1 1 cycle CAS latency 10 LATENCY2 2 cycle CAS latency 11 LATENCY3 3 cycle CAS latency Values which are not listed in the table must be considered as “reserved”. • DBW: Data Bus Width Reset value is 16 bits This field defines the Data Bus Width, which is 16 bits. It must be set to 1. • TWR: Write Recovery Delay Reset value is two cycles.
24.7.
• DS: Drive Strength (only for low-power SDRAM) DS parameter is transmitted to the SDRAM during initialization to select the SDRAM strength of data output. This parameter must be set according to the SDRAM device specification. After initialization, as soon as DS field is modified and self-refresh mode is activated, the Extended Mode Register is accessed automatically and DS bits are updated before entry in self-refresh mode.
24.7.5 SDRAMC Interrupt Enable Register Name: SDRAMC_IER Address: 0x400E0214 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 RES • RES: Refresh Error Status 0: No effect. 1: Enables the refresh error interrupt.
24.7.6 SDRAMC Interrupt Disable Register Name: SDRAMC_IDR Address: 0x400E0218 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 RES • RES: Refresh Error Status 0: No effect. 1: Disables the refresh error interrupt.
24.7.7 SDRAMC Interrupt Mask Register Name: SDRAMC_IMR Address: 0x400E021C Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 RES • RES: Refresh Error Status 0: The refresh error interrupt is disabled. 1: The refresh error interrupt is enabled.
24.7.8 SDRAMC Interrupt Status Register Name: SDRAMC_ISR Address: 0x400E0220 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 RES • RES: Refresh Error Status 0: No refresh error has been detected since the register was last read. 1: A refresh error has been detected since the register was last read.
24.7.9 SDRAMC Memory Device Register Name: SDRAMC_MDR Address: 0x400E0224 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 • MD: Memory Device Type Value Name Description 00 SDRAM SDRAM 01 LPSDRAM Low-power SDRAM Values which are not listed in the table must be considered as “reserved”.
24.7.10 SDRAMC Configuration 1 Register Name: SDRAMC_CR1 Address: 0x400E0228 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 2 1 0 TMRD • TMRD: Load Mode Register Command to Active or Refresh Command Reset Value is 2 cycles. This field defines the delay between a Load mode register command and an active or refresh command in number of cycles.
24.7.11 SDRAMC OCMS Register Name: SDRAMC_OCMS Address: 0x400E022C Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 SDR_SE • SDR_SE: SDRAM Memory Controller Scrambling Enable 0: Disable “Off Chip” Scrambling for SDR-SDRAM access. 1: Enable “Off Chip” Scrambling for SDR-SDRAM access.
25. Static Memory Controller (SMC) 25.1 Description The External Bus Interface is designed to ensure the successful data transfer between several external devices and the Cortex-M3 based device. The External Bus Interface of the SAM3X consists of a Static Memory Controller (SMC). This SMC is capable of handling several types of external memory and peripheral devices, such as SRAM, PSRAM, PROM, EPROM, EEPROM, LCD Module, NOR Flash and NAND Flash.
25.
Block Diagram Figure 25-1. Block Diagram SMC AHB Interface NAND Flash Controller (NFC) AHB arbiter Scrambler 25.3 D[15:0] A[0]/NBS0 A[20:1] A21/NANDALE A22/NANDCLE A23 NCS[3:0] SMC Interface ECC SRAM AHB Interface 25.4 User Interface NFC (4 K bytes) Internal SRAM Control & Status Registers NRD NWR0/NWE NWR1/NBS1 NANDOE NANDWE NANDRDY NWAIT I/O Lines Description Table 25-1.
25.5 Multiplexed Signals Table 25-2. Static Memory Controller (SMC) Multiplexed Signals Multiplexed Signals Related Function NWR0 NWE Byte-write or byte-select access, see Figure 25-4 "Memory Connection for an 8-bit Data Bus" and Figure 25-5 "Memory Connection for a 16-bit Data Bus" A0 NBS0 8-bit or 16-bit data bus, see Section 25.9.
25.7 Product Dependencies 25.7.1 I/O Lines The pins used for interfacing the Static Memory Controller are multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the Static Memory Controller pins to their peripheral function. If I/O Lines of the SMC are not used by the application, they can be used for other purposes by the PIO Controller. 25.7.
Figure 25-3.
25.9 Connection to External Devices 25.9.1 Data Bus Width A data bus width of 8 or 16 bits can be selected for each chip select. This option is controlled by the field DBW in SMC_MODE (Mode Register) for the corresponding chip select. Figure 25-4 shows how to connect a 512K x 8-bit memory on NCS2. Figure 25-5 shows how to connect a 512K x 16-bit memory on NCS2. 25.9.
25.9.2.2 Byte Select Access In this mode, read/write operations can be enabled/disabled at byte level. One byte-select line per byte of the data bus is provided. One NRD and one NWE signal control read and write. For 16-bit devices: the SMC provides NBS0 and NBS1 selection signals for respectively byte0 (lower byte) and byte1 (upper byte) of a 16-bit bus. Byte Select Access is used to connect one 16-bit device. Figure 25-6.
25.10 Standard Read and Write Protocols In the following sections, the byte access type is not considered. Byte select lines (NBS0 to NBS1) always have the same timing as the A address bus. NWE represents either the NWE signal in byte select access type or one of the byte write lines (NWR0 to NWR1) in byte write access type. NWR0 to NWR3 have the same timings and protocol as NWE. In the same way, NCS represents one of the NCS[0..7] chip select lines. 25.10.
25.10.1.2 NCS Waveform Similarly, the NCS signal can be divided into a setup time, pulse length and hold time: 1. NCS_RD_SETUP: the NCS setup time is defined as the setup time of address before the NCS falling edge. 2. NCS_RD_PULSE: the NCS pulse length is the time between NCS falling edge and NCS rising edge. 3. NCS_RD_HOLD: the NCS hold time is defined as the hold time of address after the NCS rising edge. 25.10.1.3 Read Cycle The NRD_CYCLE time is defined as the total duration of the read cycle, i.
25.10.2.1 Read is Controlled by NRD (READ_MODE = 1): Figure 25-8 shows the waveforms of a read operation of a typical asynchronous RAM. The read data is available tPACC after the falling edge of NRD, and turns to ‘Z’ after the rising edge of NRD. In this case, the READ_MODE must be set to 1 (read is controlled by NRD), to indicate that data is available with the rising edge of NRD.
25.10.2.2 Read is Controlled by NCS (READ_MODE = 0) Figure 25-9 shows the typical read cycle. The read data is valid tPACC after the falling edge of the NCS signal and remains valid until the rising edge of NCS. Data must be sampled when NCS is raised. In that case, the READ_MODE must be set to 0 (read is controlled by NCS): the SMC internally samples the data on the rising edge of Master Clock that generates the rising edge of NCS, whatever the programmed waveform of NRD may be. Figure 25-9.
25.10.3 Write Waveforms The write protocol is similar to the read protocol. It is depicted in Figure 25-10. The write cycle starts with the address setting on the memory address bus. 25.10.3.1 NWE Waveforms The NWE signal is characterized by a setup timing, a pulse width and a hold timing. 1. NWE_SETUP: the NWE setup time is defined as the setup of address and data before the NWE falling edge. 2. NWE_PULSE: The NWE pulse length is the time between NWE falling edge and NWE rising edge. 3.
25.10.3.3 Write Cycle The write cycle time is defined as the total duration of the write cycle, that is, from the time where address is set on the address bus to the point where address may change. The total write cycle time is equal to: NWE_CYCLE = NWE_SETUP + NWE_PULSE + NWE_HOLD = NCS_WR_SETUP + NCS_WR_PULSE + NCS_WR_HOLD All NWE and NCS (write) timings are defined separately for each chip select as an integer number of Master Clock cycles.
25.10.4.2 Write is Controlled by NCS (WRITE_MODE = 0) Figure 25-12 shows the waveforms of a write operation with WRITE_MODE set to 0. The data is put on the bus during the pulse and hold steps of the NCS signal. The internal data buffers are turned out after the NCS_WR_SETUP time, and until the end of the write cycle, regardless of the programmed waveform on NWE. Figure 25-12. WRITE_MODE = 0. The write operation is controlled by NCS MCK A[23:2] NBS0, NBS1, A0, A1 NWE, NWR0, NWR1 NCS D[15:0] 25.10.
25.10.6 Reset Values of Timing Parameters Table 25-7 gives the default value of timing parameters at reset. Table 25-7. Reset Values of Timing Parameters Register Reset Value Description SMC_SETUP 0x01010101 All setup timings are set to 1 SMC_PULSE 0x01010101 All pulse timings are set to 1 SMC_CYCLE 0x00030003 The read and write operation last 3 Master Clock cycles and provide one hold cycle WRITE_MODE 1 Write is controlled with NWE READ_MODE 1 Read is controlled with NRD 25.10.
When multiple chip selects (external SRAM) are handled, it is possible to configure the scrambling function per chip select using the OCMS field in the SMC_TIMINGS registers. To scramble the NAND Flash contents, the SRSE field must be set in the SMC_OCMS register. When NAND Flash memory content is scrambled, the on-chip SRAM page buffer associated for the transfer is also scrambled. 25.
25.12.2 Early Read Wait State In some cases, the SMC inserts a wait state cycle between a write access and a read access to allow time for the write cycle to end before the subsequent read cycle begins. This wait state is not generated in addition to a chip select wait state. The early read cycle thus only occurs between a write and read access to the same memory device (same chip select).
Figure 25-15. Early Read Wait State: NCS Controlled Write with No Hold Followed by a Read with No NCS Setup MCK A[23:2] NBS0, NBS1, A0,A1 NCS NRD no hold no setup D[15:0] write cycle (WRITE_MODE = 0) Early Read wait state read cycle (READ_MODE = 0 or READ_MODE = 1) Figure 25-16.
25.12.3 Reload User Configuration Wait State The user may change any of the configuration parameters by writing the SMC user interface. When detecting that a new user configuration has been written in the user interface, the SMC inserts a wait state before starting the next access. The so called “Reload User Configuration Wait State” is used by the SMC to load the new set of parameters to apply to next accesses. The Reload Configuration Wait State is not applied in addition to the Chip Select Wait State.
Figure 25-17 illustrates the Data Float Period in NRD-controlled mode (READ_MODE =1), assuming a data float period of 2 cycles (TDF_CYCLES = 2). Figure 25-18 shows the read operation when controlled by NCS (READ_MODE = 0) and the TDF_CYCLES parameter equals 3. Figure 25-17. TDF Period in NRD Controlled Read Access (TDF = 2) MCK A[23:2] NBS0, NBS1, A0, A1 NRD NCS tpacc D[15:0] TDF = 2 clock cycles NRD controlled read operation Figure 25-18.
25.13.2 TDF Optimization Enabled (TDF_MODE = 1) When the TDF_MODE of the SMC_MODE register is set to 1 (TDF optimization is enabled), the SMC takes advantage of the setup period of the next access to optimize the number of wait states cycle to insert. Figure 25-19 shows a read access controlled by NRD, followed by a write access controlled by NWE, on Chip Select 0.
Figure 25-20. TDF Optimization Disabled (TDF Mode = 0). TDF wait states between 2 read accesses on different chip selects MCK A[23:2] NBS0, NBS1, A0, A1 read1 controlling signal (NRD) read1 hold = 1 read2 controlling signal (NRD) read2 setup = 1 TDF_CYCLES = 6 D[15:0] 5 TDF WAIT STATES read 2 cycle TDF_MODE = 0 (optimization disabled) read1 cycle TDF_CYCLES = 6 Chip Select Wait State Figure 25-21.
Figure 25-22. TDF Mode = 0: TDF wait states between read and write accesses on the same chip select MCK A[23:2] NBS0, NBS1, A0, A1 read1 controlling signal (NRD) write2 setup = 1 read1 hold = 1 write2 controlling signal (NWE) TDF_CYCLES = 5 D[15:0] 4 TDF WAIT STATES read1 cycle TDF_CYCLES = 5 Read to Write Wait State write2 cycle TDF_MODE = 0 (optimization disabled) 25.14 External Wait Any access can be extended by an external device using the NWAIT input signal of the SMC.
Figure 25-23.
Figure 25-24.
25.14.3 Ready Mode In Ready mode (EXNW_MODE = 11), the SMC behaves differently. Normally, the SMC begins the access by down counting the setup and pulse counters of the read/write controlling signal. In the last cycle of the pulse phase, the resynchronized NWAIT signal is examined. If asserted, the SMC suspends the access as shown in Figure 25-25 and Figure 25-26. After deassertion, the access is completed: the hold step of the access is performed.
Figure 25-26.
25.14.4 NWAIT Latency and Read/Write Timings There may be a latency between the assertion of the read/write controlling signal and the assertion of the NWAIT signal by the device. The programmed pulse length of the read/write controlling signal must be at least equal to this latency plus the 2 cycles of resynchronization + 1 cycle. Otherwise, the SMC may enter the hold state of the access without detecting the NWAIT signal assertion. This is true in frozen mode as well as in ready mode.
25.15 Slow Clock Mode The SMC is able to automatically apply a set of “slow clock mode” read/write waveforms when an internal signal driven by the Power Management Controller is asserted because MCK has been turned to a very slow clock rate (typically 32 kHz clock rate). In this mode, the user-programmed waveforms are ignored and the slow clock mode waveforms are applied. This mode is provided so as to avoid reprogramming the User Interface with appropriate waveforms at very slow clock rate.
Figure 25-29. Clock Rate Transition Occurs while the SMC is Performing a Write Operation Slow Clock Mode internal signal from PMC MCK A[23:2] NBS0, NBS1, A0, A1 NWE 1 1 1 1 1 1 3 2 2 NCS NWE_CYCLE = 3 NWE_CYCLE = 7 SLOW CLOCK MODE WRITE SLOW CLOCK MODE WRITE This write cycle finishes with the slow clock mode set of parameters after the clock rate transition NORMAL MODE WRITE Slow clock mode transition is detected: Reload Configuration Wait State Figure 25-30.
25.16 NAND Flash Controller Operations 25.16.1 NFC Overview The NFC can handle automatic transfers, sending the commands and address to the NAND Flash and transferring the contents of the page (for read and write) to the NFC SRAM. It minimizes the CPU overhead. 25.16.2 NFC Control Registers NAND Flash Read and NAND Flash Program operations can be performed through the NFC Command Registers. In order to minimize CPU intervention and latency, commands are posted in a command buffer.
25.16.2.1 Building NFC Address Command Example. The base address is made of address 0x60000000 + NFCCMD bit set = 0x68000000. Page read operation example: // Build the Address Command (NFCADDR_CMD) AddressCommand = (0x60000000 | NFCCMD=1 | // NFC Command Enable NFCWR=0 |// NFC Read Data from NAND Flash NFCEN=1 | // NFC Enable. CSID=1 | // Chip Select ID = 1 ACYCLE= 5 | // Number of address cycle.
25.16.2.2 NFC Address Command Name: NFCADDR_CMD Access: Read-write Reset: 0x00000000 31 – 23 30 – 29 – 28 – 27 NFCCMD 26 NFCWR 25 NFCEN 22 21 20 ACYCLE 19 18 VCMD2 17 12 11 10 9 CSID 15 14 13 6 5 16 CMD2 CMD2 7 24 CSID 8 CMD1 4 3 2 CMD1 1 – 0 – • CMD1: Command Register Value for Cycle 1 If NFCCMD is set, when a read or write access occurs, the NFC sends this command.
25.16.2.
25.16.2.4 NFC DATA Status Name: NFCDATA_Status Access: Read Reset: 0x00000000 31 – 23 30 – 29 – 28 – 27 NFCBUSY 26 NFCWR 25 NFCEN 22 21 20 ACYCLE 19 18 VCMD2 17 12 11 10 9 CSID 15 14 13 6 5 16 CMD2 CMD2 7 24 CSID 8 CMD1 4 3 CMD1 2 1 – 0 – • CMD1: Command Register Value for Cycle 1 When a Read or Write Access occurs, the Physical Memory Interface drives the IO bus with CMD1 field during the Command Latch cycle 1.
25.16.3 NFC Initialization Prior to any Command and Data Transfer, the SMC User Interface must be configured to meet the device timing requirements. Write enable Configuration Use NWE_SETUP, NWE_PULSE and NWE_CYCLE to define the write enable waveform according to datasheet of the device. Use TADL field in the SMC_TIMINGS register to configure the timing between the last address latch cycle and the first rising edge of WEN for data input. Figure 25-32.
Figure 25-34. Read Enable Timing Configuration Working with NAND Flash Device mck cen ale cle ren tCLR tAR tREN_SETUP tREN_PULSE tREH tREN_CYCLE Ready/Busy Signal Timing configuration working with a NAND Flash device Use TWB field in SMC_TIMINGS register to configure the maximum elapsed time between the rising edge of wen signal and the falling edge of rbn signal.
25.16.3.1 NAND Flash Controller Timing Engine When the NFC Command register is written, the NFC issues a NAND Flash Command and optionally performs a data transfer between the NFC SRAM and the NAND Flash device. The NAND Flash Controller Timing Engine guarantees valid NAND Flash timings, depending on the set of parameters decoded from the address bus. These timings are defined in the SMC_TIMINGS register. For information of the timing used depending on the command, see Figure 25-36: Figure 25-36.
25.16.4 NFC SRAM 25.16.4.1 NFC SRAM Mapping If the NFC is used to read and write Data from and to the NAND Flash, the configuration depends on the page size. See Table 25-9and Table 25-10 for detailed mapping. The NFC SRAM size is 4 Kbytes. The NFC can handle NAND Flash with a page size of 4 Kbytes or of course lower size (such as 2 Kbytes for example). In the case of 2 Kbytes or lower page size, the NFC SRAM can be split into several banks. The SMC_BANK field enables to select the bank used.
Table 25-10. NFC SRAM Mapping with NAND Flash Page Size of 4 Kbytes + 128 bytes Offset Use Access 0x00001030-0x0000103F Bank 0 Spare Area 3 Read-write 0x00001040-0x0000104F Bank 0 Spare Area 4 Read-write 0x00001050-0x0000105F Bank 0 Spare Area 5 Read-write 0x00001060-0x0000106F Bank 0 Spare Area 6 Read-write 0x00001070-0x0000107F Bank 0 Spare Area 7 Read-write 0x00001080-0x00001FFF Reserved – 25.16.4.
25.16.5.1 Page Read Figure 25-37. Page Read Flow Chart Configure Device, writing in theUser Interface Using NFC Write the NFC Command registers Enable XFRDONE interrupt (SMC_IER) Wait for Interrupt Copy the data from NFC SRAM to application memory (via DMA for example) Check Error Correcting Codes Note that instead of using the interrupt one can poll the NFCBUSY Flag. For more information on the NFC Control Register, see Section 25.16.2.2 ”NFC Address Command”.
25.16.5.2 Program Page Figure 25-38. Program Page Flow Chart Configure Device, writing in the User interface Write Data in the NFC SRAM (CPU or DMA) Enable XFRDONE Write the Command Register through the AHB interface Wait for interrupt Write ECC Wait for Ready/Busy interrupt Writing the ECC can not be done using the NFC so it needs to be done “manually”. Note that instead of using the interrupt one can poll the NFCBUSY Flag. For more information on the NFC Control Register, see Section 25.16.2.
Page size is configured setting the PAGESIZE field in the ECC Mode Register (ECC_MR). Type of correction is configured setting the TYPCORRECT field in the ECC Mode Register (ECC_MR). Note that there is a limitation when using 16-bit NAND Flash: only 1 ECC for all of page is possible. For 8-bit NAND Flash there is no limitation. ECC is automatically computed as soon as a read (00h)/write (80h) command to the NAND Flash or the SmartMedia is detected. Read and write access must start at a page boundary.
Figure 25-39.
Figure 25-40. Parity Generation for 512/1024/2048/4096 16-bit Words 1st word 2nd word 3rd word 4th word (Page size -3 )th word (Page size -2 )th word (Page size -1 )th word Page size th word (+) To calculate P8’ to PX’ and P8 to PX, apply the algorithm that follows.
25.18 Static Memory Controller (SMC) User Interface The SMC is programmed using the fields listed in Table 25-11. For each chip select a set of 4 registers is used to program the parameters of the external device. In Table 25-11, “CS_number” denotes chip select number. 16 bytes per chip select are required. Table 25-11.
Table 25-11.
25.18.1 SMC NFC Configuration Register Name: SMC_CFG Address: 0x400E0000 Access: Read-write Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 21 DTOMUL 20 19 18 17 16 15 – 14 – 13 RBEDGE 12 EDGECTRL 11 – 10 – 9 RSPARE 8 WSPARE 7 – 6 – 5 – 4 – 3 – 2 – 1 0 DTOCYC PAGESIZE • PAGESIZE This field defines the page size of the NAND Flash device.
• DTOMUL: Data Timeout Multiplier These fields determine the maximum number of Master Clock cycles that the SMC waits until the detection of a rising edge on Ready/Busy signal.
25.18.
25.18.3 SMC NFC Status Register Name: SMC_SR Address: 0x400E0008 Access: Read-only Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 RB_EDGE0 23 NFCASE 22 AWB 21 UNDEF 20 DTOE 19 – 18 – 17 CMDDONE 16 XFRDONE 15 – 14 13 NFCSID 12 11 NFCWR 10 – 9 – 8 NFCBUSY 7 – 6 – 5 RB_FALL 4 RB_RISE 3 – 2 – 1 – 0 SMCSTS • SMCSTS: NAND Flash Controller status (this field cannot be reset) 0: NAND Flash Controller is disabled. 1: NAND Flash Controller is enabled.
• DTOE: Data Timeout Error When set to one this flag indicates that the Data timeout set be by DTOMUL and DTOCYC has been exceeded. This flag is reset after a status read operation. • UNDEF: Undefined Area Error When set to one this flag indicates that the processor performed an access in an undefined memory area. This flag is reset after a status read operation. • AWB: Accessing While Busy If set to one this flag indicates that an AHB master has performed an access during the busy phase.
25.18.
25.18.
25.18.
25.18.7 SMC NFC Address Cycle Zero Register Name: SMC_ADDR Address: 0x400E0018 Access: Reset: Read-Write 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 ADDR_CYCLE0 2 1 0 • ADDR_CYCLE0: NAND Flash Array Address cycle 0 When 5 address cycles are used, ADDR_CYCLE0 is the first byte written to NAND Flash (used by the NFC).
25.18.
25.18.
25.18.10 SMC ECC MODE Register Name: SMC_ECC_MD Address: 0x400E0024 Access: Read-write Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 4 3 – 2 – 1 0 ECC_PAGESIZE TYPCORREC • ECC_PAGESIZE This field defines the page size of the NAND Flash device.
25.18.11 SMC ECC Status Register 1 Name: SMC_ECC_SR1 Address: 0x400E0028 Access: Read-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 ECCERR7 22 ECCERR5 14 MULERR3 6 MULERR1 29 ECCERR7 21 ECCERR5 13 ECCERR3 5 ECCERR1 28 RECERR7 20 RECERR5 12 RECERR3 4 RECERR1 27 – 19 – 11 – 3 – 26 ECCERR6 18 ECCERR4 10 MULERR2 2 ECCERR0 25 ECCERR6 17 ECCERR4 9 ECCERR2 1 ECCERR0 24 RECERR6 16 RECERR4 8 RECERR2 0 RECERR0 • RECERR0: Recoverable Error 0: No Errors Detected. 1: Errors Detected.
• MULERR1: Multiple Error in the page between the 256th and the 511th bytes or between the 512nd and the 1023rd bytes Fixed to 0 if TYPECORREC = 0. 0: No Multiple Errors Detected. 1: Multiple Errors Detected. • RECERR2: Recoverable Error in the page between the 512nd and the 767th bytes or between the 1024th and the 1535th bytes Fixed to 0 if TYPECORREC = 0. 0: No Errors Detected. 1: Errors Detected. If MUL_ERROR is 0, a single correctable error was detected.
• RECERR4: Recoverable Error in the page between the 1024th and the 1279th bytes or between the 2048th and the 2559th bytes Fixed to 0 if TYPECORREC = 0. 0: No Errors Detected. 1: Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise multiple uncorrected errors were detected. • ECCERR4: ECC Error in the page between the 1024th and the 1279th bytes or between the 2048th and the 2559th bytes Fixed to 0 if TYPECORREC = 0. 0: No Errors Detected.
• RECERR6: Recoverable Error in the page between the 1536th and the 1791st bytes or between the 3072nd and the 3583rd bytes Fixed to 0 if TYPECORREC = 0. 0: No Errors Detected. 1: Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise multiple uncorrected errors were detected. • ECCERR6: ECC Error in the page between the 1536th and the 1791st bytes or between the 3072nd and the 3583rd bytes Fixed to 0 if TYPECORREC = 0. 0: No Errors Detected.
25.18.
• MULERR9: Multiple Error in the page between the 2304th and the 2559th bytes Fixed to 0 if TYPECORREC = 0. 0: No Multiple Errors Detected. 1: Multiple Errors Detected. • RECERR10: Recoverable Error in the page between the 2560th and the 2815th bytes Fixed to 0 if TYPECORREC = 0. 0: No Errors Detected. 1: Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise, multiple uncorrected errors were detected.
• ECCERR12: ECC Error in the page between the 3072nd and the 3327th bytes Fixed to 0 if TYPECORREC = 0 0: No Errors Detected 1: A single bit error occurred in the ECC bytes. Read ECC Parity 12 register, the error occurred at the location which contains a 1 in the least significant 24 bits. • MULERR12: Multiple Error in the page between the 3072nd and the 3327th bytes Fixed to 0 if TYPECORREC = 0. 0: No Multiple Errors Detected. 1: Multiple Errors Detected.
• RECERR15: Recoverable Error in the page between the 3840th and the 4095th bytes Fixed to 0 if TYPECORREC = 0. 0: No Errors Detected. 1: Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise, multiple uncorrected errors were detected. • ECCERR15: ECC Error in the page between the 3840th and the 4095th bytes Fixed to 0 if TYPECORREC = 0. 0: No Errors Detected. 1: A single bit error occurred in the ECC bytes.
25.18.13 SMC ECC Parity Register 0 for a Page of 512/1024/2048/4096 Bytes Name: SMC_ECC_PR0 Address: 0x400E002C Access: Read-only Reset: 0x00000000 31 – 23 – 15 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 7 6 5 4 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 3 2 1 0 WORDADDR WORDADDR BITADDR Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
25.18.
25.18.15 SMC ECC Parity Registers for 1 ECC per 512 Bytes for a Page of 512/2048/4096 Bytes, 9-bit Word Name: SMC_ECC_PRx [x=0..7] (W9BIT) Address: 0x400E0038 [2] ..
25.18.16 SMC ECC Parity Registers for 1 ECC per 256 Bytes for a Page of 512/2048/4096 Bytes, 8-bit Word Name: SMC_ECC_PRx [x=0..15] (W8BIT) Address: 0x400E0038 [2] ..
25.18.17 SMC Setup Register Name: SMC_SETUPx [x=0..
25.18.18 SMC Pulse Register Name: SMC_PULSEx [x=0..
25.18.19 SMC Cycle Register Name: SMC_CYCLEx [x=0..
25.18.20 SMC Timings Register Name: SMC_TIMINGSx [x=0..7] Address: 0x400E007C [0], 0x400E0090 [1], 0x400E00A4 [2], 0x400E00B8 [3], 0x400E00CC [4], 0x400E00E0 [5], 0x400E00F4 [6], 0x400E0108 [7] Access: Read-write Reset: 0x00000000 31 NFSEL 30 29 RBNSEL 28 23 – 27 22 – 21 – 20 – 19 15 – 14 – 13 – 12 OCMS 11 7 6 5 4 3 26 18 10 2 Command Latch Enable falling edge to Read Enable falling edge timing.
• NFSEL: NAND Flash Selection If this bit is set to one, the chip select is assigned to NAND Flash write enable and read enable lines drive the Error Correcting Code module.
25.18.21 SMC Mode Register Name: SMC_MODEx [x=0..
• BAT: Byte Access Type This field is used only if DBW defines a 16-bit data bus. • 1: Byte write access type: – Write operation is controlled using NCS, NWR0, NWR1. – Read operation is controlled using NCS and NRD. • 0: Byte select access type: – Write operation is controlled using NCS, NWE, NBS0, NBS1. – Read operation is controlled using NCS, NRD, NBS0, NBS1.
25.18.22 SMC OCMS Register Name: SMC_OCMS Address: 0x400E0110 Access: Read-write Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 SRSE 0 SMSE • SMSE: Static Memory Controller Scrambling Enable 0: Disable “Off Chip” Scrambling for SMC access. 1: Enable “Off Chip” Scrambling for SMC access. (If OCMS field is set to 1 in the relevant SMC_TIMINGS register.
25.18.23 SMC OCMS Key1 Register Name: SMC_KEY1 Address: 0x400E0114 Access: Write Once Reset: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 KEY1 23 22 21 20 KEY1 15 14 13 12 KEY1 7 6 5 4 KEY1 • KEY1: Off Chip Memory Scrambling (OCMS) Key Part 1 When Off Chip Memory Scrambling is enabled by setting the SMC_OMCS and SMC_TIMINGS registers in accordance, the data scrambling depends on KEY1 and KEY2 values.
25.18.24 SMC OCMS Key2 Register Name: SMC_KEY2 Address: 0x400E0118 Access: Write Once Reset: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 KEY2 23 22 21 20 KEY2 15 14 13 12 KEY2 7 6 5 4 KEY2 • KEY2: Off Chip Memory Scrambling (OCMS) Key Part 2 When Off Chip Memory Scrambling is enabled by setting the SMC_OMCS and SMC_TIMINGS registers in accordance, the data scrambling depends on KEY2 and KEY1 values.
25.18.25 SMC Write Protection Control Name: SMC_WPCR Address: 0x400E01E4 Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 WP_EN WP_KEY 23 22 21 20 WP_KEY 15 14 13 12 WP_KEY 7 6 5 4 • WP_EN: Write Protection Enable 0: Disables the Write Protection if WP_KEY corresponds. 1: Enables the Write Protection if WP_KEY corresponds. • WP_KEY: Write Protection KEY password Should be written at value 0x534D43 (ASCII code for “SMC”).
25.18.26 SMC Write Protection Status Name: SMC_WPSR Address: 0x400E01E8 Access: Read-only 31 - 30 - 29 - 28 - 23 22 21 20 27 - 26 - 25 - 24 - 19 18 17 16 11 10 9 8 3 2 1 0 WP_VSRC 15 14 13 12 WP_VSRC 7 - 6 - 5 - 4 - WP_VS • WP_VS: Write Protection Violation Status 0: No Write Protect Violation has occurred since the last read of the SMC_WPSR register. 1: A Write Protect Violation has occurred since the last read of the SMC_WPSR register.
26. Peripheral DMA Controller (PDC) 26.1 Description The Peripheral DMA Controller (PDC) transfers data between on-chip serial peripherals and the on- and/or off-chip memories. The link between the PDC and a serial peripheral is operated by the AHB to APB bridge. The user interface of each PDC channel is integrated into the user interface of the peripheral it serves.
The Peripheral DMA Controller handles transfer requests from the channel according to the following priorities (Low to High priorities): Table 26-1.
26.3 Block Diagram Figure 26-1.
26.4 Functional Description 26.4.1 Configuration The PDC channel user interface enables the user to configure and control data transfers for each channel. The user interface of each PDC channel is integrated into the associated peripheral user interface. The user interface of a serial peripheral, whether it is full or half duplex, contains four 32-bit pointers (RPR, RNPR, TPR, TNPR) and four 16-bit counter registers (RCR, RNCR, TCR, TNCR).
These status flags are described in the Peripheral Status Register. 26.4.4 Data Transfers The serial peripheral triggers its associated PDC channels’ transfers using transmit enable (TXEN) and receive enable (RXEN) flags in the transfer control register integrated in the peripheral’s user interface. When the peripheral receives an external data, it sends a Receive Ready signal to its PDC receive channel which then requests access to the Matrix.
26.5 Peripheral DMA Controller (PDC) User Interface Table 26-2.
26.5.1 Receive Pointer Register Name: PERIPH_RPR Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RXPTR 23 22 21 20 RXPTR 15 14 13 12 RXPTR 7 6 5 4 RXPTR • RXPTR: Receive Pointer Register RXPTR must be set to receive buffer address. When a half duplex peripheral is connected to the PDC, RXPTR = TXPTR.
26.5.2 Receive Counter Register Name: PERIPH_RCR Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 RXCTR 7 6 5 4 RXCTR • RXCTR: Receive Counter Register RXCTR must be set to receive buffer size. When a half duplex peripheral is connected to the PDC, RXCTR = TXCTR.
26.5.3 Transmit Pointer Register Name: PERIPH_TPR Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TXPTR 23 22 21 20 TXPTR 15 14 13 12 TXPTR 7 6 5 4 TXPTR • TXPTR: Transmit Counter Register TXPTR must be set to transmit buffer address. When a half duplex peripheral is connected to the PDC, RXPTR = TXPTR.
26.5.4 Transmit Counter Register Name: PERIPH_TCR Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 TXCTR 7 6 5 4 TXCTR • TXCTR: Transmit Counter Register TXCTR must be set to transmit buffer size. When a half duplex peripheral is connected to the PDC, RXCTR = TXCTR.
26.5.5 Receive Next Pointer Register Name: PERIPH_RNPR Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RXNPTR 23 22 21 20 RXNPTR 15 14 13 12 RXNPTR 7 6 5 4 RXNPTR • RXNPTR: Receive Next Pointer RXNPTR contains next receive buffer address. When a half duplex peripheral is connected to the PDC, RXNPTR = TXNPTR.
26.5.6 Receive Next Counter Register Name: PERIPH_RNCR Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 RXNCTR 7 6 5 4 RXNCTR • RXNCTR: Receive Next Counter RXNCTR contains next receive buffer size. When a half duplex peripheral is connected to the PDC, RXNCTR = TXNCTR.
26.5.7 Transmit Next Pointer Register Name: PERIPH_TNPR Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TXNPTR 23 22 21 20 TXNPTR 15 14 13 12 TXNPTR 7 6 5 4 TXNPTR • TXNPTR: Transmit Next Pointer TXNPTR contains next transmit buffer address. When a half duplex peripheral is connected to the PDC, RXNPTR = TXNPTR.
26.5.8 Transmit Next Counter Register Name: PERIPH_TNCR Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 TXNCTR 7 6 5 4 TXNCTR • TXNCTR: Transmit Counter Next TXNCTR contains next transmit buffer size. When a half duplex peripheral is connected to the PDC, RXNCTR = TXNCTR.
26.5.9 Transfer Control Register Name: PERIPH_PTCR Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 TXTDIS 8 TXTEN 7 – 6 – 5 – 4 – 3 – 2 – 1 RXTDIS 0 RXTEN • RXTEN: Receiver Transfer Enable 0: No effect. 1: Enables PDC receiver channel requests if RXTDIS is not set.
26.5.10 Transfer Status Register Name: PERIPH_PTSR Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 TXTEN 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 RXTEN • RXTEN: Receiver Transfer Enable 0: PDC Receiver channel requests are disabled. 1: PDC Receiver channel requests are enabled. • TXTEN: Transmitter Transfer Enable 0: PDC Transmitter channel requests are disabled.
27. Clock Generator 27.1 Description The Clock Generator User Interface is embedded within the Power Management Controller and is described in Section 28.15 ”Power Management Controller (PMC) User Interface”. However, the Clock Generator registers are named CKGR_. 27.2 Embedded Characteristics The Clock Generator is made up of: A Low Power 32,768 Hz Slow Clock Oscillator with bypass mode.
27.3 Block Diagram Figure 27-1. Clock Generator Block Diagram Clock Generator XTALSEL (Supply Controller) Embedded 32 kHz RC Oscillator 0 Slow Clock SLCK XIN32 XOUT32 32768 Hz Crystal Oscillator 1 MOSCSEL Embedded 12/8/4 MHz Fast RC Oscillator 0 Main Clock MAINCK XIN XOUT 3-20 MHz Crystal Oscillator Status 1 PLLA and Divider PLLA Clock PLLACK USB UTMI PLL UPLL Clock UPLLCK Control Power Management Controller 27.
27.4.1 Slow Clock RC Oscillator By default, the Slow Clock RC Oscillator is enabled and selected. The user has to take into account the possible drifts of the RC Oscillator. More details are given in the section “DC Characteristics” of the product datasheet. It can be disabled via the XTALSEL bit in the Supply Controller Control Register (SUPC_CR). 27.4.2 Slow Clock Crystal Oscillator The Clock Generator integrates a 32,768 Hz low-power oscillator.
27.5 Main Clock Figure 27-3 shows the Main Clock block diagram. Figure 27-3. Main Clock Block Diagram MOSCRCEN MOSCRCF MOSCRCS 4/8/12 MHz Fast RC Oscillator MOSCSEL MOSCSELS 0 MAINCK Main Clock MOSCXTEN 3-20 MHz Crystal or Ceramic Resonator Oscillator XIN XOUT 1 MOSCXTCNT 3-20 MHz Oscillator Counter SLCK Slow Clock MOSCXTS MOSCRCEN MOSCXTEN MOSCSEL MAINCK Main Clock Ref. Main Clock Frequency Counter MAINF MAINRDY The Main Clock has two sources: 27.5.
When disabling the Main Clock by clearing the MOSCRCEN bit in CKGR_MOR, the MOSCRCS bit in the Power Management Controller Status Register (PMC_SR) is automatically cleared, indicating the Main Clock is off. Setting the MOSCRCS bit in the Power Management Controller Interrupt Enable Register (PMC_IER) can trigger an interrupt to the processor. It is recommended to disable the Main Clock as soon as the processor no longer uses it and runs out of SLCK, PLLACKor UPLLCK.
27.5.4 Main Clock Frequency Counter The device features a Main Clock frequency counter that provides the frequency of the Main Clock. The Main Clock frequency counter is reset and starts incrementing at the Main Clock speed after the next rising edge of the Slow Clock in the following cases: when the 4/8/12 MHz Fast RC oscillator clock is selected as the source of Main Clock and when this oscillator becomes stable (i.e.
At this time, the LOCK bit is set in PMC_SR and can trigger an interrupt to the processor. The user has to load the number of Slow Clock cycles required to cover the PLL transient time into the PLLCOUNT field. The PLL clock can be divided by 2 by writing the PLLDIV2 (PLLADIV2) bit in PMC Master Clock Register (PMC_MCKR). It is forbidden to change 4/8/12 MHz Fast RC oscillator, or main selection in CKGR_MOR register while Master clock source is PLL and PLL reference clock is the Fast RC oscillator.
28. Power Management Controller (PMC) 28.1 Description The Power Management Controller (PMC) optimizes power consumption by controlling all system and user peripheral clocks. The PMC enables/disables the clock inputs to many of the peripherals and the Cortex-M3 Processor. The Supply Controller selects between the 32 kHz RC oscillator or the crystal oscillator. The unused oscillator is disabled automatically so that power consumption is optimized.
28.3 Block Diagram Figure 28-1.
28.4 Master Clock Controller The Master Clock Controller provides selection and division of the Master Clock (MCK). MCK is the clock provided to all the peripherals. The Master Clock is selected from one of the clocks provided by the Clock Generator. Selecting the Slow Clock provides a Slow Clock signal to the whole device. Selecting the Main Clock saves power consumption of the PLLs. The Master Clock Controller is made up of a clock selector and a prescaler.
Disable 1 (PMC_PCDR1) registers. The status of the peripheral clock activity can be read in the Peripheral Clock Status Register (PMC_PCSR0) and Peripheral Clock Status Register (PMC_PCSR1). When a peripheral clock is disabled, the clock is immediately stopped. The peripheral clocks are automatically disabled after a reset. In order to stop a peripheral, it is recommended that the system software wait until the peripheral has executed its last programmed operation before disabling the clock.
Moreover, like the PCK, a status bit in PMC_SR indicates that the Programmable Clock is actually what has been programmed in the Programmable Clock registers. As the Programmable Clock Controller does not manage with glitch prevention when switching clocks, it is strongly recommended to disable the Programmable Clock before any configuration change and to re-enable it after the change is actually performed. 28.
The user interface does not provide any status for Fast Startup, but the user can easily recover this information by reading the PIO Controller, and the status registers of the RTC, RTT and USB Controller. 28.11 Main Crystal Clock Failure Detector The clock failure detector monitors the 3 to 20 MHz Crystal or Ceramic Resonator-based oscillator to identify an eventual defect of this oscillator (for example, if the crystal is unconnected).
In some situations the user may need an accurate measure of the main clock frequency. This measure can be accomplished via the Main Clock Frequency Register (CKGR_MCFR). Once the MAINFRDY field is set in CKGR_MCFR, the user may read the MAINF field in CKGR_MCFR. This provides the number of main clock cycles within sixteen slow clock cycles. 3. Setting PLL and Divider: All parameters needed to configure PLLA and the divider are located in CKGR_PLLAR. The DIV field is used to control the divider itself.
Note: IF PLLx clock was selected as the Master Clock and the user decides to modify it by writing in CKGR_PLLR, the MCKRDY flag will go low while PLL is unlocked. Once PLL is locked again, LOCK goes high and MCKRDY is set. While PLL is unlocked, the Master Clock selection is automatically changed to Slow Clock. For further information, see Section 28.13.0.2 “Clock Switching Waveforms” on page 535.
28.13 Clock Switching Details 28.13.0.1Master Clock Switching Timings Table 28-1 and Table 28-2 give the worst case timings required for the Master Clock to switch from one selected clock to another one. This is in the event that the prescaler is de-activated. When the prescaler is activated, an additional time of 64 clock cycles of the newly selected clock has to be added. Table 28-1. Clock Switching Timings (Worst Case) From Main Clock SLCK PLL Clock – 4 x SLCK + 2.5 x Main Clock 0.
28.13.0.2Clock Switching Waveforms Figure 28-5. Switch Master Clock from Slow Clock to PLLx Clock Slow Clock PLLx Clock LOCK MCKRDY Master Clock Write PMC_MCKR Figure 28-6.
Figure 28-7. Change PLLx Programming Slow Clock PLLx Clock LOCKx MCKRDY Master Clock Slow Clock Write CKGR_PLLxR Figure 28-8.
28.14 Write Protection Registers To prevent any single software error that may corrupt PMC behavior, certain address spaces can be write protected by setting the WPEN bit in the “PMC Write Protect Mode Register” (PMC_WPMR). If a write access to the protected registers is detected, then the WPVS flag in the PMC Write Protect Status Register (PMC_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted.
28.15 Power Management Controller (PMC) User Interface Table 28-3.
28.15.1 PMC System Clock Enable Register Name: PMC_SCER Address: 0x400E0600 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – PCK2 PCK1 PCK0 7 6 5 4 3 2 1 0 – – UOTGCLK – – – – – This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” .
28.15.2 PMC System Clock Disable Register Name: PMC_SCDR Address: 0x400E0604 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – PCK2 PCK1 PCK0 7 6 5 4 3 2 1 0 – – UOTGCLK – – – – – This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” .
28.15.3 PMC System Clock Status Register Name: PMC_SCSR Address: 0x400E0608 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – PCK2 PCK1 PCK0 7 6 5 4 3 2 1 0 – – UOTGCLK – – – – – • UOTGCLK: USB OTG Clock (48 MHz, USB_48M) Clock Status 0 = The 48 MHz clock (UOTGCK) of the USB OTG FS Port is disabled.
28.15.
28.15.
28.15.
28.15.7 PMC UTMI Clock Configuration Register Name: CKGR_UCKR Address: 0x400E061C Access: Read-write 31 – 30 – 29 – 28 27 – 26 – 25 – 24 – 23 22 21 20 19 – 18 – 17 – 16 UPLLEN UPLLCOUNT 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – This register can only be written if the WPEN bit is cleared in the “PMC Write Protect Mode Register” . • UPLLEN: UTMI PLL Enable 0: The UTMI PLL is disabled. 1: The UTMI PLL is enabled.
28.15.8 PMC Clock Generator Main Oscillator Register Name: CKGR_MOR Address: 0x400E0620 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 CFDEN 24 MOSCSEL 23 22 21 20 19 18 17 16 11 10 9 8 3 MOSCRCEN 2 – 1 MOSCXTBY 0 MOSCXTEN KEY 15 14 13 12 MOSCXTST 7 – 6 5 MOSCRCF 4 This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” . • KEY: Password Should be written at value 0x37.
• MOSCXTST: Main Crystal Oscillator Start-up Time Specifies the number of Slow Clock cycles multiplied by 8 for the Main Crystal Oscillator start-up time. • MOSCSEL: Main Oscillator Selection 0 = The Main On-Chip RC Oscillator is selected. 1 = The Main Crystal Oscillator is selected. • CFDEN: Clock Failure Detector Enable 0 = The Clock Failure Detector is disabled. 1 = The Clock Failure Detector is enabled.
28.15.9 PMC Clock Generator Main Clock Frequency Register Name: CKGR_MCFR Address: 0x400E0624 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 MAINFRDY 15 14 13 12 11 10 9 8 3 2 1 0 MAINF 7 6 5 4 MAINF This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” . • MAINF: Main Clock Frequency Gives the number of Main Clock cycles within 16 Slow Clock periods.
28.15.10 PMC Clock Generator PLLA Register Name: CKGR_PLLAR Address: 0x400E0628 Access: Read-write 31 – 30 – 29 ONE 28 – 27 – 26 25 MULA 24 23 22 21 20 19 18 17 16 10 9 8 2 1 0 MULA 15 – 14 – 13 7 6 5 12 11 PLLACOUNT 4 3 DIVA Possible limitations on PLLA input frequencies and multiplier factors should be checked before using the PMC. Warning: Bit 29 must always be set to 1 when programming the CKGR_PLLAR register.
28.15.11 PMC Master Clock Register Name: PMC_MCKR Address: 0x400E0630 Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – UPLLDIV2 PLLADIV2 – – – – 7 6 5 4 3 2 1 – – – PRES This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” .
28.15.12 PMC USB Clock Register Name: PMC_USB Address: 0x400E0638 Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – USBDIV 7 6 5 4 3 2 1 0 – – – – – – – USBS This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” . • USBS: USB Input Clock Selection 0 = USB Clock Input is PLLA. 1 = USB Clock Input is PLLB.
28.15.13 PMC Programmable Clock Register Name: PMC_PCKx Address: 0x400E0640 Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – PRES – CSS This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” .
28.15.
28.15.
28.15.16 PMC Status Register Name: PMC_SR Address: 0x400E0668 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – FOS CFDS CFDEV MOSCRCS MOSCSELS 15 14 13 12 11 10 9 8 – – – – – PCKRDY2 PCKRDY1 PCKRDY0 7 6 5 4 3 2 1 0 OSCSELS LOCKU– – – MCKRDY – LOCKA MOSCXTS • MOSCXTS: Main XTAL Oscillator Status 0 = Main XTAL oscillator is not stabilized. 1 = Main XTAL oscillator is stabilized.
• CFDEV: Clock Failure Detector Event 0 = No clock failure detection of the main on-chip RC oscillator clock has occurred since the last read of PMC_SR. 1 = At least one clock failure detection of the main on-chip RC oscillator clock has occurred since the last read of PMC_SR. • CFDS: Clock Failure Detector Status 0 = A clock failure of the main on-chip RC oscillator clock is not detected. 1 = A clock failure of the main on-chip RC oscillator clock is detected.
28.15.
28.15.18 PMC Fast Startup Mode Register Name: PMC_FSMR Address: 0x400E0670 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 LPM 19 – 18 USBAL 17 RTCAL 16 RTTAL 15 FSTT15 14 FSTT14 13 FSTT13 12 FSTT12 11 FSTT11 10 FSTT10 9 FSTT9 8 FSTT8 7 FSTT7 6 FSTT6 5 FSTT5 4 FSTT4 3 FSTT3 2 FSTT2 1 FSTT1 0 FSTT0 This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” .
28.15.19 PMC Fast Startup Polarity Register Name: PMC_FSPR Address: 0x400E0674 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 FSTP15 14 FSTP14 13 FSTP13 12 FSTP12 11 FSTP11 10 FSTP10 9 FSTP9 8 FSTP8 7 FSTP7 6 FSTP6 5 FSTP5 4 FSTP4 3 FSTP3 2 FSTP2 1 FSTP1 0 FSTP0 This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” .
28.15.20 PMC Fault Output Clear Register Name: PMC_FOCR Address: 0x400E0678 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 FOCLR • FOCLR: Fault Output Clear Clears the clock failure detector fault output.
28.15.21 PMC Write Protect Mode Register Name: PMC_WPMR Address: 0x400E06E4 Access: Read-write Reset: See Table 28-3 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 – – – – – – – WPEN • WPEN: Write Protect Enable 0 = Disables the Write Protect if WPKEY corresponds to 0x504D43 (“PMC” in ASCII). 1 = Enables the Write Protect if WPKEY corresponds to 0x504D43 (“PMC” in ASCII).
28.15.22 PMC Write Protect Status Register Name: PMC_WPSR Address: 0x400E06E8 Access: Read-only Reset: See Table 28-3 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 11 10 9 8 WPVSRC 15 14 13 12 WPVSRC 7 6 5 4 3 2 1 0 – – – – – – – WPVS • WPVS: Write Protect Violation Status 0 = No Write Protect Violation has occurred since the last read of the PMC_WPSR register.
28.15.23 PMC Peripheral Clock Enable Register 1 Name: PMC_PCER1 Address: 0x400E0700 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – PID44 PID43 PID42 PID41 PID40 7 6 5 4 3 2 1 0 PID39 PID38 PID37 PID36 PID35 PID34 PID33 PID32 This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” .
28.15.24 PMC Peripheral Clock Disable Register 1 Name: PMC_PCDR1 Address: 0x400E0704 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – PID44 PID43 PID42 PID41 PID40 7 6 5 4 3 2 1 0 PID39 PID38 PID37 PID36 PID35 PID34 PID33 PID32 This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” on page 561.
28.15.25 PMC Peripheral Clock Status Register 1 Name: PMC_PCSR1 Address: 0x400E0708 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – PID44 PID43 PID42 PID41 PID40 7 6 5 4 3 2 1 0 PID39 PID38 PID37 PID36 PID35 PID34 PID33 PID32 • PIDx: Peripheral Clock x Status 0 = The corresponding peripheral clock is disabled. 1 = The corresponding peripheral clock is enabled.
28.15.26 PMC Peripheral Control Register Name: PMC_PCR Address: 0x400E070C Access: Read-write 31 30 29 28 27 26 25 24 – – – EN – – – – 23 22 21 20 19 18 17 – – – – – – 15 14 13 12 11 10 9 8 – – – CMD – – – – 7 6 5 4 3 2 1 0 – – 16 DIV PID • PID: Peripheral ID Peripheral ID selection from PID2 to PID63 PID2 to PID63 refer to identifiers as defined in the section “Peripheral Identifiers” in the product datasheet.
29. Chip Identifier (CHIPID) 29.1 Description Chip Identifier registers permit recognition of the device and its revision. These registers provide the sizes and types of the on-chip memories, as well as the set of embedded peripherals. Two chip identifier registers are embedded: CHIPID_CIDR (Chip ID Register) and CHIPID_EXID (Extension ID). Both registers contain a hard-wired value that is read-only.
29.3 Chip Identifier (CHIPID) User Interface Table 29-2.
29.3.1 Chip ID Register Name: CHIPID_CIDR Address: 0x400E0940 Access: Read-only 31 30 29 EXT 28 27 26 NVPTYP 23 22 21 20 19 18 ARCH 15 14 13 6 24 17 16 9 8 1 0 SRAMSIZ 12 11 10 NVPSIZ2 7 25 ARCH NVPSIZ 5 4 EPROC 3 2 VERSION • VERSION: Version of the Device Current version of the device.
Value Name Description 13 Reserved 14 2048K 2048K bytes 15 Reserved • NVPSIZ2 Second Nonvolatile Program Memory Size Value Name Description 0 NONE None 1 8K 8K bytes 2 16K 16K bytes 3 32K 32K bytes 4 Reserved 5 64K 6 64K bytes Reserved 7 128K 8 128K bytes Reserved 9 256K 256K bytes 10 512K 512K bytes 11 Reserved 12 1024K 13 1024K bytes Reserved 14 2048K 15 2048K bytes Reserved • SRAMSIZ: Internal SRAM Size Value 570 Name Description 0 48K 48K bytes 1
Value Name Description 13 256K 256K bytes 14 96K 96K bytes 15 512K 512K bytes • ARCH: Architecture Identifier Value Name Description 0x19 AT91SAM9xx AT91SAM9xx Series 0x29 AT91SAM9XExx AT91SAM9XExx Series 0x34 AT91x34 AT91x34 Series 0x37 CAP7 CAP7 Series 0x39 CAP9 CAP9 Series 0x3B CAP11 CAP11 Series 0x40 AT91x40 AT91x40 Series 0x42 AT91x42 AT91x42 Series 0x55 AT91x55 AT91x55 Series 0x60 AT91SAM7Axx AT91SAM7Axx Series 0x61 AT91SAM7AQxx AT91SAM7AQxx Series 0x63
Value Name Description 0x9A SAM3SDxC SAM3SDxC Series (100-pin version) 0xA5 SAM5A SAM5A 0xF0 AT75Cxx AT75Cxx Series • NVPTYP: Nonvolatile Program Memory Type Value Name Description 0 ROM ROM 1 ROMLESS ROMless or on-chip Flash 4 SRAM SRAM emulating ROM 2 FLASH Embedded Flash Memory ROM and Embedded Flash Memory 3 ROM_FLASH NVPSIZ is ROM size NVPSIZ2 is Flash size • EXT: Extension Flag 0 = Chip ID has a single register definition without extension 1 = An extended Chip ID exists.
29.3.2 Chip ID Extension Register Name: CHIPID_EXID Address: 0x400E0944 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 EXID 23 22 21 20 EXID 15 14 13 12 EXID 7 6 5 4 EXID • EXID: Chip ID Extension Reads 0 if the bit EXT in CHIPID_CIDR is 0.
30. Synchronous Serial Controller (SSC) 30.1 Description The Atmel Synchronous Serial Controller (SSC) provides a synchronous communication link with external devices. It supports many serial synchronous communication protocols generally used in audio and telecom applications such as I2S, Short Frame Sync, Long Frame Sync, etc. The SSC contains an independent receiver and transmitter and a common clock divider.
30.3 Block Diagram Figure 30-1. Block Diagram System Bus APB Bridge DMA Peripheral Bus TF TK PMC TD MCK PIO SSC Interface RF RK Interrupt Control RD SSC Interrupt 30.4 Application Block Diagram Figure 30-2.
30.5 Pin Name List Table 30-1. I/O Lines Description Pin Name Pin Description RF Receiver Frame Synchro Input/Output RK Receiver Clock Input/Output RD Receiver Data Input TF Transmitter Frame Synchro Input/Output TK Transmitter Clock Input/Output TD Transmitter Data Output 30.6 Type Product Dependencies 30.6.1 I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines.
30.7 Functional Description This chapter contains the functional description of the following: SSC Functional Block, Clock Management, Data format, Start, Transmitter, Receiver and Frame Sync. The receiver and transmitter operate separately. However, they can work synchronously by programming the receiver to use the transmit clock and/or to start a data transfer when transmission starts.
The receiver clock can be generated by: an external clock received on the RK I/O pad the transmitter clock the internal clock divider Furthermore, the transmitter block can generate an external clock on the TK I/O pad, and the receiver block can generate an external clock on the RK I/O pad. This allows the SSC to support many Master and Slave Mode data transfers. 30.7.1.1 Clock Divider Figure 30-4.
30.7.1.2 Transmitter Clock Management The transmitter clock is generated from the receiver clock or the divider clock or an external clock scanned on the TK I/O pad. The transmitter clock is selected by the CKS field in SSC_TCMR (Transmit Clock Mode Register). Transmit Clock can be inverted independently by the CKI bits in SSC_TCMR. The transmitter can also drive the TK I/O pad continuously or be limited to the actual data transfer. The clock output is configured by the SSC_TCMR register.
Figure 30-7. Receiver Clock Management RK (pin) Tri-state Controller MUX Clock Output Transmitter Clock Divider Clock Data Transfer CKO CKS INV MUX Tri-state Controller CKI CKG Receiver Clock 30.7.1.4 Serial Clock Ratio Considerations The Transmitter and the Receiver can be programmed to operate with the clock signals provided on either the TK or RK pins. This allows the SSC to support many slave-mode data transfers.
30.7.2 Transmitter Operations A transmitted frame is triggered by a start event and can be followed by synchronization data before data transmission. The start event is configured by setting the Transmit Clock Mode Register (SSC_TCMR). See “Start” on page 582. The frame synchronization is configured setting the Transmit Frame Mode Register (SSC_TFMR). See “Frame Sync” on page 584.
30.7.3 Receiver Operations A received frame is triggered by a start event and can be followed by synchronization data before data transmission. The start event is configured setting the Receive Clock Mode Register (SSC_RCMR). See “Start” on page 582. The frame synchronization is configured setting the Receive Frame Mode Register (SSC_RFMR). See “Frame Sync” on page 584. The receiver uses a shift register clocked by the receiver clock signal and the start mode selected in the SSC_RCMR.
Detection on TF/RF input/output is done by the field FSOS of the Transmit/Receive Frame Mode Register (TFMR/RFMR). Figure 30-10.
30.7.5 Frame Sync The Transmitter and Receiver Frame Sync pins, TF and RF, can be programmed to generate different kinds of frame synchronization signals. The Frame Sync Output Selection (FSOS) field in the Receive Frame Mode Register (SSC_RFMR) and in the Transmit Frame Mode Register (SSC_TFMR) are used to select the required waveform. Programmable low or high levels during data transfer are supported. Programmable high levels before the start of data transfers or toggling are also supported.
Register (SSC_RC0R). When this start event is selected, the user can program the Receiver to start a new data transfer either by writing a new Compare 0, or by receiving continuously until Compare 1 occurs. This selection is done with the bit (STOP) in SSC_RCMR. 30.7.7 Data Format The data framing format of both the transmitter and the receiver are programmable through the Transmitter Frame Mode Register (SSC_TFMR) and the Receiver Frame Mode Register (SSC_RFMR).
Figure 30-13. Transmit and Receive Frame Format in Edge/Pulse Start Modes Start Start PERIOD (1) TF/RF FSLEN TD (If FSDEN = 1) TD (If FSDEN = 0) RD Data Data Default From SSC_TSHR From DATDEF From SSC_THR From SSC_THR From DATDEF Default Data Data Sync Data Default From SSC_THR From DATDEF Ignored Sync Data To SSC_RSHR Default From SSC_THR Data From DATDEF Ignored Data To SSC_RHR To SSC_RHR DATLEN DATLEN STTDLY Sync Data Sync Data DATNB Note: 1.
30.7.8 Loop Mode The receiver can be programmed to receive transmissions from the transmitter. This is done by setting the Loop Mode (LOOP) bit in SSC_RFMR. In this case, RD is connected to TD, RF is connected to TF and RK is connected to TK. 30.7.9 Interrupt Most bits in SSC_SR have a corresponding bit in interrupt management registers. The SSC can be programmed to generate an interrupt when it detects an event.
30.8 SSC Application Examples The SSC can support several serial communication modes used in audio or high speed serial links. Some standard applications are shown in the following figures. All serial link applications supported by the SSC are not listed here. Figure 30-17. Audio Application Block Diagram Clock SCK TK Word Select WS I2S RECEIVER TF Data SD SSC TD RD Clock SCK RF Word Select WS RK MSB Data SD LSB Right Channel Left Channel Figure 30-18.
Figure 30-19.
30.8.1 Write Protection Registers To prevent any single software error that may corrupt SSC behavior, certain address spaces can be writeprotected by setting the WPEN bit in the “SSC Write Protect Mode Register” (SSC_WPMR). If a write access to the protected registers is detected, then the WPVS flag in the SSC Write Protect Status Register (US_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted.
30.9 Synchronous Serial Controller (SSC) User Interface Table 30-6.
30.9.1 SSC Control Register Name: SSC_CR Address: 0x40004000 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 SWRST 14 – 13 – 12 – 11 – 10 – 9 TXDIS 8 TXEN 7 – 6 – 5 – 4 – 3 – 2 – 1 RXDIS 0 RXEN • RXEN: Receive Enable 0 = No effect. 1 = Enables Receive if RXDIS is not set. • RXDIS: Receive Disable 0 = No effect. 1 = Disables Receive.
30.9.2 SSC Clock Mode Register Name: SSC_CMR Address: 0x40004004 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 10 9 8 7 6 5 4 1 0 DIV 3 2 DIV This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register” . • DIV: Clock Divider 0 = The Clock Divider is not active. Any Other Value: The Divided Clock equals the Master Clock divided by 2 times DIV.
30.9.3 SSC Receive Clock Mode Register Name: SSC_RCMR Address: 0x40004010 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 10 9 8 PERIOD 23 22 21 20 STTDLY 15 – 7 14 – 13 – 12 STOP 11 6 5 CKI 4 3 CKO CKG START 2 1 0 CKS This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register” .
• CKG: Receive Clock Gating Selection Value Name Description RK Pin 0 NONE None Input-only 1 CONTINUOUS Continuous Receive Clock Output 2 TRANSFER Receive Clock only during data transfers Output 3-7 Reserved • START: Receive Start Selection Value Name Description 0 CONTINUOUS Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
30.9.4 SSC Receive Frame Mode Register Name: SSC_RFMR Address: 0x40004014 Access: Read-write 31 FSLEN_EXT 30 FSLEN_EXT 29 FSLEN_EXT FSLEN_EXT 23 – 22 15 – 7 MSBF 28 27 – 26 – 25 – 24 FSEDGE 21 FSOS 20 19 18 17 16 14 – 13 – 12 – 11 9 8 6 – 5 LOOP 4 3 1 0 FSLEN 10 DATNB 2 DATLEN This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register” . • DATLEN: Data Length 0 = Forbidden value (1-bit data length not supported).
• FSOS: Receive Frame Sync Output Selection Value Name Description RF Pin 0 NONE None Input-only 1 NEGATIVE Negative Pulse Output 2 POSITIVE Positive Pulse Output 3 LOW Driven Low during data transfer Output 4 HIGH Driven High during data transfer Output 5 TOGGLING Toggling at each start of data transfer Output Reserved Undefined 6-7 • FSEDGE: Frame Sync Edge Detection Determines which edge on Frame Sync will generate the interrupt RXSYN in the SSC Status Register.
30.9.5 SSC Transmit Clock Mode Register Name: SSC_TCMR Address: 0x40004018 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 10 9 8 PERIOD 23 22 21 20 STTDLY 15 – 7 14 – 13 – 12 – 11 6 5 CKI 4 3 CKO CKG START 2 1 0 CKS This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register” .
• CKG: Transmit Clock Gating Selection Value Name Description 0 NONE None 1 CONTINUOUS Transmit Clock enabled only if TF Low 2 TRANSFER Transmit Clock enabled only if TF High • START: Transmit Start Selection Value Name Description 0 CONTINUOUS Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data.
30.9.6 SSC Transmit Frame Mode Register Name: SSC_TFMR Address: 0x4000401C Access: Read-write 31 FSLEN_EXT 30 FSLEN_EXT 29 FSLEN_EXT FSLEN_EXT 23 FSDEN 22 15 – 7 MSBF 28 27 – 26 – 25 – 24 FSEDGE 21 FSOS 20 19 18 17 16 14 – 13 – 12 – 11 9 8 6 – 5 DATDEF 4 3 1 0 FSLEN 10 DATNB 2 DATLEN This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register” . • DATLEN: Data Length 0 = Forbidden value (1-bit data length not supported).
• FSOS: Transmit Frame Sync Output Selection Value Name Description RF Pin 0 NONE None Input-only 1 NEGATIVE Negative Pulse Output 2 POSITIVE Positive Pulse Output 3 LOW Driven Low during data transfer Output 4 HIGH Driven High during data transfer Output 5 TOGGLING Toggling at each start of data transfer Output Reserved Undefined 6-7 • FSDEN: Frame Sync Data Enable 0 = The TD line is driven with the default value during the Transmit Frame Sync signal.
30.9.7 SSC Receive Holding Register Name: SSC_RHR Address: 0x40004020 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RDAT 23 22 21 20 RDAT 15 14 13 12 RDAT 7 6 5 4 RDAT • RDAT: Receive Data Right aligned regardless of the number of data bits defined by DATLEN in SSC_RFMR.
30.9.8 SSC Transmit Holding Register Name: SSC_THR Address: 0x40004024 Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TDAT 23 22 21 20 TDAT 15 14 13 12 TDAT 7 6 5 4 TDAT • TDAT: Transmit Data Right aligned regardless of the number of data bits defined by DATLEN in SSC_TFMR.
30.9.
30.9.
30.9.11 SSC Receive Compare 0 Register Name: SSC_RC0R Address: 0x40004038 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 CP0 7 6 5 4 CP0 This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register” .
30.9.12 SSC Receive Compare 1 Register Name: SSC_RC1R Address: 0x4000403C Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 CP1 7 6 5 4 CP1 This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register” .
30.9.13 SSC Status Register Name: SSC_SR Address: 0x40004040 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 RXEN 16 TXEN 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 – 6 – 5 OVRUN 4 RXRDY 3 – 2 – 1 TXEMPTY 0 TXRDY • TXRDY: Transmit Ready 0 = Data has been loaded in SSC_THR and is waiting to be loaded in the Transmit Shift Register (TSR). 1 = SSC_THR is empty.
• RXSYN: Receive Sync 0 = An Rx Sync has not occurred since the last read of the Status Register. 1 = An Rx Sync has occurred since the last read of the Status Register. • TXEN: Transmit Enable 0 = Transmit is disabled. 1 = Transmit is enabled. • RXEN: Receive Enable 0 = Receive is disabled. 1 = Receive is enabled.
30.9.14 SSC Interrupt Enable Register Name: SSC_IER Address: 0x40004044 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 – 6 – 5 OVRUN 4 RXRDY 3 – 2 – 1 TXEMPTY 0 TXRDY • TXRDY: Transmit Ready Interrupt Enable 0 = 0 = No effect. 1 = Enables the Transmit Ready Interrupt. • TXEMPTY: Transmit Empty Interrupt Enable 0 = No effect. 1 = Enables the Transmit Empty Interrupt.
• RXSYN: Rx Sync Interrupt Enable 0 = No effect. 1 = Enables the Rx Sync Interrupt.
30.9.15 SSC Interrupt Disable Register Name: SSC_IDR Address: 0x40004048 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 – 6 – 5 OVRUN 4 RXRDY 3 – 2 – 1 TXEMPTY 0 TXRDY • TXRDY: Transmit Ready Interrupt Disable 0 = No effect. 1 = Disables the Transmit Ready Interrupt. • TXEMPTY: Transmit Empty Interrupt Disable 0 = No effect. 1 = Disables the Transmit Empty Interrupt.
• RXSYN: Rx Sync Interrupt Enable 0 = No effect. 1 = Disables the Rx Sync Interrupt.
30.9.16 SSC Interrupt Mask Register Name: SSC_IMR Address: 0x4000404C Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 – 6 – 5 OVRUN 4 RXRDY 3 – 2 – 1 TXEMPTY 0 TXRDY • TXRDY: Transmit Ready Interrupt Mask 0 = The Transmit Ready Interrupt is disabled. 1 = The Transmit Ready Interrupt is enabled.
• RXSYN: Rx Sync Interrupt Mask 0 = The Rx Sync Interrupt is disabled. 1 = The Rx Sync Interrupt is enabled.
30.9.17 SSC Write Protect Mode Register Name: SSC_WPMR Address: 0x400040E4 Access: Read-write Reset: See Table 30-6 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 — — — — — — — WPEN • WPEN: Write Protect Enable 0 = Disables the Write Protect if WPKEY corresponds to 0x535343 (“SSC” in ASCII). 1 = Enables the Write Protect if WPKEY corresponds to 0x535343 (“SSC” in ASCII).
30.9.18 SSC Write Protect Status Register Name: SSC_WPSR Address: 0x400040E8 Access: Read-only Reset: See Table 30-6 31 30 29 28 27 26 25 24 — — — — — — — — 23 22 21 20 19 18 17 16 11 10 9 8 WPVSRC 15 14 13 12 WPVSRC 7 6 5 4 3 2 1 0 — — — — — — — WPVS • WPVS: Write Protect Violation Status 0 = No Write Protect Violation has occurred since the last read of the SSC_WPSR register.
31. Parallel Input/Output Controller (PIO) 31.1 Description The Parallel Input/Output Controller (PIO) manages up to 32 fully programmable input/output lines. Each I/O line may be dedicated as a general-purpose I/O or be assigned to a function of an embedded peripheral. This assures effective optimization of the pins of a product. Each I/O line is associated with a bit number in all of the 32-bit registers of the 32-bit wide User Interface.
31.3 Block Diagram Figure 31-1. Block Diagram PIO Controller PIO Interrupt NVIC PIO Clock PMC Data, Enable Up to 32 peripheral IOs Embedded Peripheral PIN 0 Data, Enable PIN 1 Up to 32 pins Embedded Peripheral Up to 32 peripheral IOs PIN 31 APB Figure 31-2.
31.4 Product Dependencies 31.4.1 Pin Multiplexing Each pin is configurable, according to product definition as either a general-purpose I/O line only, or as an I/O line multiplexed with one or two peripheral I/Os. As the multiplexing is hardware defined and thus product-dependent, the hardware designer and programmer must carefully determine the configuration of the PIO controllers required by their application. When an I/O line is general-purpose only, i.e.
31.5 Functional Description The PIO Controller features up to 32 fully-programmable I/O lines. Most of the control logic associated to each I/O is represented in Figure 31-3. In this description each signal shown represents but one of up to 32 possible indexes. Figure 31-3.
31.5.1 Pull-up Resistor Control Each I/O line is designed with an embedded pull-up resistor. The pull-up resistor can be enabled or disabled by writing respectively PIO_PUER (Pull-up Enable Register) and PIO_PUDR (Pull-up Disable Resistor). Writing in these registers results in setting or clearing the corresponding bit in PIO_PUSR (Pull-up Status Register). Reading a 1 in PIO_PUSR means the pull-up is disabled and reading a 0 means the pull-up is enabled.
31.5.4 Output Control When the I/0 line is assigned to a peripheral function, i.e. the corresponding bit in PIO_PSR is at 0, the drive of the I/O line is controlled by the peripheral. Peripheral A or B depending on the value in PIO_ABSR (AB Select Register) determines whether the pin is driven or not. When the I/O line is controlled by the PIO controller, the pin can be configured to be driven. This is done by writing PIO_OER (Output Enable Register) and PIO_ODR (Output Disable Register).
Figure 31-4. Output Line Timings MCK Write PIO_SODR Write PIO_ODSR at 1 APB Access Write PIO_CODR Write PIO_ODSR at 0 APB Access PIO_ODSR 2 cycles 2 cycles PIO_PDSR 31.5.8 Inputs The level on each I/O line can be read through PIO_PDSR (Pin Data Status Register). This register indicates the level of the I/O lines regardless of their configuration, whether uniquely as an input or driven by the PIO controller or driven by a peripheral.
The glitch filters are controlled by the register set: PIO_IFER (Input Filter Enable Register), PIO_IFDR (Input Filter Disable Register) and PIO_IFSR (Input Filter Status Register). Writing PIO_IFER and PIO_IFDR respectively sets and clears bits in PIO_IFSR. This last register enables the glitch filter on the I/O lines. When the glitch and/or debouncing filter is enabled, it does not modify the behavior of the inputs on the peripherals.
These Additional Modes are: Rising Edge Detection Falling Edge Detection Low Level Detection High Level Detection In order to select an Additional Interrupt Mode: The type of event detection (Edge or Level) must be selected by writing in the set of registers; PIO_ESR (Edge Select Register) and PIO_LSR (Level Select Register) which enable respectively, the Edge and Level Detection. The current status of this selection is accessible through the PIO_ELSR (Edge/Level Status Register).
Figure 31-7. Event Detector on Input Lines (Figure represents line 0) Event Detector Rising Edge Detector 1 Falling Edge Detector 0 0 PIO_REHLSR[0] 1 PIO_FRLHSR[0] Resynchronized input on line 0 Event detection on line 0 1 PIO_FELLSR[0] 0 High Level Detector 1 Low Level Detector 0 PIO_LSR[0] PIO_ELSR[0] PIO_ESR[0] PIO_AIMER[0] PIO_AIMMR[0] PIO_AIMDR[0] Edge Detector 31.5.10.
Figure 31-8. Input Change Interrupt Timings if there are no Additional Interrupt Modes MCK Pin Level PIO_ISR Read PIO_ISR APB Access APB Access 31.5.11 I/O Lines Lock When an I/O line is controlled by a peripheral (particularly the Pulse Width Modulation Controller PWM), it can become locked by the action of this peripheral via an input of the PIO controller.
31.6 I/O Lines Programming Example The programing example as shown in Table 31-2 below is used to obtain the following configuration.
31.6.1 Write Protection Registers To prevent any single software error that may corrupt PIO behavior, certain address spaces can be write-protected by setting the WPEN bit in the “PIO Write Protect Mode Register” (PIO_WPMR). If a write access to the protected registers is detected, then the WPVS flag in the PIO Write Protect Status Register (PIO_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted.
31.7 Parallel Input/Output Controller (PIO) User Interface Each I/O line controlled by the PIO Controller is associated with a bit in each of the PIO Controller User Interface registers. Each register is 32 bits wide. If a parallel I/O line is not defined, writing to the corresponding bits has no effect. Undefined bits read zero. If the I/O line is not multiplexed with any peripheral, the I/O line is controlled by the PIO Controller and PIO_PSR returns 1 systematically. Table 31-3.
Table 31-3.
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31.7.20 PIO Multi-driver Status Register Name: PIO_MDSR Address: 0x400E0E58 (PIOA), 0x400E1058 (PIOB), 0x400E1258 (PIOC), 0x400E1458 (PIOD), 0x400E1658 (PIOE), 0x400E1858 (PIOF) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Multi Drive Status.
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31.7.
31.7.23 PIO Pull Up Status Register Name: PIO_PUSR Address: 0x400E0E68 (PIOA), 0x400E1068 (PIOB), 0x400E1268 (PIOC), 0x400E1468 (PIOD), 0x400E1668 (PIOE), 0x400E1868 (PIOF) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Pull Up Status.
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31.7.31 PIO Output Write Status Register Name: PIO_OWSR Address: 0x400E0EA8 (PIOA), 0x400E10A8 (PIOB), 0x400E12A8 (PIOC), 0x400E14A8 (PIOD), 0x400E16A8 (PIOE), 0x400E18A8 (PIOF) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Output Write Status.
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31.7.
31.7.34 Additional Interrupt Modes Mask Register Name: PIO_AIMMR Address: 0x400E0EB8 (PIOA), 0x400E10B8 (PIOB), 0x400E12B8 (PIOC), 0x400E14B8 (PIOD), 0x400E16B8 (PIOE), 0x400E18B8 (PIOF) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Peripheral CD Status.
31.7.35 Edge Select Register Name: PIO_ESR Address: 0x400E0EC0 (PIOA), 0x400E10C0 (PIOB), 0x400E12C0 (PIOC), 0x400E14C0 (PIOD), 0x400E16C0 (PIOE), 0x400E18C0 (PIOF) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Edge Interrupt Selection. 0: No effect.
31.7.36 Level Select Register Name: PIO_LSR Address: 0x400E0EC4 (PIOA), 0x400E10C4 (PIOB), 0x400E12C4 (PIOC), 0x400E14C4 (PIOD), 0x400E16C4 (PIOE), 0x400E18C4 (PIOF) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Level Interrupt Selection. 0: No effect.
31.7.37 Edge/Level Status Register Name: PIO_ELSR Address: 0x400E0EC8 (PIOA), 0x400E10C8 (PIOB), 0x400E12C8 (PIOC), 0x400E14C8 (PIOD), 0x400E16C8 (PIOE), 0x400E18C8 (PIOF) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Edge/Level Interrupt source selection.
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31.7.41 Lock Status Register Name: PIO_LOCKSR Address: 0x400E0EE0 (PIOA), 0x400E10E0 (PIOB), 0x400E12E0 (PIOC), 0x400E14E0 (PIOD), 0x400E16E0 (PIOE), 0x400E18E0 (PIOF) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Lock Status.
31.7.42 PIO Write Protect Mode Register Name: PIO_WPMR Address: 0x400E0EE4 (PIOA), 0x400E10E4 (PIOB), 0x400E12E4 (PIOC), 0x400E14E4 (PIOD), 0x400E16E4 (PIOE), 0x400E18E4 (PIOF) Access: Read-write Reset: See Table 31-3 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 — — — — — — — WPEN For more information on Write Protection Registers, refer to Section 31.6.1 ”Write Protection Registers”.
31.7.
32. Serial Peripheral Interface (SPI) 32.1 Description The Serial Peripheral Interface (SPI) circuit is a synchronous serial data link that provides communication with external devices in Master or Slave Mode. It also enables communication between processors if an external processor is connected to the system. The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to other SPIs.
32.3 Block Diagram Figure 32-1. Block Diagram AHB Matrix DMA Ch. Peripheral Bridge APB SPCK MISO PMC MOSI MCK SPI Interface PIO NPCS0/NSS NPCS1 NPCS2 Interrupt Control NPCS3 SPI Interrupt 32.4 Application Block Diagram Figure 32-2.
32.5 Signal Description Table 32-1.
32.6 Product Dependencies 32.6.1 I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the SPI pins to their peripheral functions. Table 32-2.
32.7 Functional Description 32.7.1 Modes of Operation The SPI operates in Master Mode or in Slave Mode. Operation in Master Mode is programmed by writing at 1 the MSTR bit in the Mode Register. The pins NPCS0 to NPCS3 are all configured as outputs, the SPCK pin is driven, the MISO line is wired on the receiver input and the MOSI line driven as an output by the transmitter. If the MSTR bit is written at 0, the SPI operates in Slave Mode.
Figure 32-3. SPI Transfer Format (NCPHA = 1, 8 bits per transfer) 1 SPCK cycle (for reference) 2 3 4 6 5 7 8 SPCK (CPOL = 0) SPCK (CPOL = 1) MOSI (from master) MSB MISO (from slave) MSB 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB * NSS (to slave) * Not defined, but normally MSB of previous character received. Figure 32-4.
32.7.3 Master Mode Operations When configured in Master Mode, the SPI operates on the clock generated by the internal programmable baud rate generator. It fully controls the data transfers to and from the slave(s) connected to the SPI bus. The SPI drives the chip select line to the slave and the serial clock signal (SPCK). The SPI features two holding registers, the Transmit Data Register and the Receive Data Register, and a single Shift Register.
32.7.3.1 Master Mode Block Diagram Figure 32-5. Master Mode Block Diagram SPI_CSR0..3 SCBR Baud Rate Generator MCK SPCK SPI Clock SPI_CSR0..3 BITS NCPHA CPOL LSB MISO SPI_RDR RDRF OVRES RD MSB Shift Register MOSI SPI_TDR TDRE TD SPI_CSR0..
32.7.3.2 Master Mode Flow Diagram Figure 32-6. Master Mode Flow Diagram SPI Enable - NPCS defines the current Chip Select - CSAAT, DLYBS, DLYBCT refer to the fields of the Chip Select Register corresponding to the Current Chip Select - When NPCS is 0xF, CSAAT is 0.
Figure 32-7 shows Transmit Data Register Empty (TDRE), Receive Data Register (RDRF) and Transmission Register Empty (TXEMPTY) status flags behavior within the SPI_SR (Status Register) during an 8-bit data transfer in fixed mode and no Peripheral Data Controller involved. Figure 32-7.
These delays allow the SPI to be adapted to the interfaced peripherals and their speed and bus release time. Figure 32-8. Programmable Delays Chip Select 1 Chip Select 2 SPCK DLYBCS DLYBS DLYBCT DLYBCT 32.7.3.5 Peripheral Selection The serial peripherals are selected through the assertion of the NPCS0 to NPCS3 signals. By default, all the NPCS signals are high before and after each transfer.
transferred through MISO and MOSI lines with the chip select configuration registers. This is not the optimal means in term of memory size for the buffers, but it provides a very effective means to exchange data with several peripherals without any intervention of the processor. 32.7.3.7 Peripheral Chip Select Decoding The user can program the SPI to operate with up to 15 peripherals by decoding the four Chip Select lines, NPCS0 to NPCS3 with 1 of up to 16 decoder/demultiplexer.
32.7.3.8 Peripheral Deselection without DMAC During a transfer of more than one data on a Chip Select without the DMAC, the SPI_TDR is loaded by the processor, the flag TDRE rises as soon as the content of the SPI_TDR is transferred into the internal shift register. When this flag is detected high, the SPI_TDR can be reloaded.
Figure 32-10. Peripheral Deselection CSAAT = 0 and CSNAAT = 0 TDRE NPCS[0..3] CSAAT = 1 and CSNAAT= 0 / 1 DLYBCT DLYBCT A A A A DLYBCS A DLYBCS PCS = A PCS = A Write SPI_TDR TDRE NPCS[0..3] DLYBCT DLYBCT A A A A DLYBCS A DLYBCS PCS=A PCS = A Write SPI_TDR TDRE NPCS[0..3] DLYBCT DLYBCT A B A B DLYBCS DLYBCS PCS = B PCS = B Write SPI_TDR CSAAT = 0 and CSNAAT = 0 CSAAT = 0 and CSNAAT = 1 DLYBCT DLYBCT TDRE NPCS[0..
By default, the Mode Fault detection circuitry is enabled. The user can disable Mode Fault detection by setting the MODFDIS bit in the SPI Mode Register (SPI_MR). 32.7.4 SPI Slave Mode When operating in Slave Mode, the SPI processes data bits on the clock provided on the SPI clock pin (SPCK). The SPI waits for NSS to go active before receiving the serial clock from an external master.
32.7.5 Write Protected Registers To prevent any single software error that may corrupt SPI behavior, the registers listed below can be writeprotected by setting the WPEN bit in the SPI Write Protection Mode Register (SPI_WPMR). If a write access in a write-protected register is detected, then the WPVS flag in the SPI Write Protection Status Register (SPI_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted.
32.8 Serial Peripheral Interface (SPI) User Interface Table 32-5.
32.8.1 SPI Control Register Name: SPI_CR Address: 0x40008000 (0), 0x4000C000 (1) Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – LASTXFER 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 SWRST – – – – – SPIDIS SPIEN • SPIEN: SPI Enable 0 = No effect. 1 = Enables the SPI to transfer and receive data. • SPIDIS: SPI Disable 0 = No effect. 1 = Disables the SPI.
32.8.2 SPI Mode Register Name: SPI_MR Address: 0x40008004 (0), 0x4000C004 (1) Access: Read-write 31 30 29 28 27 26 19 18 25 24 17 16 DLYBCS 23 22 21 20 – – – – 15 14 13 12 11 10 9 8 – – – – – – – – PCS 7 6 5 4 3 2 1 0 LLB – WDRBT MODFDIS – PCSDEC PS MSTR This register can only be written if the WPEN bit is cleared in ”SPI Write Protection Mode Register”. • MSTR: Master/Slave Mode 0 = SPI is in Slave mode. 1 = SPI is in Master mode.
• LLB: Local Loopback Enable 0 = Local loopback path disabled. 1 = Local loopback path enabled LLB controls the local loopback on the data serializer for testing in Master Mode only. (MISO is internally connected on MOSI.) • PCS: Peripheral Chip Select This field is only used if Fixed Peripheral Select is active (PS = 0).
32.8.3 SPI Receive Data Register Name: SPI_RDR Address: 0x40008008 (0), 0x4000C008 (1) Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – 15 14 13 12 PCS 11 10 9 8 3 2 1 0 RD 7 6 5 4 RD • RD: Receive Data Data received by the SPI Interface is stored in this register right-justified. Unused bits read zero.
32.8.4 SPI Transmit Data Register Name: SPI_TDR Address: 0x4000800C (0), 0x4000C00C (1) Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – LASTXFER 23 22 21 20 19 18 17 16 – – – – 15 14 13 12 PCS 11 10 9 8 3 2 1 0 TD 7 6 5 4 TD • TD: Transmit Data Data to be transmitted by the SPI Interface is stored in this register. Information to be transmitted must be written to the transmit data register in a right-justified format.
32.8.
• SPIENS: SPI Enable Status 0 = SPI is disabled. 1 = SPI is enabled.
32.8.6 SPI Interrupt Enable Register Name: SPI_IER Address: 0x40008014 (0), 0x4000C014 (1) Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – UNDES TXEMPTY NSSR 7 6 5 4 3 2 1 0 – – – – OVRES MODF TDRE RDRF 0 = No effect. 1 = Enables the corresponding interrupt.
32.8.7 SPI Interrupt Disable Register Name: SPI_IDR Address: 0x40008018 (0), 0x4000C018 (1) Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – UNDES TXEMPTY NSSR 7 6 5 4 3 2 1 0 – – – – OVRES MODF TDRE RDRF 0 = No effect. 1 = Disables the corresponding interrupt.
32.8.8 SPI Interrupt Mask Register Name: SPI_IMR Address: 0x4000801C (0), 0x4000C01C (1) Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – UNDES TXEMPTY NSSR 7 6 5 4 3 2 1 0 – – – – OVRES MODF TDRE RDRF 0 = The corresponding interrupt is not enabled. 1 = The corresponding interrupt is enabled.
32.8.9 SPI Chip Select Register Name: SPI_CSRx[x=0..3] Address: 0x40008030 (0), 0x4000C030 (1) Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 DLYBCT 23 22 21 20 DLYBS 15 14 13 12 SCBR 7 6 5 4 BITS 3 2 1 0 CSAAT CSNAAT NCPHA CPOL This register can only be written if the WPEN bit is cleared in ”SPI Write Protection Mode Register”. Note: SPI_CSRx registers must be written even if the user wants to use the defaults.
• BITS: Bits Per Transfer (See the (Note:) below the register table; Section 32.8.9 “SPI Chip Select Register” on page 703.) The BITS field determines the number of data bits transferred. Reserved values should not be used.
Otherwise, the following equation determines the delay: 32 × DLYBCT Delay Between Consecutive Transfers = -----------------------------------MCK SAM3X / SAM3A [DATASHEET] Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15 705
32.8.
32.8.11 SPI Write Protection Status Register Name: SPI_WPSR Address: 0x400080E8 (0), 0x4000C0E8 (1) Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 WPVSRC 7 6 5 4 3 2 1 0 – – – – – – – WPVS • WPVS: Write Protection Violation Status 0 = No Write Protect Violation has occurred since the last read of the SPI_WPSR register.
33. Two-wire Interface (TWI) 33.1 Description The Atmel Two-wire Interface (TWI) interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds of up to 400 Kbits per second, based on a byte-oriented transfer format. It can be used with any Atmel Two-wire Interface bus Serial EEPROM and I²C compatible device such as Real Time Clock (RTC), Dot Matrix/Graphic LCD Controllers and Temperature Sensor, to name but a few.
33.3 List of Abbreviations Table 33-2. 33.4 Abbreviations Abbreviation Description TWI Two-wire Interface A Acknowledge NA Non Acknowledge P Stop S Start Sr Repeated Start SADR Slave Address ADR Any address except SADR R Read W Write Block Diagram Figure 33-1.
33.5 Application Block Diagram Figure 33-2. Application Block Diagram VDD Rp Host with TWI Interface Rp TWD TWCK Atmel TWI Serial EEPROM Slave 1 I²C RTC I²C LCD Controller I²C Temp. Sensor Slave 2 Slave 3 Slave 4 Rp: Pull up value as given by the I²C Standard 33.5.1 I/O Lines Description Table 33-3. I/O Lines Description Pin Name Pin Description TWD Two-wire Serial Data Input/Output TWCK Two-wire Serial Clock Input/Output 33.6 Type Product Dependencies 33.6.
33.6.3 Interrupt The TWI interface has an interrupt line connected to the Nested Vector Interrupt Controller (NVIC). In order to handle interrupts, the NVIC must be programmed before configuring the TWI. Table 33-5.
33.7 Functional Description 33.7.1 Transfer Format The data put on the TWD line must be 8 bits long. Data is transferred MSB first; each byte must be followed by an acknowledgement. The number of bytes per transfer is unlimited (see Figure 33-4). Each transfer begins with a START condition and terminates with a STOP condition (see Figure 33-3). A high-to-low transition on the TWD line while TWCK is high defines the START condition.
33.8 Master Mode 33.8.1 Definition The Master is the device that starts a transfer, generates a clock and stops it. 33.8.2 Application Block Diagram Figure 33-5. Master Mode Typical Application Block Diagram VDD Rp Host with TWI Interface Rp TWD TWCK Atmel TWI Serial EEPROM Slave 1 I²C RTC I²C LCD Controller I²C Temp. Sensor Slave 2 Slave 3 Slave 4 Rp: Pull up value as given by the I²C Standard 33.8.
While no new data is written in the TWI_THR, the Serial Clock Line is tied low. When new data is written in the TWI_THR, the SCL is released and the data is sent. To generate a STOP event, the STOP command must be performed by writing in the STOP field of TWI_CR. After a Master Write transfer, the Serial Clock line is stretched (tied low) while no new data is written in the TWI_THR or until a STOP command is performed. See Figure 33-6, Figure 33-7, and Figure 33-8. Figure 33-6.
Figure 33-8. Master Write with One Byte Internal Address and Multiple Data Bytes STOP command performed (by writing in the TWI_CR) TWD S DADR W A IADR A DATA n A DATA n+1 A DATA n+2 A P TWCK TXCOMP TXRDY Write THR (Data n) Write THR (Data n+1) Write THR (Data n+2) Last data sent 33.8.5 Master Receiver Mode The read sequence begins by setting the START bit. After the start condition has been sent, the master sends a 7bit slave address to notify the slave device.
Figure 33-10. Master Read with Multiple Data Bytes TWD S DADR R A DATA n A DATA (n+1) A DATA (n+m)-1 A DATA (n+m) N P TXCOMP Write START Bit RXRDY Read RHR DATA n Read RHR DATA (n+1) Read RHR DATA (n+m)-1 Read RHR DATA (n+m) Write STOP Bit after next-to-last data read RXRDY is used as Receive Ready for the PDC receive channel. 33.8.6 Internal Address The TWI interface can perform various transfer formats: Transfers with 7-bit slave address devices and 10-bit slave address devices. 33.8.6.
Figure 33-11. Master Write with One, Two or Three Bytes Internal Address and One Data Byte Three bytes internal address S TWD DADR W A IADR(23:16) A IADR(15:8) A IADR(7:0) A W A IADR(15:8) A IADR(7:0) A DATA A W A IADR(7:0) A DATA A DATA A P Two bytes internal address S TWD DADR P One byte internal address S TWD DADR P Figure 33-12.
33.8.7 Using the Peripheral DMA Controller (PDC) The use of the PDC significantly reduces the CPU load. To assure correct implementation, respect the following programming sequences: 33.8.7.1 Data Transmit with the PDC 1. Initialize the transmit PDC (memory pointers, size, etc.). 2. Configure the master mode (DADR, CKDIV, etc.). 3. Start the transfer by setting the PDC TXTEN bit. 4. Wait for the PDC end TX flag. 5. Disable the PDC by setting the PDC TXDIS bit. 33.8.7.2 Data Receive with the PDC 1.
Figure 33-15.
Figure 33-16.
Figure 33-17.
Figure 33-18.
Figure 33-19.
Figure 33-20.
33.9 Multi-master Mode 33.9.1 Definition More than one master may handle the bus at the same time without data corruption by using arbitration. Arbitration starts as soon as two or more masters place information on the bus at the same time, and stops (arbitration is lost) for the master that intends to send a logical one while the other master sends a logical zero. As soon as arbitration is lost by a master, it stops sending data and listens to the bus in order to detect a stop.
Figure 33-21. Programmer Sends Data While the Bus is Busy TWCK START sent by the TWI STOP sent by the master DATA sent by a master TWD DATA sent by the TWI Bus is busy Bus is free Transfer is kept TWI DATA transfer A transfer is programmed (DADR + W + START + Write THR) Bus is considered as free Transfer is initiated Figure 33-22.
Figure 33-23.
33.10 Slave Mode 33.10.1 Definition The Slave Mode is defined as a mode where the device receives the clock and the address from another device called the master. In this mode, the device never initiates and never completes the transmission (START, REPEATED_START and STOP conditions are always provided by the master). 33.10.2 Application Block Diagram Figure 33-24.
See Figure 33-25 on page 730. 33.10.4.2Write Sequence In the case of a Write sequence (SVREAD is low), the RXRDY (Receive Holding Register Ready) flag is set as soon as a character has been received in the TWI_RHR (TWI Receive Holding Register). RXRDY is reset when reading the TWI_RHR. TWI continues receiving data until a STOP condition or a REPEATED_START + an address different from SADR is detected. Note that at the end of the write sequence TXCOMP flag is set and SVACC reset.
Figure 33-25. Read Access Ordered by a MASTER SADR matches, TWI answers with an ACK SADR does not match, TWI answers with a NACK TWD S ADR R NA DATA NA P/S/Sr SADR R A DATA A ACK/NACK from the Master A DATA NA S/Sr TXRDY Read RHR Write THR NACK SVACC SVREAD SVREAD has to be taken into account only while SVACC is active EOSVACC Notes: 1. When SVACC is low, the state of SVREAD becomes irrelevant. 2.
In case of a WRITE command, the programmer has to decode the programming sequence and program a new SADR if the programming sequence matches. Figure 33-27 on page 731 describes the General Call access. Figure 33-27.
2. At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address different from SADR. 3. SCLWS is automatically set when the clock synchronization mechanism is started. Clock Synchronization in Write Mode The clock is tied low if the shift register and the TWI_RHR is full. If a STOP or REPEATED_START condition was not detected, it is tied low until TWI_RHR is read. Figure 33-29 on page 732 describes the clock synchronization in Read mode. Figure 33-29.
Figure 33-30. Repeated Start + Reversal from Read to Write Mode TWI_THR TWD DATA0 S SADR R A DATA0 DATA1 A DATA1 NA Sr SADR W A DATA2 TWI_RHR A DATA3 DATA2 A P DATA3 SVACC SVREAD TXRDY RXRDY EOSACC Cleared after read As soon as a START is detected TXCOMP 1. TXCOMP is only set at the end of the transmission because after the repeated start, SADR is detected again. Reversal of Write to Read The master initiates the communication by a write command and finishes it by a read command.
Figure 33-32.
33.11 Two-wire Interface (TWI) User Interface Table 33-6.
33.11.1 TWI Control Register Name: TWI_CR Address: 0x4008C000 (0), 0x40090000 (1) Access: Write-only Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 SWRST 6 QUICK 5 SVDIS 4 SVEN 3 MSDIS 2 MSEN 1 STOP 0 START • START: Send a START Condition 0 = No effect. 1 = A frame beginning with a START bit is transmitted according to the features defined in the mode register.
• SVEN: TWI Slave Mode Enabled 0 = No effect. 1 = If SVDIS = 0, the slave mode is enabled. Note: Switching from Master to Slave mode is only permitted when TXCOMP = 1. • SVDIS: TWI Slave Mode Disabled 0 = No effect. 1 = The slave mode is disabled. The shifter and holding characters (if it contains data) are transmitted in case of read operation. In write operation, the character being transferred must be completely received before disabling. • QUICK: SMBUS Quick Command 0 = No effect.
33.11.
33.11.3 TWI Slave Mode Register Name: TWI_SMR Address: 0x4008C008 (0), 0x40090008 (1) Access: Read-write Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 21 20 19 SADR 18 17 16 15 – 14 – 13 – 12 – 11 – 10 – 9 8 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – • SADR: Slave Address The slave device address is used in Slave mode in order to be accessed by master devices in read or write mode.
33.11.4 TWI Internal Address Register Name: TWI_IADR Address: 0x4008C00C (0), 0x4009000C (1) Access: Read-write Reset: 0x00000000 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 2 1 0 IADR 15 14 13 12 IADR 7 6 5 4 IADR • IADR: Internal Address 0, 1, 2 or 3 bytes depending on IADRSZ.
33.11.5 TWI Clock Waveform Generator Register Name: TWI_CWGR Address: 0x4008C010 (0), 0x40090010 (1) Access: Read-write Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 22 21 20 19 18 17 CKDIV 16 15 14 13 12 11 10 9 8 3 2 1 0 CHDIV 7 6 5 4 CLDIV TWI_CWGR is only used in Master mode.
33.11.6 TWI Status Register Name: TWI_SR Address: 0x4008C020 (0), 0x40090020 (1) Access: Read-only Reset: 0x0000F009 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 TXBUFE 14 RXBUFF 13 ENDTX 12 ENDRX 11 EOSACC 10 SCLWS 9 ARBLST 8 NACK 7 – 6 OVRE 5 GACC 4 SVACC 3 SVREAD 2 TXRDY 1 RXRDY 0 TXCOMP • TXCOMP: Transmission Completed (automatically set / reset) TXCOMP used in Master mode: 0 = During the length of the current frame.
If TXRDY is high and if a NACK has been detected, the transmission will be stopped. Thus when TRDY = NACK = 1, the programmer must not fill TWI_THR to avoid losing it. TXRDY behavior in Slave mode can be seen in Figure 33-25 on page 730, Figure 33-28 on page 731, Figure 33-30 on page 733 and Figure 33-31 on page 733. • SVREAD: Slave Read (automatically set / reset) This bit is only used in Slave mode. When SVACC is low (no Slave access has been detected) SVREAD is irrelevant.
• ARBLST: Arbitration Lost (clear on read) This bit is only used in Master mode. 0: Arbitration won. 1: Arbitration lost. Another master of the TWI bus has won the multi-master arbitration. TXCOMP is set at the same time. • SCLWS: Clock Wait State (automatically set / reset) This bit is only used in Slave mode. 0 = The clock is not stretched. 1 = The clock is stretched. TWI_THR / TWI_RHR buffer is not filled / emptied before the emission / reception of a new character.
33.11.
33.11.
33.11.
33.11.
33.11.
34. Universal Asynchronous Receiver Transceiver (UART) 34.1 Description The Universal Asynchronous Receiver Transmitter features a two-pin UART that can be used for communication and trace purposes and offers an ideal medium for in-situ programming solutions. Moreover, the association with two peripheral DMA controller (PDC) channels permits packet handling for these tasks with processor time reduced to a minimum. 34.
34.3 Block Diagram Figure 34-1. UART Functional Block Diagram Peripheral Bridge Peripheral DMA Controller APB UART UTXD Transmit Power Management Controller Parallel Input/ Output Baud Rate Generator MCK Receive URXD Interrupt Control Table 34-1. uart_irq UART Pin Description Pin Name Description Type URXD UART Receive Data Input UTXD UART Transmit Data Output 34.4 Product Dependencies 34.4.1 I/O Lines The UART pins are multiplexed with PIO lines.
34.5 UART Operations The UART operates in asynchronous mode only and supports only 8-bit character handling (with parity). It has no clock pin. The UART is made up of a receiver and a transmitter that operate independently, and a common baud rate generator. Receiver timeout and transmitter time guard are not implemented. However, all the implemented features are compatible with those of a standard USART. 34.5.
34.5.2.2 Start Detection and Data Sampling The UART only supports asynchronous operations, and this affects only its receiver. The UART receiver detects the start of a received character by sampling the URXD signal until it detects a valid start bit. A low level (space) on URXD is interpreted as a valid start bit if it is detected for more than 7 cycles of the sampling clock, which is 16 times the baud rate. Hence, a space that is longer than 7/16 of the bit period is detected as a valid start bit.
34.5.2.4 Receiver Overrun If UART_RHR has not been read by the software (or the Peripheral Data Controller or DMA Controller) since the last transfer, the RXRDY bit is still set and a new character is received, the OVRE status bit in UART_SR is set. OVRE is cleared when the software writes the control register UART_CR with the bit RSTSTA (Reset Status) at 1. Figure 34-6. Receiver Overrun S URXD D0 D1 D2 D3 D4 D5 D6 D7 P stop D0 S D1 D2 D3 D4 D5 D6 D7 P stop RXRDY OVRE RSTSTA 34.5.
34.5.3 Transmitter 34.5.3.1 Transmitter Reset, Enable and Disable After device reset, the UART transmitter is disabled and it must be enabled before being used. The transmitter is enabled by writing the control register UART_CR with the bit TXEN at 1. From this command, the transmitter waits for a character to be written in the Transmit Holding Register (UART_THR) before actually starting the transmission. The programmer can disable the transmitter by writing UART_CR with the bit TXDIS at 1.
Figure 34-10. Transmitter Control UART_THR Data 0 Data 1 Shift Register UTXD Data 0 S Data 0 Data 1 P stop S Data 1 P stop TXRDY TXEMPTY Write Data 0 in UART_THR Write Data 1 in UART_THR 34.5.4 Peripheral DMA Controller Both the receiver and the transmitter of the UART are connected to a Peripheral DMA Controller (PDC) channel. The peripheral data controller channels are programmed via registers that are mapped within the UART user interface from the offset 0x100.
34.5.5 Test Modes The UART supports three test modes. These modes of operation are programmed by using the field CHMODE (Channel Mode) in the mode register (UART_MR). The Automatic Echo mode allows bit-by-bit retransmission. When a bit is received on the URXD line, it is sent to the UTXD line. The transmitter operates normally, but has no effect on the UTXD line. The Local Loopback mode allows the transmitted characters to be received.
34.6 Universal Asynchronous Receiver Transceiver (UART) User Interface Table 34-3.
34.6.1 UART Control Register Name: UART_CR Address: 0x400E0800 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – RSTSTA 7 6 5 4 3 2 1 0 TXDIS TXEN RXDIS RXEN RSTTX RSTRX – – • RSTRX: Reset Receiver 0 = No effect. 1 = The receiver logic is reset and disabled. If a character is being received, the reception is aborted.
34.6.
34.6.
34.6.
34.6.
34.6.6 UART Status Register Name: UART_SR Address: 0x400E0814 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – RXBUFF TXBUFE – TXEMPTY – 7 6 5 4 3 2 1 0 PARE FRAME OVRE ENDTX ENDRX – TXRDY RXRDY • RXRDY: Receiver Ready 0 = No character has been received since the last read of the UART_RHR or the receiver is disabled.
• TXBUFE: Transmission Buffer Empty 0 = The buffer empty signal from the transmitter PDC channel is inactive. 1 = The buffer empty signal from the transmitter PDC channel is active. • RXBUFF: Receive Buffer Full 0 = The buffer full signal from the receiver PDC channel is inactive. 1 = The buffer full signal from the receiver PDC channel is active.
34.6.7 UART Receiver Holding Register Name: UART_RHR Address: 0x400E0818 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 RXCHR • RXCHR: Received Character Last received character if RXRDY is set.
34.6.8 UART Transmit Holding Register Name: UART_THR Address: 0x400E081C Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 TXCHR • TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set.
34.6.
35. Universal Synchronous Asynchronous Receiver Transmitter (USART) 35.1 Description The Universal Synchronous Asynchronous Receiver Transceiver (USART) provides one full duplex universal synchronous asynchronous serial link. Data frame format is widely programmable (data length, parity, number of stop bits) to support a maximum of standards. The receiver implements parity error, framing error and overrun error detection.
35.2 Embedded Characteristics Programmable Baud Rate Generator 5- to 9-bit Full-duplex Synchronous or Asynchronous Serial Communications ̶ 1, 1.
35.3 Block Diagram Figure 35-1. USART Block Diagram (Peripheral) DMA Controller Channel Channel PIO Controller USART RXD Receiver RTS Interrupt Controller USART Interrupt TXD Transmitter CTS PMC MCK DIV Baud Rate Generator SCK MCK/DIV User Interface SLCK APB Table 35-1.
35.4 Application Block Diagram Figure 35-2. Application Block Diagram IrLAP PPP Serial Driver Field Bus Driver EMV Driver IrDA Driver LIN Driver SPI Driver USART 35.5 RS232 Drivers RS485 Drivers Serial Port Differential Bus Smart Card Slot IrDA Transceivers LIN Transceiver SPI Bus I/O Lines Description Table 35-2.
35.6 Product Dependencies 35.6.1 I/O Lines The pins used for interfacing the USART may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the desired USART pins to their peripheral function. If I/O lines of the USART are not used by the application, they can be used for other purposes by the PIO Controller. To prevent the TXD line from falling when the USART is disabled, the use of an internal pull up is mandatory.
35.6.3 Interrupt The USART interrupt line is connected on one of the internal sources of the Interrupt Controller. Using the USART Table 35-4. Peripheral IDs Instance ID USART0 17 USART1 18 USART2 19 USART3 20 interrupt requires the Interrupt Controller to be programmed first. Note that it is not recommended to use the USART interrupt line in edge sensitive mode.
35.7 Functional Description The USART is capable of managing several types of serial synchronous or asynchronous communications. It supports the following communication modes: 5- to 9-bit full-duplex asynchronous serial communication ̶ MSB- or LSB-first ̶ 1, 1.
̶ 776 Remote loopback, local loopback, automatic echo SAM3X / SAM3A [DATASHEET] Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
35.7.1 Baud Rate Generator The Baud Rate Generator provides the bit period clock named the Baud Rate Clock to both the receiver and the transmitter.
Baud Rate Calculation Example Table 35-5 shows calculations of CD to obtain a baud rate at 38400 bauds for different source clock frequencies. This table also shows the actual resulting baud rate and the error. Table 35-5. Baud Rate Example (OVER = 0) Source Clock Expected Baud Rate MHz Bit/s 3 686 400 38 400 6.00 6 38 400.00 0.00% 4 915 200 38 400 8.00 8 38 400.00 0.00% 5 000 000 38 400 8.14 8 39 062.50 1.70% 7 372 800 38 400 12.00 12 38 400.00 0.00% 8 000 000 38 400 13.
clock divider. This feature is only available when using USART normal mode. The fractional Baud Rate is calculated using the following formula: SelectedClock Baudrate = --------------------------------------------------------------- 8 ( 2 – Over ) CD + FP ------- 8 The modified architecture is presented below: Figure 35-4.
35.7.1.4 Baud Rate in ISO 7816 Mode The ISO7816 specification defines the bit rate with the following formula: Di B = ------ × f Fi where: B is the bit rate Di is the bit-rate adjustment factor Fi is the clock frequency division factor f is the ISO7816 clock frequency (Hz) Di is a binary value encoded on a 4-bit field, named DI, as represented in Table 35-6. Table 35-6.
Figure 35-5. Elementary Time Unit (ETU) FI_DI_RATIO ISO7816 Clock Cycles ISO7816 Clock on SCK ISO7816 I/O Line on TXD 1 ETU 35.7.2 Receiver and Transmitter Control After reset, the receiver is disabled. The user must enable the receiver by setting the RXEN bit in the Control Register (US_CR). However, the receiver registers can be programmed before the receiver clock is enabled. After reset, the transmitter is disabled. The user must enable it by setting the TXEN bit in the Control Register (US_CR).
Figure 35-6. Character Transmit Example: 8-bit, Parity Enabled One Stop Baud Rate Clock TXD D0 Start Bit D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit The characters are sent by writing in the Transmit Holding Register (US_THR). The transmitter reports two status bits in the Channel Status Register (US_CSR): TXRDY (Transmitter Ready), which indicates that US_THR is empty and TXEMPTY, which indicates that all the characters written in US_THR have been processed.
The Manchester encoded character can also be encapsulated by adding both a configurable preamble and a start frame delimiter pattern. Depending on the configuration, the preamble is a training sequence, composed of a predefined pattern with a programmable length from 1 to 15 bit times. If the preamble length is set to 0, the preamble waveform is not generated prior to any character.
Figure 35-10. Start Frame Delimiter Preamble Length is set to 0 SFD Manchester encoded data DATA Txd One bit start frame delimiter SFD Manchester encoded data DATA Txd SFD Manchester encoded data Command Sync start frame delimiter DATA Txd Data Sync start frame delimiter Drift Compensation Drift compensation is available only in 16X oversampling mode. An hardware recovery system allows a larger clock drift. To enable the hardware system, the bit in the USART_MAN register must be set.
35.7.3.3 Asynchronous Receiver If the USART is programmed in asynchronous operating mode (SYNC = 0), the receiver oversamples the RXD input line. The oversampling is either 16 or 8 times the Baud Rate clock, depending on the OVER bit in the Mode Register (US_MR). The receiver samples the RXD line. If the line is sampled during one half of a bit time to 0, a start bit is detected and data, parity and stop bits are successively sampled on the bit rate clock.
35.7.3.4 Manchester Decoder When the MAN field in US_MR register is set to 1, the Manchester decoder is enabled. The decoder performs both preamble and start frame delimiter detection. One input line is dedicated to Manchester encoded input data. An optional preamble sequence can be defined, its length is user-defined and totally independent of the emitter side. Use RX_PL in US_MAN register to configure the length of the preamble sequence.
Figure 35-16. Manchester Error Flag Preamble Length is set to 4 Elementary character bit time SFD Manchester encoded data Txd Entering USART character area sampling points Preamble subpacket and Start Frame Delimiter were successfully decoded Manchester Coding Error detected When the start frame delimiter is a sync pattern (ONEBIT field to 0), both command and data delimiter are supported.
The USART module is configured as a Manchester encoder/decoder. Looking at the downstream communication channel, Manchester encoded characters are serially sent to the RF emitter. This may also include a user defined preamble and a start frame delimiter. Mostly, preamble is used in the RF receiver to distinguish between a valid data from a transmitter and signals due to noise. The Manchester stream is then modulated. See Figure 35-18 for an example of ASK modulation scheme.
Figure 35-20. Synchronous Mode Character Reception Example: 8-bit, Parity Enabled 1 Stop Baud Rate Clock RXD Sampling Start D0 D1 D2 D3 D4 D5 D6 D7 Stop Bit Parity Bit 35.7.3.7 Receiver Operations When a character reception is completed, it is transferred to the Receive Holding Register (US_RHR) and the RXRDY bit in the Status Register (US_CSR) rises. If a character is completed while the RXRDY is set, the OVRE (Overrun Error) bit is set.
Table 35-9 shows an example of the parity bit for the character 0x41 (character ASCII “A”) depending on the configuration of the USART. Because there are two bits to 1, 1 bit is added when a parity is odd, or 0 is added when a parity is even. Table 35-9.
The duration of the idle state is programmed in the TG field of the Transmitter Timeguard Register (US_TTGR). When this field is programmed to zero no timeguard is generated. Otherwise, the transmitter holds a high level on TXD after each transmitted byte during the number of bit periods programmed in TG in addition to the number of stop bits. As illustrated in Figure 35-23, the behavior of TXRDY and TXEMPTY status bits is modified by the programming of a timeguard.
35.7.3.11 Receiver Time-out The Receiver Time-out provides support in handling variable-length frames. This feature detects an idle condition on the RXD line. When a time-out is detected, the bit TIMEOUT in the Channel Status Register (US_CSR) rises and can generate an interrupt, thus indicating to the driver an end of frame. The time-out delay period (during which the receiver waits for a new character) is programmed in the TO field of the Receiver Time-out Register (US_RTOR).
Table 35-11. Maximum Time-out Period (Continued) Baud Rate Bit Time Time-out 14400 69 4 551 19200 52 3 413 28800 35 2 276 33400 30 1 962 56000 18 1 170 57600 17 1 138 200000 5 328 35.7.3.12 Framing Error The receiver is capable of detecting framing errors. A framing error happens when the stop bit of a received character is detected at level 0. This can occur if the receiver and the transmitter are fully desynchronized.
The transmitter considers the break as though it is a character, i.e. the STTBRK and STPBRK commands are taken into account only if the TXRDY bit in US_CSR is to 1 and the start of the break condition clears the TXRDY and TXEMPTY bits as if a character is processed. Writing US_CR with both STTBRK and STPBRK bits to 1 can lead to an unpredictable result. All STPBRK commands requested without a previous STTBRK command are ignored.
Figure 35-27. Connection with a Remote Device for Hardware Handshaking USART Remote Device TXD RXD RXD TXD CTS RTS RTS CTS Setting the USART to operate with hardware handshaking is performed by writing the USART_MODE field in the Mode Register (US_MR) to the value 0x2.
35.7.4.1 ISO7816 Mode Overview The ISO7816 is a half duplex communication on only one bidirectional line. The baud rate is determined by a division of the clock provided to the remote device (see “Baud Rate Generator” on page 777). The USART connects to a smart card as shown in Figure 35-30. The TXD line becomes bidirectional and the Baud Rate Generator feeds the ISO7816 clock on the SCK pin.
Figure 35-31. T = 0 Protocol without Parity Error Baud Rate Clock RXD Start Bit D0 D2 D1 D4 D3 D5 D6 D7 Parity Guard Guard Next Bit Time 1 Time 2 Start Bit Figure 35-32. T = 0 Protocol with Parity Error Baud Rate Clock Error I/O Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Guard Bit Time 1 D0 Guard Start Time 2 Bit D1 Repetition Receive Error Counter The USART receiver also records the total number of errors. This can be read in the Number of Error (US_NER) register.
35.7.5 IrDA Mode The USART features an IrDA mode supplying half-duplex point-to-point wireless communication. It embeds the modulator and demodulator which allows a glueless connection to the infrared transceivers, as shown in Figure 35-33. The modulator and demodulator are compliant with the IrDA specification version 1.1 and support data transfer speeds ranging from 2.4 Kb/s to 115.2 Kb/s. The USART IrDA mode is enabled by setting the USART_MODE field in the Mode Register (US_MR) to the value 0x8.
Figure 35-34. IrDA Modulation Start Bit Transmitter Output 0 Stop Bit Data Bits 0 1 1 0 0 1 1 0 1 TXD 3 16 Bit Period Bit Period 35.7.5.2 IrDA Baud Rate Table 35-13 gives some examples of CD values, baud rate error and pulse duration. Note that the requirement on the maximum acceptable error of ±1.87% must be met. Table 35-13. IrDA Baud Rate Error Peripheral Clock Baud Rate CD Baud Rate Error Pulse Time 3 686 400 115 200 2 0.00% 1.63 20 000 000 115 200 11 1.38% 1.
35.7.5.3 IrDA Demodulator The demodulator is based on the IrDA Receive filter comprised of an 8-bit down counter which is loaded with the value programmed in US_IF. When a falling edge is detected on the RXD pin, the Filter Counter starts counting down at the Master Clock (MCK) speed. If a rising edge is detected on the RXD pin, the counter stops and is reloaded with US_IF. If no rising edge is detected when the counter reaches 0, the input of the receiver is driven low during one bit time.
35.7.6 RS485 Mode The USART features the RS485 mode to enable line driver control. While operating in RS485 mode, the USART behaves as though in asynchronous or synchronous mode and configuration of all the parameters is possible. The difference is that the RTS pin is driven high when the transmitter is operating. The behavior of the RTS pin is controlled by the TXEMPTY bit. A typical connection of the USART to a RS485 bus is shown in Figure 35-36. Figure 35-36.
35.7.7 SPI Mode The Serial Peripheral Interface (SPI) Mode is a synchronous serial data link that provides communication with external devices in Master or Slave Mode. It also enables communication between processors if an external processor is connected to the system. The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to other SPIs.
if the internal clock divided (MCK/DIV) is selected, the value programmed in CD must be even to ensure a 50:50 mark/space ratio on the SCK pin, this value can be odd if the internal clock is selected (MCK). In SPI Slave Mode: the external clock (SCK) selection is forced regardless of the value of the USCLKS field in the Mode Register (US_MR). Likewise, the value written in US_BRGR has no effect, because the clock is provided directly by the signal on the USART SCK pin.
Figure 35-38. SPI Transfer Format (CPHA=1, 8 bits per transfer) SCK cycle (for reference) 1 2 3 4 6 5 7 8 SCK (CPOL = 0) SCK (CPOL = 1) MOSI SPI Master ->TXD SPI Slave -> RXD MISO SPI Master ->RXD SPI Slave -> TXD MSB MSB 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB NSS SPI Master -> RTS SPI Slave -> CTS Figure 35-39.
35.7.7.4 Receiver and Transmitter Control See “Receiver and Transmitter Control” on page 781. 35.7.7.5 Character Transmission The characters are sent by writing in the Transmit Holding Register (US_THR). An additional condition for transmitting a character can be added when the USART is configured in SPI master mode.
The LIN (Local Interconnect Network) is a serial communication protocol which efficiently supports the control of mechatronic nodes in distributed automotive applications. The main properties of the LIN bus are: Single Master/Multiple Slaves concept Low cost silicon implementation based on common UART/SCI interface hardware, an equivalent in software, or as a pure state machine.
As soon as the Synch Break Field is transmitted, the flag LINBK in the Channel Status register (US_CSR) is set to 1. Likewise, as soon as the Identifier Field is sent, the flag LINID in the Channel Status register (US_CSR) is set to 1. These flags are reset by writing the bit RSTSTA to 1 in the Control register (US_CR). Figure 35-40.
35.7.8.7 Header Reception (Slave Node Configuration) All the LIN Frames start with a header which is sent by the master node and consists of a Synch Break Field, Synch Field and Identifier Field. In Slave node configuration, the frame handling starts with the reception of the header. The USART uses a break detection threshold of 11 nominal bit times at the actual baud rate. At any time, if 11 consecutive recessive bits are detected on the bus, the USART detects a Break Field.
35.7.8.8 Slave Node Synchronization The synchronization is done only in Slave node configuration. The procedure is based on time measurement between falling edges of the Synch Field. The falling edges are available in distances of 2, 4, 6 and 8 bit times. Figure 35-42. Synch Field Synch Field 8 Tbit 2 Tbit 2 Tbit 2 Tbit 2 Tbit Start bit Stop bit The time measurement is made by a 19-bit counter clocked by the sampling clock (see Section 35.7.1).
The following formula is used to compute the deviation of the slave bit rate relative to the master bit rate after synchronization (FSLAVE is the real slave node clock frequency).
35.7.8.10 Node Action In function of the identifier, the node is concerned, or not, by the LIN response. Consequently, after sending or receiving the identifier, the USART must be configured. There are three possible configurations: PUBLISH: the node sends the response. SUBSCRIBE: the node receives the response. IGNORE: the node is not concerned by the response, it does not send and does not receive the response.
35.7.8.11 Response Data Length The LIN response data length is the number of data fields (bytes) of the response excluding the checksum. The response data length can either be configured by the user or be defined automatically by bits 4 and 5 of the Identifier (compatibility to LIN Specification 1.1).
35.7.8.13 Frame Slot Mode This mode is useful only for Master nodes. It respects the following rule: each frame slot shall be longer than or equal to TFrame_Maximum. If the Frame Slot Mode is enabled (FSDIS = 0) and a frame transfer has been completed, the TXRDY flag is set again only after TFrame_Maximum delay, from the start of frame. So the Master node cannot send a new header if the frame slot duration of the previous frame is inferior to TFrame_Maximum.
Inconsistent Synch Field Error This error is generated in Slave node configuration, if the Synch Field character received is other than 0x55. This error is reported by flag LINISFE in the Channel Status Register (US_CSR). Identifier Parity Error This error is generated in Slave node configuration, if the parity of the identifier is wrong. This error can be generated only if the parity feature is enabled (PARDIS = 0). This error is reported by flag LINIPE in the Channel Status Register (US_CSR).
Figure 35-46. Master Node Configuration, NACT = PUBLISH Frame slot = TFrame_Maximum Frame Header Break Synch Data3 Interframe space Response space Protected Identifier Response Data 1 Data N-1 Checksum Data N TXRDY FSDIS=1 FSDIS=0 RXRDY Write US_LINIR Write US_THR Data 1 Data 2 Data 3 Data N LINTC Figure 35-47.
Figure 35-48. Master Node Configuration, NACT=IGNORE Frame slot = TFrame_Maximum Frame Break Response space Header Data3 Synch Protected Identifier Interframe space Response Data 1 Data N-1 Data N Checksum TXRDY FSDIS=1 FSDIS=0 RXRDY Write US_LINIR LINTC Slave Node Configuration Write TXEN and RXEN in US_CR to enable both the transmitter and the receiver. Write USART_MODE in US_MR to select the LIN mode and the Slave Node configuration.
Figure 35-49. Slave Node Configuration, NACT = PUBLISH Break Synch Protected Identifier Data 1 Data N-1 Data N Checksum Data N Checksum TXRDY RXRDY LINIDRX Read US_LINID Write US_THR Data 1 Data 2 Data 3 Data N LINTC Figure 35-50. Slave Node Configuration, NACT = SUBSCRIBE Break Synch Protected Identifier Data 1 Data N-1 TXRDY RXRDY LINIDRX Read US_LINID Read US_RHR Data 1 Data N-2 Data N-1 Data N LINTC Figure 35-51.
Master Node Configuration The user can choose between two PDC modes by the PDCM bit in the LIN Mode register (US_LINMR): PDCM = 1: the LIN configuration is stored in the WRITE buffer and it is written by the PDC in the Transmit Holding register US_THR (instead of the LIN Mode register US_LINMR). Because the PDC transfer size is limited to a byte, the transfer is split into two accesses. During the first access the bits, NACT, PARDIS, CHKDIS, CHKTYP, DLM and FSDIS are written.
In this configuration, the PDC transfers only the DATA. The Identifier must be read by the user in the LIN Identifier register (US_LINIR). The LIN mode must be written by the user in the LIN Mode register (US_LINMR). The WRITE buffer contains the DATA if the USART sends the response (NACT=PUBLISH). The READ buffer contains the DATA if the USART receives the response (NACT=SUBSCRIBE). Figure 35-54.
Table 35-16. Receiver Time-out programming LIN Specification 2.0 Baud Rate Time-out period TO 1 000 bit/s 4 000 2 400 bit/s 9 600 9 600 bit/s 4s 38 400 19 200 bit/s 76 800 20 000 bit/s 80 000 1.3 - 25 000 Tbits 25 000 35.7.9 Test Modes The USART can be programmed to operate in three different test modes. The internal loopback capability allows on-board diagnostics.
35.7.9.3 Local Loopback Mode Local loopback mode connects the output of the transmitter directly to the input of the receiver, as shown in Figure 35-57. The TXD and RXD pins are not used. The RXD pin has no effect on the receiver and the TXD pin is continuously driven high, as in idle state. Figure 35-57. Local Loopback Mode Configuration RXD Receiver 1 Transmitter TXD 35.7.9.4 Remote Loopback Mode Remote loopback mode directly connects the RXD pin to the TXD pin, as shown in Figure 35-58.
35.7.10 Write Protection Registers To prevent any single software error that may corrupt USART behavior, certain address spaces can be writeprotected by setting the WPEN bit in the USART Write Protect Mode Register (US_WPMR). If a write access to the protected registers is detected, then the WPVS flag in the USART Write Protect Status Register (US_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted.
35.8 Universal Synchronous Asynchronous Receiver Transmitter (USART) User Interface Table 35-17.
35.8.1 USART Control Register Name: US_CR Address: 0x40098000 (0), 0x4009C000 (1), 0x400A0000 (2), 0x400A4000 (3) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 LINWKUP 20 LINABT 19 RTSDIS/RCS 18 RTSEN/FCS 17 – 16 – 15 RETTO 14 RSTNACK 13 RSTIT 12 SENDA 11 STTTO 10 STPBRK 9 STTBRK 8 RSTSTA 7 TXDIS 6 TXEN 5 RXDIS 4 RXEN 3 RSTTX 2 RSTRX 1 – 0 – • RSTRX: Reset Receiver 0: No effect. 1: Resets the receiver. • RSTTX: Reset Transmitter 0: No effect.
• STTBRK: Start Break 0: No effect. 1: Starts transmission of a break after the characters present in US_THR and the Transmit Shift Register have been transmitted. No effect if a break is already being transmitted. • STPBRK: Stop Break 0: No effect. 1: Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods. No effect if no break is being transmitted. • STTTO: Start Time-out 0: No effect.
• RCS: Release SPI Chip Select – Applicable if USART operates in SPI Master Mode (USART_MODE = 0xE): RCS = 0: No effect. RCS = 1: Releases the Slave Select Line NSS (RTS pin). • LINABT: Abort LIN Transmission 0: No effect. 1: Abort the current LIN transmission. • LINWKUP: Send LIN Wakeup Signal 0: No effect: 1: Sends a wakeup signal on the LIN bus.
35.8.
• SYNC: Synchronous Mode Select 0: USART operates in Asynchronous Mode. 1: USART operates in Synchronous Mode. • CPHA: SPI Clock Phase – Applicable if USART operates in SPI Mode (USART_MODE = 0xE or 0xF): CPHA = 0: Data is changed on the leading edge of SPCK and captured on the following edge of SPCK. CPHA = 1: Data is captured on the leading edge of SPCK and changed on the following edge of SPCK. CPHA determines which edge of SPCK causes data to change and which edge causes data to be captured.
• MODE9: 9-bit Character Length 0: CHRL defines character length. 1: 9-bit character length. • CLKO: Clock Output Select 0: The USART does not drive the SCK pin. 1: The USART drives the SCK pin if USCLKS does not select the external clock SCK. • OVER: Oversampling Mode 0: 16x Oversampling. 1: 8x Oversampling. • INACK: Inhibit Non Acknowledge 0: The NACK is generated. 1: The NACK is not generated.
• MODSYNC: Manchester Synchronization Mode 0:The Manchester Start bit is a 0 to 1 transition 1: The Manchester Start bit is a 1 to 0 transition. • ONEBIT: Start Frame Delimiter Selector 0: Start Frame delimiter is COMMAND or DATA SYNC. 1: Start Frame delimiter is One Bit.
35.8.3 USART Interrupt Enable Register Name: US_IER Address: 0x40098008 (0), 0x4009C008 (1), 0x400A0008 (2), 0x400A4008 (3) Access: Write-only 31 – 30 – 29 LINSNRE 28 LINCE 27 LINIPE 26 LINISFE 25 LINBE 24 MANE 23 – 22 – 21 – 20 19 CTSIC 18 – 17 – 16 – 15 LINTC 14 LINID 13 NACK/LINBK 12 RXBUFF 11 TXBUFE 10 ITER/UNRE 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 ENDTX 3 ENDRX 2 RXBRK 1 TXRDY 0 RXRDY 0: No effect 1: Enables the corresponding interrupt.
• LINTC: LIN Transfer Completed Interrupt Enable • CTSIC: Clear to Send Input Change Interrupt Enable • MANE: Manchester Error Interrupt Enable • LINBE: LIN Bus Error Interrupt Enable • LINISFE: LIN Inconsistent Synch Field Error Interrupt Enable • LINIPE: LIN Identifier Parity Interrupt Enable • LINCE: LIN Checksum Error Interrupt Enable • LINSNRE: LIN Slave Not Responding Error Interrupt Enable 832 SAM3X / SAM3A [DATASHEET] Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
35.8.4 USART Interrupt Disable Register Name: US_IDR Address: 0x4009800C (0), 0x4009C00C (1), 0x400A000C (2), 0x400A400C (3) Access: Write-only 31 – 30 – 29 LINSNRE 28 LINCE 27 LINIPE 26 LINISFE 25 LINBE 24 MANE 23 – 22 – 21 – 20 19 CTSIC 18 – 17 – 16 – 15 LINTC 14 LINID 13 NACK/LINBK 12 RXBUFF 11 TXBUFE 10 ITER/UNRE 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 ENDTX 3 ENDRX 2 RXBRK 1 TXRDY 0 RXRDY 0: No effect 1: Disables the corresponding interrupt.
• LINTC: LIN Transfer Completed Interrupt Disable • CTSIC: Clear to Send Input Change Interrupt Disable • MANE: Manchester Error Interrupt Disable • LINBE: LIN Bus Error Interrupt Disable • LINISFE: LIN Inconsistent Synch Field Error Interrupt Disable • LINIPE: LIN Identifier Parity Interrupt Disable • LINCE: LIN Checksum Error Interrupt Disable • LINSNRE: LIN Slave Not Responding Error Interrupt Disable 834 SAM3X / SAM3A [DATASHEET] Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
35.8.5 USART Interrupt Mask Register Name: US_IMR Address: 0x40098010 (0), 0x4009C010 (1), 0x400A0010 (2), 0x400A4010 (3) Access: Read-only 31 – 30 – 29 LINSNRE 28 LINCE 27 LINIPE 26 LINISFE 25 LINBE 24 MANE 23 – 22 – 21 – 20 19 CTSIC 18 – 17 – 16 – 15 LINTC 14 LINID 13 NACK/LINBK 12 RXBUFF 11 TXBUFE 10 ITER/UNRE 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 ENDTX 3 ENDRX 2 RXBRK 1 TXRDY 0 RXRDY 0: The corresponding interrupt is not enabled.
• LINTC: LIN Transfer Completed Interrupt Mask • CTSIC: Clear to Send Input Change Interrupt Mask • MANE: Manchester Error Interrupt Mask • LINBE: LIN Bus Error Interrupt Mask • LINISFE: LIN Inconsistent Synch Field Error Interrupt Mask • LINIPE: LIN Identifier Parity Interrupt Mask • LINCE: LIN Checksum Error Interrupt Mask • LINSNRE: LIN Slave Not Responding Error Interrupt Mask 836 SAM3X / SAM3A [DATASHEET] Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
35.8.
• PARE: Parity Error 0: No parity error has been detected since the last RSTSTA. 1: At least one parity error has been detected since the last RSTSTA. • TIMEOUT: Receiver Time-out 0: There has not been a time-out since the last Start Time-out command (STTTO in US_CR) or the Time-out Register is 0. 1: There has been a time-out since the last Start Time-out command (STTTO in US_CR).
• LINID: LIN Identifier Sent or LIN Identifier Received – If USART operates in LIN Master Mode (USART_MODE = 0xA): 0: No LIN Identifier has been sent since the last RSTSTA. 1: At least one LIN Identifier has been sent since the last RSTSTA. – If USART operates in LIN Slave Mode (USART_MODE = 0xB): 0: No LIN Identifier has been received since the last RSTSTA.
• LINSNRE: LIN Slave Not Responding Error 0: No LIN Slave Not Responding Error has been detected since the last RSTSTA. 1: A LIN Slave Not Responding Error has been detected since the last RSTSTA.
35.8.7 USART Receive Holding Register Name: US_RHR Address: 0x40098018 (0), 0x4009C018 (1), 0x400A0018 (2), 0x400A4018 (3) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 RXSYNH 14 – 13 – 12 – 11 – 10 – 9 – 8 RXCHR 7 6 5 4 3 2 1 0 RXCHR • RXCHR: Received Character Last character received if RXRDY is set. • RXSYNH: Received Sync 0: Last Character received is a Data. 1: Last Character received is a Command.
35.8.8 USART Transmit Holding Register Name: US_THR Address: 0x4009801C (0), 0x4009C01C (1), 0x400A001C (2), 0x400A401C (3) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 TXSYNH 14 – 13 – 12 – 11 – 10 – 9 – 8 TXCHR 7 6 5 4 3 2 1 0 TXCHR • TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set.
35.8.9 USART Baud Rate Generator Register Name: US_BRGR Address: 0x40098020 (0), 0x4009C020 (1), 0x400A0020 (2), 0x400A4020 (3) Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 17 FP 16 15 14 13 12 11 10 9 8 3 2 1 0 CD 7 6 5 4 CD This register can only be written if the WPEN bit is cleared in “USART Write Protect Mode Register” on page 854.
35.8.10 USART Receiver Time-out Register Name: US_RTOR Address: 0x40098024 (0), 0x4009C024 (1), 0x400A0024 (2), 0x400A4024 (3) Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 TO 15 14 13 12 11 10 9 8 3 2 1 0 TO 7 6 5 4 TO This register can only be written if the WPEN bit is cleared in “USART Write Protect Mode Register” on page 854. • TO: Time-out Value 0: The Receiver Time-out is disabled.
35.8.11 USART Transmitter Timeguard Register Name: US_TTGR Address: 0x40098028 (0), 0x4009C028 (1), 0x400A0028 (2), 0x400A4028 (3) Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 TG This register can only be written if the WPEN bit is cleared in “USART Write Protect Mode Register” on page 854. • TG: Timeguard Value 0: The Transmitter Timeguard is disabled.
35.8.12 USART FI DI RATIO Register Name: US_FIDI Address: 0x40098040 (0), 0x4009C040 (1), 0x400A0040 (2), 0x400A4040 (3) Access: Read-write Reset Value: 0x174 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 9 FI_DI_RATIO 8 7 6 5 4 3 2 1 0 FI_DI_RATIO This register can only be written if the WPEN bit is cleared in “USART Write Protect Mode Register” on page 854.
35.8.13 USART Number of Errors Register Name: US_NER Address: 0x40098044 (0), 0x4009C044 (1), 0x400A0044 (2), 0x400A4044 (3) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 NB_ERRORS • NB_ERRORS: Number of Errors Total number of errors that occurred during an ISO7816 transfer. This register automatically clears when read.
35.8.14 USART IrDA FILTER Register Name: US_IF Address: 0x4009804C (0), 0x4009C04C (1), 0x400A004C (2), 0x400A404C (3) Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 IRDA_FILTER This register can only be written if the WPEN bit is cleared in “USART Write Protect Mode Register” on page 854. • IRDA_FILTER: IrDA Filter Sets the filter of the IrDA demodulator.
35.8.15 USART Manchester Configuration Register Name: US_MAN Address: 0x40098050 (0), 0x4009C050 (1), 0x400A0050 (2), 0x400A4050 (3) Access: Read-write 31 – 30 DRIFT 29 1 28 RX_MPOL 27 – 26 – 25 23 – 22 – 21 – 20 – 19 18 17 15 – 14 – 13 – 12 TX_MPOL 11 – 10 – 9 7 – 6 – 5 – 4 – 3 2 1 24 RX_PP 16 RX_PL 8 TX_PP 0 TX_PL This register can only be written if the WPEN bit is cleared in “USART Write Protect Mode Register” on page 854.
• RX_MPOL: Receiver Manchester Polarity 0: Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition. 1: Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition. • DRIFT: Drift compensation 0: The USART can not recover from an important clock drift 1: The USART can recover from clock drift. The 16X clock mode must be enabled.
35.8.16 USART LIN Mode Register Name: US_LINMR Address: 0x40098054 (0), 0x4009C054 (1), 0x400A0054 (2), 0x400A4054 (3) Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 PDCM 15 14 13 12 11 10 9 8 3 CHKDIS 2 PARDIS 1 DLC 7 WKUPTYP 6 FSDIS 5 DLM 4 CHKTYP 0 NACT • NACT: LIN Node Action Value Name Description 00 PUBLISH The USART transmits the response. 01 SUBSCRIBE The USART receives the response.
• WKUPTYP: Wakeup Signal Type 0: setting the bit LINWKUP in the control register sends a LIN 2.0 wakeup signal. 1: setting the bit LINWKUP in the control register sends a LIN 1.3 wakeup signal. • DLC: Data Length Control 0 - 255: Defines the response data length if DLM=0,in that case the response data length is equal to DLC+1 bytes. • PDCM: PDC Mode 0: The LIN mode register US_LINMR is not written by the PDC. 1: The LIN mode register US_LINMR (excepting that flag) is written by the PDC.
35.8.17 USART LIN Identifier Register Name: US_LINIR Address: 0x40098058 (0), 0x4009C058 (1), 0x400A0058 (2), 0x400A4058 (3) Access: Read-write or Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 IDCHR • IDCHR: Identifier Character If USART_MODE=0xA (Master node configuration): IDCHR is Read-write and its value is the Identifier character to be transmitted.
35.8.18 USART Write Protect Mode Register Name: US_WPMR Address: 0x400980E4 (0), 0x4009C0E4 (1), 0x400A00E4 (2), 0x400A40E4 (3) Access: Read-write Reset: See Table 35-17 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 — — — — — — — WPEN • WPEN: Write Protect Enable 0 = Disables the Write Protect if WPKEY corresponds to 0x555341 (“USA” in ASCII).
35.8.19 USART Write Protect Status Register Name: US_WPSR Address: 0x400980E8 (0), 0x4009C0E8 (1), 0x400A00E8 (2), 0x400A40E8 (3) Access: Read-only Reset: See Table 35-17 31 30 29 28 27 26 25 24 — — — — — — — — 23 22 21 20 19 18 17 16 11 10 9 8 WPVSRC 15 14 13 12 WPVSRC 7 6 5 4 3 2 1 0 — — — — — — — WPVS • WPVS: Write Protect Violation Status 0 = No Write Protect Violation has occurred since the last read of the US_WPSR register.
36. Timer Counter (TC) 36.1 Description A Timer Counter (TC) module includes three identical TC channels. The number of implemented TC modules is device-specific. Each TC channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation.
36.3 Block Diagram Table 36-1. Timer Counter Clock Assignment Name Definition TIMER_CLOCK1 MCK/2 TIMER_CLOCK2 MCK/8 TIMER_CLOCK3 MCK/32 TIMER_CLOCK4 MCK/128 TIMER_CLOCK5 SLCK Note: Figure 36-1. 1. When SLCK is selected for Peripheral Clock (CSS = 0 in PMC Master Clock Register), SLCK input is equivalent to Peripheral Clock.
Table 36-2. Signal Name Description Block/Channel Signal Name XC0, XC1, XC2 Channel Signal Capture Mode: Timer Counter Input Waveform Mode: Timer Counter Output TIOB Capture Mode: Timer Counter Input Waveform Mode: Timer Counter Input/Output Interrupt Signal Output (internal signal) SYNC Synchronization Input Signal (from configuration register) Pin Name List Table 36-3. 36.5 External Clock Inputs TIOA INT 36.
Table 36-4. I/O Lines (Continued) Instance Signal I/O Line Peripheral TC1 TIOA4 PB2 B TC1 TIOA4 PE11 A TC1 TIOA5 PB4 B TC1 TIOA5 PE13 A TC1 TIOB3 PB1 B TC1 TIOB3 PE10 A TC1 TIOB4 PB3 B TC1 TIOB4 PE12 A TC1 TIOB5 PB5 B TC1 TIOB5 PE14 A TC2 TCLK6 PC27 B TC2 TCLK7 PC30 B TC2 TCLK8 PD9 B TC2 TIOA6 PC25 B TC2 TIOA7 PC28 B TC2 TIOA8 PD7 B TC2 TIOB6 PC26 B TC2 TIOB7 PC29 B TC2 TIOB8 PD8 B 36.5.
36.6 Functional Description 36.6.1 Description All channels of the Timer Counter are independent and identical in operation except when the QDEC is enabled. The registers for channel programming are listed in Table 36-6 “Register Mapping”. 36.6.2 32-bit Counter Each 32-bit channel is organized around a 32-bit counter. The value of the counter is incremented at each positive edge of the selected clock.
Figure 36-2. Clock Chaining Selection TC0XC0S Timer/Counter Channel 0 TCLK0 TIOA1 XC0 TIOA2 TIOA0 XC1 = TCLK1 TIOB0 XC2 = TCLK2 SYNC TC1XC1S Timer/Counter Channel 1 TCLK1 TIOA1 XC0 = TCLK0 TIOA0 XC1 TIOA2 XC2 = TCLK2 TIOB1 SYNC Timer/Counter Channel 2 TC2XC2S XC0 = TCLK0 TCLK2 TIOA2 XC1 = TCLK1 TIOA0 XC2 TIOB2 TIOA1 SYNC Figure 36-3.
36.6.4 Clock Control The clock of each counter can be controlled in two different ways: it can be enabled/disabled and started/stopped. See Figure 36-4. The clock can be enabled or disabled by the user with the CLKEN and the CLKDIS commands in the TC Channel Control Register (TC_CCR). In Capture mode it can be disabled by an RB load event if LDBDIS is set to 1 in the TC_CMR. In Waveform mode, it can be disabled by an RC Compare event if CPCDIS is set to 1 in TC_CMR.
The following triggers are common to both modes: Software Trigger: Each channel has a software trigger, available by setting SWTRG in TC_CCR. SYNC: Each channel has a synchronization signal SYNC. When asserted, this signal has the same effect as a software trigger. The SYNC signals of all channels are asserted simultaneously by writing TC_BCR (Block Control) with SYNC set.
SAM3X / SAM3A [DATASHEET] Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15 MTIOA MTIOB 1 ABETRG CLKI If RA is not loaded or RB is Loaded Edge Detector ETRGEDG SWTRG Timer/Counter Channel BURST Peripheral Clock Synchronous Edge Detection S R OVF LDRB Edge Detector Edge Detector Capture Register A LDBSTOP R S CLKEN LDRA If RA is Loaded CPCTRG Counter RESET Trig CLK Q Q CLKSTA LDBDIS Capture Register B CLKDIS TC1_SR TIOA TIOB SYNC XC2 XC1 XC0 TIMER_CLOCK5 TIME
36.6.10 Waveform Mode Waveform mode is entered by setting the TC_CMRx.WAVE bit. In Waveform mode, the TC channel generates one or two PWM signals with the same frequency and independently programmable duty cycles, or generates different types of one-shot or repetitive pulses. In this mode, TIOA is configured as an output and TIOB is defined as an output if it is not used as an external event (EEVT parameter in TC_CMR).
1 SAM3X / SAM3A [DATASHEET] Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15 EEVT BURST ENETRG CLKI Timer/Counter Channel Edge Detector EEVTEDG SWTRG Peripheral Clock Synchronous Edge Detection Trig CLK R S OVF WAVSEL RESET Counter WAVSEL Q Compare RA = Register A Q CLKSTA Compare RC = Compare RB = CPCSTOP CPCDIS Register C CLKDIS Register B R S CLKEN CPAS INT BSWTRG BEEVT BCPB BCPC ASWTRG AEEVT ACPA ACPC Output Controller TIOB SYNC XC2 XC1 XC0 TIMER
36.6.11.1 WAVSEL = 00 When WAVSEL = 00, the value of TC_CV is incremented from 0 to 232-1. Once 232-1 has been reached, the value of TC_CV is reset. Incrementation of TC_CV starts again and the cycle continues. See Figure 36-7. An external event trigger or a software trigger can reset the value of TC_CV. It is important to note that the trigger may occur at any time. See Figure 36-8. RC Compare cannot be programmed to generate a trigger in this configuration.
36.6.11.2 WAVSEL = 10 When WAVSEL = 10, the value of TC_CV is incremented from 0 to the value of RC, then automatically reset on a RC Compare. Once the value of TC_CV has been reset, it is then incremented and so on. See Figure 36-9. It is important to note that TC_CV can be reset at any time by an external event or a software trigger if both are programmed correctly. See Figure 36-10.
36.6.11.3 WAVSEL = 01 When WAVSEL = 01, the value of TC_CV is incremented from 0 to 232-1 . Once 232-1 is reached, the value of TC_CV is decremented to 0, then re-incremented to 232-1 and so on. See Figure 36-11. A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV then increments. See Figure 36-12.
36.6.11.4 WAVSEL = 11 When WAVSEL = 11, the value of TC_CV is incremented from 0 to RC. Once RC is reached, the value of TC_CV is decremented to 0, then re-incremented to RC and so on. See Figure 36-13. A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV then increments. See Figure 36-14.
36.6.12 External Event/Trigger Conditions An external event can be programmed to be detected on one of the clock sources (XC0, XC1, XC2) or TIOB. The external event selected can then be used as a trigger. The EEVT parameter in TC_CMR selects the external trigger. The EEVTEDG parameter defines the trigger edge for each of the possible external triggers (rising, falling or both). If EEVTEDG is cleared (none), no external event is defined.
Figure 36-15. Predefined Connection of the Quadrature Decoder with Timer Counters Reset pulse SPEEDEN Quadrature Decoder 1 1 (Filter + Edge Detect + QD) TIOA Timer/Counter Channel 0 TIOA0 QDEN PHEdges 1 TIOB 1 XC0 TIOB0 TIOA0 PHA TIOB0 PHB TIOB1 IDX XC0 Speed/Position QDEN Index 1 TIOB TIOB1 1 XC0 Timer/Counter Channel 1 XC0 Rotation Direction Timer/Counter Channel 2 Speed Time Base 36.6.14.
Figure 36-16. Input Stage Input Pre-Processing MAXFILT SWAP 1 PHA Filter TIOA0 MAXFILT > 0 1 PHedge Direction and Edge Detection INVA 1 PHB Filter TIOB0 1 DIR 1 IDX INVB 1 1 IDX Filter TIOB1 IDXPHB INVIDX Input filtering can efficiently remove spurious pulses that might be generated by the presence of particulate contamination on the optical or magnetic disk of the rotary sensor. Spurious pulses can also occur in environments with high levels of electro-magnetic interference.
Figure 36-17.
36.6.14.3 Direction Status and Change Detection After filtering, the quadrature signals are analyzed to extract the rotation direction and edges of the two quadrature signals detected in order to be counted by timer/counter logic downstream. The direction status can be directly read at anytime in the TC_QISR. The polarity of the direction flag status depends on the configuration written in TC_BMR. INVA, INVB, INVIDX, SWAP modify the polarity of DIR flag.
configurable and corresponds to (MAXFILT + 1) × tperipheral clock ns. After being filtered there is no reason to have two edges closer than (MAXFILT + 1) × tperipheral clock ns under normal mode of operation. Figure 36-19.
Depending on the quadrature signals, the direction is decoded and allows to count up or down in timer/counter channels 0 and 1. The direction status is reported on TC_QISR. 36.6.14.5 Speed Measurement When SPEEDEN is set in the TC_BMR, the speed measure is enabled on channel 0. A time base must be defined on channel 2 by writing the TC_RC2 period register. Channel 2 must be configured in Waveform mode (WAVE bit set) in TC_CMR2.
36.6.16 Fault Mode At any time, the TC_RCx registers can be used to perform a comparison on the respective current channel counter value (TC_CVx) with the value of TC_RCx register. The CPCSx flags can be set accordingly and an interrupt can be generated. This interrupt is processed but requires an unpredictable amount of time to be achieve the required action. It is possible to trigger the FAULT output of the TIMER1 with CPCS from TC_SR0 and/or CPCS from TC_SR1.
36.7 Timer Counter (TC) User Interface Table 36-6.
36.7.1 TC Channel Control Register Name: TC_CCRx [x=0..2] Address: 0x40080000 (0)[0], 0x40080040 (0)[1], 0x40080080 (0)[2], 0x40084000 (1)[0], 0x40084040 (1)[1], 0x40084080 (1)[2], 0x40088000 (2)[0], 0x40088040 (2)[1], 0x40088080 (2)[2] Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 SWTRG 1 CLKDIS 0 CLKEN • CLKEN: Counter Clock Enable Command 0: No effect.
36.7.2 TC Channel Mode Register: Capture Mode Name: TC_CMRx [x=0..
• LDBDIS: Counter Clock Disable with RB Loading 0: Counter clock is not disabled when RB loading occurs. 1: Counter clock is disabled when RB loading occurs. • ETRGEDG: External Trigger Edge Selection Value Name Description 0 NONE The clock is not gated by an external signal. 1 RISING Rising edge 2 FALLING Falling edge 3 EDGE Each edge • ABETRG: TIOA or TIOB External Trigger Selection 0: TIOB is used as an external trigger. 1: TIOA is used as an external trigger.
36.7.3 TC Channel Mode Register: Waveform Mode Name: TC_CMRx [x=0..2] (WAVEFORM_MODE) Access: Read/Write 31 30 29 BSWTRG 23 28 27 BEEVT 22 20 14 13 7 CPCDIS 6 CPCSTOP WAVSEL 24 BCPB 19 AEEVT 15 WAVE 25 BCPC 21 ASWTRG 26 18 17 16 ACPC 12 ENETRG 11 4 3 CLKI 5 BURST ACPA 10 9 EEVT 8 EEVTEDG 2 1 TCCLKS 0 This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register.
• CPCDIS: Counter Clock Disable with RC Compare 0: Counter clock is not disabled when counter reaches RC. 1: Counter clock is disabled when counter reaches RC. • EEVTEDG: External Event Edge Selection Value Name Description 0 NONE None 1 RISING Rising edge 2 FALLING Falling edge 3 EDGE Each edge • EEVT: External Event Selection Signal selected as external event.
• ACPC: RC Compare Effect on TIOA Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle • AEEVT: External Event Effect on TIOA Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle • ASWTRG: Software Trigger Effect on TIOA Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle • BCPB: RB Compare Effect on TIOB Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle • B
• BSWTRG: Software Trigger Effect on TIOB 886 Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle SAM3X / SAM3A [DATASHEET] Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
36.7.4 TC Stepper Motor Mode Register Name: TC_SMMRx [x=0..
36.7.5 TC Counter Value Register Name: TC_CVx [x=0..2] Address: 0x40080010 (0)[0], 0x40080050 (0)[1], 0x40080090 (0)[2], 0x40084010 (1)[0], 0x40084050 (1)[1], 0x40084090 (1)[2], 0x40088010 (2)[0], 0x40088050 (2)[1], 0x40088090 (2)[2] Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CV 23 22 21 20 CV 15 14 13 12 CV 7 6 5 4 CV • CV: Counter Value CV contains the counter value in real time.
36.7.6 TC Register A Name: TC_RAx [x=0..2] Address: 0x40080014 (0)[0], 0x40080054 (0)[1], 0x40080094 (0)[2], 0x40084014 (1)[0], 0x40084054 (1)[1], 0x40084094 (1)[2], 0x40088014 (2)[0], 0x40088054 (2)[1], 0x40088094 (2)[2] Access: Read-only if TC_CMRx.WAVE = 0, Read/Write if TC_CMRx.
36.7.7 TC Register B Name: TC_RBx [x=0..2] Address: 0x40080018 (0)[0], 0x40080058 (0)[1], 0x40080098 (0)[2], 0x40084018 (1)[0], 0x40084058 (1)[1], 0x40084098 (1)[2], 0x40088018 (2)[0], 0x40088058 (2)[1], 0x40088098 (2)[2] Access: Read-only if TC_CMRx.WAVE = 0, Read/Write if TC_CMRx.
36.7.8 TC Register C Name: TC_RCx [x=0..2] Address: 0x4008001C (0)[0], 0x4008005C (0)[1], 0x4008009C (0)[2], 0x4008401C (1)[0], 0x4008405C (1)[1], 0x4008409C (1)[2], 0x4008801C (2)[0], 0x4008805C (2)[1], 0x4008809C (2)[2] Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RC 23 22 21 20 RC 15 14 13 12 RC 7 6 5 4 RC This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register.
36.7.9 TC Status Register Name: TC_SRx [x=0..
• ETRGS: External Trigger Status (cleared on read) 0: External trigger has not occurred since the last read of the Status Register. 1: External trigger has occurred since the last read of the Status Register. • CLKSTA: Clock Enabling Status 0: Clock is disabled. 1: Clock is enabled. • MTIOA: TIOA Mirror 0: TIOA is low. If TC_CMRx.WAVE = 0, this means that TIOA pin is low. If TC_CMRx.WAVE = 1, this means that TIOA is driven low. 1: TIOA is high. If TC_CMRx.WAVE = 0, this means that TIOA pin is high.
36.7.10 TC Interrupt Enable Register Name: TC_IERx [x=0..
• ETRGS: External Trigger 0: No effect. 1: Enables the External Trigger Interrupt.
36.7.11 TC Interrupt Disable Register Name: TC_IDRx [x=0..
• ETRGS: External Trigger 0: No effect. 1: Disables the External Trigger Interrupt.
36.7.12 TC Interrupt Mask Register Name: TC_IMRx [x=0..
• ETRGS: External Trigger 0: The External Trigger Interrupt is disabled. 1: The External Trigger Interrupt is enabled.
36.7.13 TC Block Control Register Name: TC_BCR Address: 0x400800C0 (0), 0x400840C0 (1), 0x400880C0 (2) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 SYNC • SYNC: Synchro Command 0: No effect. 1: Asserts the SYNC signal which generates a software trigger simultaneously for each of the channels.
36.7.14 TC Block Mode Register Name: TC_BMR Address: 0x400800C4 (0), 0x400840C4 (1), 0x400880C4 (2) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 23 22 21 20 19 – 18 – 17 IDXPHB 16 SWAP 12 EDGPHA 11 QDTRANS 10 SPEEDEN 9 POSEN 8 QDEN 4 3 2 1 0 MAXFILT 15 INVIDX 14 INVB 13 INVA 7 – 6 – 5 TC2XC2S 24 MAXFILT TC1XC1S TC0XC0S This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register.
• POSEN: Position Enabled 0: Disable position. 1: Enables the position measure on channel 0 and 1. • SPEEDEN: Speed Enabled 0: Disabled. 1: Enables the speed measure on channel 0, the time base being provided by channel 2. • QDTRANS: Quadrature Decoding Transparent 0: Full quadrature decoding logic is active (direction change detected). 1: Quadrature decoding logic is inactive (direction change inactive) but input filtering and edge detection are performed.
36.7.15 TC QDEC Interrupt Enable Register Name: TC_QIER Address: 0x400800C8 (0), 0x400840C8 (1), 0x400880C8 (2) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 QERR 1 DIRCHG 0 IDX • IDX: Index 0: No effect. 1: Enables the interrupt when a rising edge occurs on IDX input. • DIRCHG: Direction Change 0: No effect.
36.7.16 TC QDEC Interrupt Disable Register Name: TC_QIDR Address: 0x400800CC (0), 0x400840CC (1), 0x400880CC (2) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 QERR 1 DIRCHG 0 IDX • IDX: Index 0: No effect. 1: Disables the interrupt when a rising edge occurs on IDX input. • DIRCHG: Direction Change 0: No effect.
36.7.17 TC QDEC Interrupt Mask Register Name: TC_QIMR Address: 0x400800D0 (0), 0x400840D0 (1), 0x400880D0 (2) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 QERR 1 DIRCHG 0 IDX • IDX: Index 0: The interrupt on IDX input is disabled. 1: The interrupt on IDX input is enabled. • DIRCHG: Direction Change 0: The interrupt on rotation direction change is disabled.
36.7.18 TC QDEC Interrupt Status Register Name: TC_QISR Address: 0x400800D4 (0), 0x400840D4 (1), 0x400880D4 (2) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 DIR 7 – 6 – 5 – 4 – 3 – 2 QERR 1 DIRCHG 0 IDX • IDX: Index 0: No Index input change since the last read of TC_QISR. 1: The IDX input has changed since the last read of TC_QISR.
36.7.19 TC Fault Mode Register Name: TC_FMR Address: 0x400800D8 (0), 0x400840D8 (1), 0x400880D8 (2) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 ENCF1 0 ENCF0 This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register.
36.7.20 TC Write Protection Mode Register Name: TC_WPMR Address: 0x400800E4 (0), 0x400840E4 (1), 0x400880E4 (2) Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 WPEN WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 – 6 – 5 – 4 – • WPEN: Write Protection Enable 0: Disables the write protection if WPKEY corresponds to 0x54494D (“TIM” in ASCII). 1: Enables the write protection if WPKEY corresponds to 0x54494D (“TIM” in ASCII).
37. High Speed MultiMedia Card Interface (HSMCI) 37.1 Description The High Speed Multimedia Card Interface (HSMCI) supports the MultiMedia Card (MMC) Specification V4.3, the SD Memory Card Specification V2.0, the SDIO V2.0 specification and CE-ATA V1.1.
37.3 Block Diagram Figure 37-1. Block Diagram APB Bridge DMAC APB MCCK(1) MCCDA(1) MCDA0(1) PMC MCK MCDA1(1) MCDA2(1) MCDA3(1) MCCDB(1) HSMCI Interface PIO MCDB0(1) MCDB1(1) MCDB2(1) MCDB3(1) MCDB4(1) MCDB5(1) MCDB6(1) Interrupt Control MCDB7(1) HSMCI Interrupt Note: 910 1. When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to HSMCIx_CDA, MCCDB to HSMCIx_CDB, MCDAy to HSMCIx_DAy, MCDBy to HSMCIx_DBy.
37.4 Application Block Diagram Figure 37-2. Application Block Diagram Application Layer ex: File System, Audio, Security, etc. Physical Layer HSMCI Interface 1 2 3 4 5 6 7 1 2 3 4 5 6 78 9 9 1011 1213 8 SDCard MMC 37.5 Pin Name List Table 37-1. I/O Lines Description for 8-bit Configuration (2) Pin Name Pin Description Type(1) Comments MCCDA/MCCDB Command/response I/O/PP/OD CMD of an MMC or SDCard/SDIO MCCK Clock I/O CLK of an MMC or SD Card/SDIO MCDA0 - MCDA7 Data 0..
37.6 37.6.1 Product Dependencies I/O Lines The pins used for interfacing the High Speed MultiMedia Cards or SD Cards are multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the peripheral functions to HSMCI pins. Table 37-2. 37.6.
37.7 Bus Topology Figure 37-3. High Speed MultiMedia Memory Card Bus Topology 1 2 3 4 5 6 7 9 1011 1213 8 MMC The High Speed MultiMedia Card communication is based on a 13-pin serial bus interface. It has three communication lines and four supply lines. Table 37-4.
Figure 37-4. MMC Bus Connections (One Slot) HSMCI MCDA0 MCCDA MCCK 1 2 3 4 5 6 7 1 2 3 4 5 6 7 1 2 3 4 5 6 7 9 1011 9 1011 9 1011 1213 8 MMC1 Note: 1213 8 MMC2 1213 8 MMC3 When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to HSMCIx_CDA MCDAy to HSMCIx_DAy. Figure 37-5. SD Memory Card Bus Topology 1 2 3 4 5 6 78 9 SD CARD The SD Memory Card bus includes the signals listed in Table 37-5. Table 37-5.
SD Card Bus Connections with One Slot 1 2 3 4 5 6 78 Figure 37-6. MCDA0 - MCDA3 MCCK 9 MCCDA SD CARD When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to HSMCIx_CDA MCDAy to HSMCIx_DAy. Figure 37-7.
When the HSMCI is configured to operate with SD memory cards, the width of the data bus can be selected in the HSMCI_SDCR register. Clearing the SDCBUS bit in this register means that the width is one bit; setting it means that the width is four bits. In the case of High Speed MultiMedia cards, only the data line 0 is used. The other data lines can be used as independent PIOs. 37.
For example, to perform an ALL_SEND_CID command: Host Command CMD S T Content CRC NID Cycles E Z ****** CID Z S T Content Z Z Z The command ALL_SEND_CID and the fields and values for the HSMCI_CMDR Control Register are described in Table 37-6 and Table 37-7. Table 37-6.
Table 37-8. Command/Response Functional Flow Diagram Set the command argument HSMCI_ARGR = Argument(1) Set the command HSMCI_CMDR = Command Read HSMCI_SR Wait for command ready status flag 0 CMDRDY 1 Check error bits in the status register (1) Yes Status error flags? (1) RETURN ERROR Read response if required Does the command involve a busy indication? No RETURN OK Read HSMCI_SR 0 NOTBUSY 1 RETURN OK Note: 918 1.
37.8.2 Data Transfer Operation The High Speed MultiMedia Card allows several read/write operations (single block, multiple blocks, stream, etc.). These kinds of transfer can be selected setting the Transfer Type (TRTYP) field in the HSMCI Command Register (HSMCI_CMDR). These operations can be done using the features of the DMA Controller. In all cases, the block length (BLKLEN field) must be defined either in the mode register HSMCI_MR, or in the Block Register HSMCI_BLKR.
Figure 37-9.
37.8.4 Write Operation In write operation, the HSMCI Mode Register (HSMCI_MR) is used to define the padding value when writing nonmultiple block size. If the bit PADV is 0, then 0x00 value is used when padding data, otherwise 0xFF is used. If set, the bit DMAEN in the HSMCI_DMA register enables DMA transfer. The following flowchart (Figure 37-10) shows how to write a single block with or without use of DMA facilities.
Figure 37-10.
Figure 37-11.
37.8.5 WRITE_SINGLE_BLOCK Operation using DMA Controller 1. Wait until the current command execution has successfully terminated. c. 2. Check that CMDRDY and NOTBUSY fields are asserted in HSMCI_SR Program the block length in the card. This value defines the value block_length. 3. Program the block length in the HSMCI configuration register with block_length value. 4. Program HSMCI_DMA register with the following fields: ̶ OFFSET field with dma_offset.
37.8.6 READ_SINGLE_BLOCK Operation using DMA Controller 37.8.6.1 Block Length is Multiple of 4 1. Wait until the current command execution has successfully completed. a. Check that CMDRDY and NOTBUSY are asserted in HSMCI_SR. 2. Program the block length in the card. This value defines the value block_length. 3. Program the block length in the HSMCI configuration register with block_length value. 4. Set RDPROOF bit in HSMCI_MR to avoid overflow. 5.
37.8.6.2 Block Length is Not Multiple of 4 and Padding Not Used (ROPT field in HSMCI_DMA register set to 0) In the previous DMA transfer flow (block length multiple of 4), the DMA controller is configured to use only WORD AHB access. When the block length is no longer a multiple of 4 this is no longer true. The DMA controller is programmed to copy exactly the block length number of bytes using 2 transfer descriptors. 1. Use the previous step until READ_SINGLE_BLOCK then 2.
–SRC_WIDTH is set to BYTE. –SCSIZE must be set according to the value of HSMCI_DMA, CHKSIZE field. –BTSIZE is programmed with block_length[1:0]. (last 1, 2, or 3 bytes of the buffer). n. Program LLI_B.DMAC_CTRLBx with the following field’s values: –DST_INCR is set to INCR –SRC_INCR is set to INCR –FC field is programmed with peripheral to memory flow control mode. –Both SRC_DSCR and DST_DSCR are set to 1 (descriptor fetch is disabled) or Next descriptor location points to 0.
37.8.6.3 Block Length is Not Multiple of 4, with Padding Value (ROPT field in HSMCI_DMA register set to 1) When the ROPT field is set to one, The DMA Controller performs only WORD access on the bus to transfer a nonmultiple of 4 block length. Unlike previous flow, in which the transfer size is rounded to the nearest multiple of 4. 1. Program the HSMCI Interface, see previous flow. ̶ 2. ROPT field is set to 1. Program the DMA Controller a.
37.8.7 WRITE_MULTIPLE_BLOCK 37.8.7.1 One Block per Descriptor 1. Wait until the current command execution has successfully terminated. a. Check that CMDRDY and NOTBUSY are asserted in HSMCI_SR. 2. Program the block length in the card. This value defines the value block_length. 3. Program the block length in the HSMCI configuration register with block_length value. 4. Program HSMCI_DMA register with the following fields: ̶ OFFSET field with dma_offset. ̶ CHKSIZE is user defined.
i. If LLI(n) is the last descriptor, then LLI(n).DSCR points to 0 else LLI(n) points to the start address of LLI(n+1). j. Program DMAC_CTRLBx for channel register x with 0. Its content is updated with the LLI fetch operation. k. Program DMAC_DSCRx for channel register x with the address of the first descriptor LLI(0). l. Enable Channel x writing one to DMAC_CHER[x]. The DMA is ready and waiting for request. 7. Poll CBTC[x] bit in the DMAC_EBCISR Register. 8.
37.8.8 READ_MULTIPLE_BLOCK 37.8.8.1 Block Length is a Multiple of 4 1. Wait until the current command execution has successfully terminated. a. Check that CMDRDY and NOTBUSY are asserted in HSMCI_SR. 2. Program the block length in the card. This value defines the value block_length. 3. Program the block length in the HSMCI configuration register with block_length value. 4. Set RDPROOF bit in HSMCI_MR to avoid overflow. 5.
i. Program LLI_W(n).DMAC_DSCRx with the address of LLI_W(n+1) descriptor. And set the DSCRx_IF to the AHB Layer ID. This operation actually links descriptors together. If LLI_W(n) is the last descriptor then LLI_W(n).DMAC_DSCRx points to 0. j. Program DMAC_CTRLBx register for channel x with 0. its content is updated with the LLI Fetch operation. k. Program DMAC_DSCRx register for channel x with the address of LLI_W(0). l. Enable Channel x writing one to DMAC_CHER[x].
37.8.8.2 Block Length is Not Multiple of 4. (ROPT field in HSMCI_DMA register set to 0) Two DMA Transfer descriptors are used to perform the HSMCI block transfer. 1. Use the previous step to configure the HSMCI to perform a READ_MULTIPLE_BLOCK command. 2. Issue a READ_MULTIPLE_BLOCK command. 3. Program the DMA Controller to use a list of descriptors. a. Read the channel register to choose an available (disabled) channel. b.
–SRC_WIDTH is set to BYTE. –SCSIZE must be set according to the value of HSMCI_DMA, CHKSIZE field. –BTSIZE is programmed with block_length[1:0]. (last 1, 2, or 3 bytes of the buffer). o. Program LLI_B(n).DMAC_CTRLBx with the following field’s values: ̶ p. ̶ DST_INCR is set to INCR. ̶ SRC_INCR is set to INCR. ̶ FC field is programmed with peripheral to memory flow control mode. ̶ Both SRC_DSCR and DST_DSCR are set to 1 (descriptor fetch is disabled) or Next descriptor location points to 0.
37.8.8.3 Block Length is Not a Multiple of 4. (ROPT field in HSMCI_DMA register set to 1) One DMA Transfer descriptor is used to perform the HSMCI block transfer, the DMA writes a rounded up value to the nearest multiple of 4. 1. Use the previous step to configure the HSMCI to perform a READ_MULTIPLE_BLOCK. 2. Set the ROPT field to 1 in the HSMCI_DMA register. 3. Issue a READ_MULTIPLE_BLOCK command. 4. Program the DMA controller to use a list of descriptors: a.
9. 37.9 Wait for XFRDONE in HSMCI_SR register. SD/SDIO Card Operation The High Speed MultiMedia Card Interface allows processing of SD Memory (Secure Digital Memory Card) and SDIO (SD Input Output) Card commands. SD/SDIO cards are based on the Multi Media Card (MMC) format, but are physically slightly thicker and feature higher data transfer rates, a lock switch on the side to prevent accidental overwriting and security features.
37.10 CE-ATA Operation CE-ATA maps the streamlined ATA command set onto the MMC interface. The ATA task file is mapped onto MMC register space. CE-ATA utilizes five MMC commands: GO_IDLE_STATE (CMD0): used for hard reset. STOP_TRANSMISSION (CMD12): causes the ATA command currently executing to be aborted. FAST_IO (CMD39): Used for single register access to the ATA taskfile registers, 8 bit access only.
GO_IDLE_STATE (CMD0) to the device. GO_IDLE_STATE (CMD0) is a hard reset to the device and completely resets all device states. Note that after issuing GO_IDLE_STATE (CMD0), all device initialization needs to be completed again. If the CEATA device completes all MMC commands correctly but fails the ATA command with the ERR bit set in the ATA Status register, no error recovery action is required.
37.12 HSMCI Transfer Done Timings 37.12.1 Definition The XFRDONE flag in the HSMCI_SR indicates exactly when the read or write sequence is finished. 37.12.2 Read Access During a read access, the XFRDONE flag behaves as shown in Figure 37-12. Figure 37-12. XFRDONE During a Read Access CMD line HSMCI read CMD Card response The CMDRDY flag is released 8 tbit after the end of the card response. CMDRDY flag Data Last Block 1st Block Not busy flag XFRDONE flag 37.12.
37.13 Write Protection Registers To prevent any single software error that may corrupt HSMCI behavior, the entire HSMCI address space from address offset 0x000 to 0x00FC can be write-protected by setting the WPEN bit in the “HSMCI Write Protect Mode Register” (HSMCI_WPMR).
37.14 High Speed MultiMedia Card Interface (HSMCI) User Interface Table 37-9.
37.14.1 HSMCI Control Register Name: HSMCI_CR Address: 0x40000000 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 SWRST 6 – 5 – 4 – 3 PWSDIS 2 PWSEN 1 MCIDIS 0 MCIEN • MCIEN: Multi-Media Interface Enable 0: No effect. 1: Enables the Multi-Media Interface if MCDIS is 0. • MCIDIS: Multi-Media Interface Disable 0: No effect. 1: Disables the Multi-Media Interface.
37.14.2 HSMCI Mode Register Name: HSMCI_MR Address: 0x40000004 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 BLKLEN 23 22 21 20 BLKLEN 15 – 14 PADV 13 FBYTE 12 WRPROOF 11 RDPROOF 10 9 PWSDIV 8 7 6 5 4 3 2 1 0 CLKDIV This register can only be written if the WPEN bit is cleared in “HSMCI Write Protect Mode Register” on page 967. • CLKDIV: Clock Divider High Speed MultiMedia Card Interface clock (MCCK or HSMCI_CK) is Master Clock (MCK) divided by (2*(CLKDIV+1)).
• PADV: Padding Value 0: 0x00 value is used when padding data in write transfer. 1: 0xFF value is used when padding data in write transfer. PADV may be only in manual transfer. • BLKLEN: Data Block Length This field determines the size of the data block. This field is also accessible in the HSMCI Block Register (HSMCI_BLKR). Bits 16 and 17 must be set to 0 if FBYTE is disabled. Note: In SDIO Byte mode, BLKLEN field is not used.
37.14.3 HSMCI Data Timeout Register Name: HSMCI_DTOR Address: 0x40000008 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 5 DTOMUL 4 3 2 1 0 DTOCYC This register can only be written if the WPEN bit is cleared in “HSMCI Write Protect Mode Register” on page 967.
37.14.4 HSMCI SDCard/SDIO Register Name: HSMCI_SDCR Address: 0x4000000C Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 6 5 – 4 – 3 – 2 – 1 7 SDCBUS 0 SDCSEL This register can only be written if the WPEN bit is cleared in “HSMCI Write Protect Mode Register” on page 967. • SDCSEL: SDCard/SDIO Slot Value Name Description 0 SLOTA Slot A is selected.
37.14.
37.14.6 HSMCI Command Register Name: HSMCI_CMDR Address: 0x40000014 Access: Write-only 31 – 30 – 29 – 28 – 27 BOOT_ACK 26 ATACS 25 23 – 22 – 21 20 TRTYP 19 18 TRDIR 17 15 – 14 – 13 – 12 MAXLAT 11 OPDCMD 10 9 SPCMD 8 6 5 4 3 2 1 0 7 RSPTYP 24 IOSPCMD 16 TRCMD CMDNB This register is write-protected while CMDRDY is 0 in HSMCI_SR. If an Interrupt command is sent, this register is only writeable by an interrupt response (field SPCMD).
• OPDCMD: Open Drain Command 0 (PUSHPULL) = Push pull command. 1 (OPENDRAIN) = Open drain command. • MAXLAT: Max Latency for Command to Response 0 (5) = 5-cycle max latency. 1 (64) = 64-cycle max latency. • TRCMD: Transfer Command Value Name Description 0 NO_DATA 1 START_DATA Start data transfer 2 STOP_DATA Stop data transfer 3 – No data transfer Reserved • TRDIR: Transfer Direction 0 (WRITE) = Write. 1 (READ) = Read.
37.14.7 HSMCI Block Register Name: HSMCI_BLKR Address: 0x40000018 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 BLKLEN 23 22 21 20 BLKLEN 15 14 13 12 BCNT 7 6 5 4 BCNT • BCNT: MMC/SDIO Block Count - SDIO Byte Count This field determines the number of data byte(s) or block(s) to transfer.
37.14.8 HSMCI Completion Signal Timeout Register Name: HSMCI_CSTOR Address: 0x4000001C Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 5 CSTOMUL 4 3 2 1 0 CSTOCYC This register can only be written if the WPEN bit is cleared in “HSMCI Write Protect Mode Register” on page 967.
37.14.9 HSMCI Response Register Name: HSMCI_RSPR Address: 0x40000020 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RSP 23 22 21 20 RSP 15 14 13 12 RSP 7 6 5 4 RSP • RSP: Response Note: 952 1. The response register can be read by N accesses at the same HSMCI_RSPR or at consecutive addresses (0x20 to 0x2C). N depends on the size of the response.
37.14.
37.14.
37.14.12 HSMCI Status Register Name: HSMCI_SR Address: 0x40000040 Access: Read-only 31 UNRE 30 OVRE 29 ACKRCVE 28 ACKRCV 27 XFRDONE 26 FIFOEMPTY 25 DMADONE 24 BLKOVRE 23 CSTOE 22 DTOE 21 DCRCE 20 RTOE 19 RENDE 18 RCRCE 17 RDIRE 16 RINDE 15 14 13 12 11 10 – – CSRCV SDIOWAIT – – 9 SDIO IRQ for Slot B 8 SDIO IRQ for Slot A 7 – 6 – 5 NOTBUSY 4 DTIP 3 BLKE 2 TXRDY 1 RXRDY 0 CMDRDY • CMDRDY: Command Ready 0: A command is in progress. 1: The last command has been sent.
• NOTBUSY: HSMCI Not Busy This flag must be used only for Write Operations. A block write operation uses a simple busy signalling of the write operation duration on the data (DAT0) line: during a data transfer block, if the card does not have a free data receive buffer, the card indicates this condition by pulling down the data line (DAT0) to LOW. The card stops pulling down the data line as soon as at least one receive buffer for the defined data transfer block length becomes free.
• RTOE: Response Time-out Error 0: No error. 1: The response time-out set by MAXLAT in the HSMCI_CMDR has been exceeded. Cleared when writing in the HSMCI_CMDR. • DCRCE: Data CRC Error 0: No error. 1: A CRC16 error has been detected in the last data block. Cleared by reading in the HSMCI_SR register. • DTOE: Data Time-out Error 0: No error. 1: The data time-out set by DTOCYC and DTOMUL in HSMCI_DTOR has been exceeded. Cleared by reading in the HSMCI_SR register.
• OVRE: Overrun 0: No error. 1: At least one 8-bit received data has been lost (not read). Cleared when sending a new data transfer command. When FERRCTRL in HSMCI_CFG is set to 1, OVRE becomes reset after read. • UNRE: Underrun 0: No error. 1: At least one 8-bit data has been sent without valid information (not written). Cleared when sending a new data transfer command or when setting FERRCTRL in HSMCI_CFG to 1. When FERRCTRL in HSMCI_CFG is set to 1, UNRE becomes reset after read.
37.14.
• BLKOVRE: DMA Block Overrun Error Interrupt Enable • DMADONE: DMA Transfer completed Interrupt Enable • FIFOEMPTY: FIFO empty Interrupt enable • XFRDONE: Transfer Done Interrupt enable • ACKRCV: Boot Acknowledge Interrupt Enable • ACKRCVE: Boot Acknowledge Error Interrupt Enable • OVRE: Overrun Interrupt Enable • UNRE: Underrun Interrupt Enable 0: No effect. 1: Enables the corresponding interrupt.
37.14.
• DMADONE: DMA Transfer completed Interrupt Disable • FIFOEMPTY: FIFO empty Interrupt Disable • XFRDONE: Transfer Done Interrupt Disable • ACKRCV: Boot Acknowledge Interrupt Disable • ACKRCVE: Boot Acknowledge Error Interrupt Disable • OVRE: Overrun Interrupt Disable • UNRE: Underrun Interrupt Disable 0: No effect. 1: Disables the corresponding interrupt.
37.14.
• DMADONE: DMA Transfer Completed Interrupt Mask • FIFOEMPTY: FIFO Empty Interrupt Mask • XFRDONE: Transfer Done Interrupt Mask • ACKRCV: Boot Operation Acknowledge Received Interrupt Mask • ACKRCVE: Boot Operation Acknowledge Error Interrupt Mask • OVRE: Overrun Interrupt Mask • UNRE: Underrun Interrupt Mask 0: The corresponding interrupt is not enabled. 1: The corresponding interrupt is enabled.
37.14.16 HSMCI DMA Configuration Register Name: HSMCI_DMA Address: 0x40000050 Access: Read-write 31 30 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 ROPT 11 – 10 – 9 – 8 DMAEN 7 – 6 – 5 – 4 CHKSIZE 3 – 2 – 1 0 OFFSET This register can only be written if the WPEN bit is cleared in “HSMCI Write Protect Mode Register” on page 967.
37.14.17 HSMCI Configuration Register Name: HSMCI_CFG Address: 0x40000054 Access: Read-write 31 30 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 LSYNC 11 – 10 – 9 – 8 HSMODE 7 – 6 – 5 – 4 FERRCTRL 3 – 2 – 1 – 0 FIFOMODE This register can only be written if the WPEN bit is cleared in “HSMCI Write Protect Mode Register” on page 967.
37.14.18 HSMCI Write Protect Mode Register Name: HSMCI_WPMR Address: 0x400000E4 Access: Read-write 31 30 29 28 27 WP_KEY (0x4D => “M”) 26 25 24 23 22 21 20 19 WP_KEY (0x43 => C”) 18 17 16 15 14 13 12 11 WP_KEY (0x49 => “I”) 10 9 8 7 6 5 2 1 0 WP_EN 4 3 • WP_EN: Write Protection Enable 0: Disables the Write Protection if WP_KEY corresponds to 0x4D4349 (“MCI’ in ASCII). 1: Enables the Write Protection if WP_KEY corresponds to 0x4D4349 (“MCI’ in ASCII).
37.14.
37.14.20 HSMCI FIFOx Memory Aperture Name: HSMCI_FIFOx[x=0..
38. Pulse Width Modulation (PWM) 38.1 Description The PWM macrocell controls 8 channels independently. Each channel controls two complementary square output waveforms. Characteristics of the output waveforms such as period, duty-cycle, polarity and dead-times (also called dead-bands or non-overlapping times) are configured through the user interface. Each channel selects and uses one of the clocks provided by the clock generator.
38.
38.3 Block Diagram Figure 38-1.
38.5 Product Dependencies 38.5.1 I/O Lines The pins used for interfacing the PWM are multiplexed with PIO lines. The programmer must first program the PIO controller to assign the desired PWM pins to their peripheral function. If I/O lines of the PWM are not used by the application, they can be used for other purposes by the PIO controller. All of the PWM outputs may or may not be enabled. If an application requires only four channels, then only four PIO lines will be assigned to PWM outputs. Table 38-2.
Table 38-2. I/O Lines (Continued) PWM PWML1 PB17 B PWM PWML1 PC4 B PWM PWML2 PA20 B PWM PWML2 PB18 B PWM PWML2 PC6 B PWM PWML2 PE17 A PWM PWML3 PA0 B PWM PWML3 PB19 B PWM PWML3 PC8 B PWM PWML4 PC21 B PWM PWML4 PE19 A PWM PWML5 PC22 B PWM PWML5 PE21 A PWM PWML6 PC23 B PWM PWML6 PE23 A PWM PWML7 PC24 B PWM PWML7 PE25 A 38.5.2 Power Management The PWM is not continuously clocked.
Table 38-4. Fault Inputs Fault Inputs External PWM Fault Input Number Polarity Level(1) Fault Input ID PA5 PWMFI0 User Defined 0 PA3 PWMFI1 User Defined 1 PD6 PWMFI2 User Defined 2 MAIN OSC – 1 3 ADC – 1 4 Timer0 – 1 5 Note: 1. FPOL bit in PWMC_FMR.
38.6 Functional Description The PWM macrocell is primarily composed of a clock generator module and 8 channels. Clocked by the master clock (MCK), the clock generator module provides 13 clocks. Each channel can independently choose one of the clock generator outputs. Each channel generates an output waveform with attributes that can be defined independently for each channel through the user interface registers. 38.6.1 PWM Clock Generator Figure 38-2.
After a reset of the PWM controller, DIVA (DIVB) and PREA (PREB) are set to 0. This implies that after reset clkA (clkB) are turned off. At reset, all clocks provided by the modulo n counter are turned off except clock ”MCK”. This situation is also true when the PWM master clock is turned off through the Power Management Controller. CAUTION: Before using the PWM macrocell, the programmer must first enable the PWM clock in the Power Management Controller (PMC). 38.6.2 PWM Channel 38.6.2.
38.6.2.2 Comparator The comparator continuously compares its counter value with the channel period defined by CPRD in the “PWM Channel Period Register” on page 1048 (PWM_CPRDx) and the duty-cycle defined by CDTY in the “PWM Channel Duty Cycle Register” on page 1046 (PWM_CDTYx) to generate an output signal OCx accordingly. The different properties of the waveform of the output OCx are: the clock selection.
the waveform alignment. The output waveform can be left or center aligned. Center aligned waveforms can be used to generate non overlapped waveforms. This property is defined in the CALG field of the PWM_CMRx register. The default mode is left aligned. Figure 38-4. Non Overlapped Center Aligned Waveforms No overlap OC0 OC1 Period Note: 1. See Figure 38-5 on page 980 for a detailed description of center aligned waveforms.
Figure 38-5.
38.6.2.3 2-bit Gray Up/Down Counter for Stepper Motor It is possible to configure a couple of channels to provide a 2-bit gray count waveform on 2 outputs. Dead-Time Generator and other downstream logic can be configured on these channels. Up or down count mode can be configured on-the-fly by means of PWM_SMMR configuration registers. When GCEN0 is set to 1, channels 0 and 1 outputs are driven with gray counter. Figure 38-6. 2-bit Gray Up/Down Counter GCEN0 = 1 PWMH0 PWML0 PWMH1 PWML1 DOWNx 38.6.2.
Figure 38-7. Complementary Output Waveforms output waveform OCx CPOLx = 0 output waveform DTOHx DTHIx = 0 output waveform DTOLx DTLIx = 0 output waveform DTOHx DTHIx = 1 output waveform DTOLx DTLIx = 1 DTHx DTLx DTHx DTLx output waveform OCx CPOLx = 1 output waveform DTOHx DTHIx = 0 output waveform DTOLx DTLIx = 0 output waveform DTOHx DTHIx = 1 output waveform DTOLx DTLIx = 1 38.6.2.
By using buffer registers PWM_OSSUPD and PWM_OSCUPD, the output selection of PWM outputs is done synchronously to the channel counter, at the beginning of the next PWM period. By using registers PWM_OSS and PWM_OSC, the output selection of PWM outputs is done asynchronously to the channel counter, as soon as the register is written. The value of the current output selection can be read in PWM_OS.
The fault protection on a channel is triggered when this channel is enabled and when any one of the faults that are enabled for this channel is active. It can be triggered even if the PWM master clock (MCK) is not running but only by a fault input that is not glitch filtered.
38.6.2.7 Synchronous Channels Some channels can be linked together as synchronous channels. They have the same source clock, the same period, the same alignment and are started together. In this way, their counters are synchronized together. The synchronous channels are defined by the SYNCx bits in the “PWM Sync Channels Mode Register” (PWM_SCM). Only one group of synchronous channels is allowed.
Table 38-5.
Method 1: Manual write of duty-cycle values and manual trigger of the update In this mode, the update of the period value, the duty-cycle values and the dead-time values must be done by writing in their respective update registers with the CPU (respectively PWM_CPRDUPDx, PWM_CDTYUPDx and PWM_DTUPDx).
Method 2: Manual write of duty-cycle values and automatic trigger of the update In this mode, the update of the period value, the duty-cycle values, the dead-time values and the update period value must be done by writing in their respective update registers with the CPU (respectively PWM_CPRDUPDx, PWM_CDTYUPDx, PWM_DTUPDx and PWM_SCUPUPD).
Figure 38-11.
Method 3: Automatic write of duty-cycle values and automatic trigger of the update In this mode, the update of the duty cycle values is made automatically by the Peripheral DMA Controller (PDC). The update of the period value, the dead-time values and the update period value must be done by writing in their respective update registers with the CPU (respectiv ely PW M_CPR DUPDx , PWM_D TU PDx and PWM_SCUPUPD).
Sequence for Method 3: 1. Select the automatic write of duty-cycle values and automatic update by setting the field UPDM to 2 in the PWM_SCM register. 2. Define the synchronous channels by the bits SYNCx in the PWM_SCM register. 3. Define the update period by the field UPR in the PWM_SCUP register. 4.
Figure 38-12. Method 3 (UPDM=2 and PTRM=0) CCNT0 CDTYUPD UPRUPD 0x1 UPR 0x1 UPRCNT 0x0 CDTY 0x60 0x40 0x20 0x80 0xB0 0xA0 0x3 0x3 0x1 0x0 0x1 0x0 0x1 0x1 0x2 0x3 0x0 0x1 0x80 0x60 0x40 0x20 0x0 0x2 0xA0 PDC transfer request WRDY Figure 38-13.
38.6.3 PWM Comparison Units The PWM provides 8 independent comparison units able to compare a programmed value with the current value of the channel 0 counter (which is the channel counter of all synchronous channels, Section 38.6.2.7 “Synchronous Channels”). These comparisons are intended to generate pulses on the event lines (used to synchronize ADC, see Section 38.6.
is triggered. The comparison x update period CUPR itself can be updated while the channel 0 is enabled by using the PWM_CMPMUPDx register. CAUTION: to be taken into account, the write of the register PWM_CMPVUPDx must be followed by a write of the register PWM_CMPMUPDx. The comparison match and the comparison update can be source of an interrupt, but only if it is enabled and not masked.
38.6.4 PWM Event Lines The PWM provides 2 independent event lines intended to trigger actions in other peripherals (in particular for ADC (Analog-to-Digital Converter)). A pulse (one cycle of the master clock (MCK)) is generated on an event line, when at least one of the selected comparisons is matching. The comparisons can be selected or unselected independently by the CSEL bits in the “PWM Event Line x Register” (PWM_ELMRx for the Event Line x). Figure 38-16.
38.6.5 PWM Controller Operations 38.6.5.1 Initialization Before enabling the channels, they must have been configured by the software application: 996 Unlock User Interface by writing the WPCMD field in the PWM_WPCR Register. Configuration of the clock generator (DIVA, PREA, DIVB, PREB in the PWM_CLK register if required).
38.6.5.2 Source Clock Selection Criteria The large number of source clocks can make selection difficult. The relationship between the value in the “PWM Channel Period Register” (PWM_CPRDx) and the “PWM Channel Duty Cycle Register” (PWM_CDTYx) can help the user in choosing. The event number written in the Period Register gives the PWM accuracy. The Duty-Cycle quantum cannot be lower than 1/CPRDx value. The higher the value of PWM_CPRDx, the greater the PWM accuracy.
Figure 38-17.
38.6.5.4 Changing the Synchronous Channels Update Period It is possible to change the update period of synchronous channels while they are enabled. (See “Method 2: Manual write of duty-cycle values and automatic trigger of the update” on page 988 and “Method 3: Automatic write of duty-cycle values and automatic trigger of the update” on page 990.
38.6.5.5 Changing the Comparison Value and the Comparison Configuration It is possible to change the comparison values and the comparison configurations while the channel 0 is enabled (see Section 38.6.3 “PWM Comparison Units”).
38.6.5.6 Interrupts Depending on the interrupt mask in the PWM_IMR1 and PWM_IMR2 registers, an interrupt can be generated at the end of the corresponding channel period (CHIDx in the PWM_ISR1 register), after a fault event (FCHIDx in the PWM_ISR1 register), after a comparison match (CMPMx in the PWM_ISR2 register), after a comparison update (CMPUx in the PWM_ISR2 register) or according to the transfer mode of the synchronous channels (WRDY, ENDTX, TXBUFE and UNRE in the PWM_ISR2 register).
At any time, the user can determine which Write Protect is active in which register group by the fields WPSWS and WPHWS in the “PWM Write Protect Status Register” on page 1039 (PWM_WPSR). If a write access in a write-protected register is detected, then the WPVS flag in the PWM_WPSR register is set and the field WPVSRC indicates in which register the write access has been attempted, through its address offset without the two LSBs.
38.7 Pulse Width Modulation (PWM) User Interface Table 38-6.
Table 38-6.
Table 38-6.
38.7.1 PWM Clock Register Name: PWM_CLK Address: 0x40094000 Access: Read-write 31 – 30 – 29 – 28 – 27 26 23 22 21 20 19 18 11 10 25 24 17 16 9 8 1 0 PREB DIVB 15 – 14 – 13 – 12 – 7 6 5 4 PREA 3 2 DIVA This register can only be written if the bits WPSWS0 and WPHWS0 are cleared in “PWM Write Protect Status Register” on page 1039.
38.7.2 PWM Enable Register Name: PWM_ENA Address: 0x40094004 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 CHID7 6 CHID6 5 CHID5 4 CHID4 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID 0 = No effect. 1 = Enable PWM output for channel x.
38.7.3 PWM Disable Register Name: PWM_DIS Address: 0x40094008 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 CHID7 6 CHID6 5 CHID5 4 CHID4 3 CHID3 2 CHID2 1 CHID1 0 CHID0 This register can only be written if the bits WPSWS1 and WPHWS1 are cleared in “PWM Write Protect Status Register” on page 1039. • CHIDx: Channel ID 0 = No effect. 1 = Disable PWM output for channel x.
38.7.4 PWM Status Register Name: PWM_SR Address: 0x4009400C Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 CHID7 6 CHID6 5 CHID5 4 CHID4 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID 0 = PWM output for channel x is disabled. 1 = PWM output for channel x is enabled.
38.7.
38.7.
38.7.
38.7.8 PWM Interrupt Status Register 1 Name: PWM_ISR1 Address: 0x4009401C Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 FCHID7 22 FCHID6 21 FCHID5 20 FCHID4 19 FCHID3 18 FCHID2 17 FCHID1 16 FCHID0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 CHID7 6 CHID6 5 CHID5 4 CHID4 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Counter Event on Channel x 0 = No new counter event has occurred since the last read of the PWM_ISR1 register.
38.7.9 PWM Sync Channels Mode Register Name: PWM_SCM Address: 0x40094020 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 22 PTRCS 21 20 PTRM 19 – 18 – 17 16 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 SYNC7 6 SYNC6 5 SYNC5 4 SYNC4 3 SYNC3 2 SYNC2 1 SYNC1 0 SYNC0 UPDM This register can only be written if the bits WPSWS2 and WPHWS2 are cleared in “PWM Write Protect Status Register” on page 1039.
• PTRCS: PDC Transfer Request Comparison Selection Selection of the comparison used to set the flag WRDY and the corresponding PDC transfer request.
38.7.
38.7.11 PWM Sync Channels Update Period Register Name: PWM_SCUP Address: 0x4009402C Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 UPRCNT UPR • UPR: Update Period Defines the time between each update of the synchronous channels if automatic trigger of the update is activated (UPDM = 1 or UPDM = 2 in “PWM Sync Channels Mode Register” on page 1014).
38.7.12 PWM Sync Channels Update Period Update Register Name: PWM_SCUPUPD Address: 0x40094030 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 2 1 0 UPRUPD This register acts as a double buffer for the UPR value. This prevents an unexpected automatic trigger of the update of synchronous channels.
38.7.
38.7.
38.7.
38.7.16 PWM Interrupt Status Register 2 Name: PWM_ISR2 Address: 0x40094040 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 CMPU7 22 CMPU6 21 CMPU5 20 CMPU4 19 CMPU3 18 CMPU2 17 CMPU1 16 CMPU0 15 CMPM7 14 CMPM6 13 CMPM5 12 CMPM4 11 CMPM3 10 CMPM2 9 CMPM1 8 CMPM0 7 – 6 – 5 – 4 – 3 UNRE 2 TXBUFE 1 ENDTX 0 WRDY • WRDY: Write Ready for Synchronous Channels Update 0 = New duty-cycle and dead-time values for the synchronous channels cannot be written.
38.7.17 PWM Output Override Value Register Name: PWM_OOV Address: 0x40094044 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 OOVL7 22 OOVL6 21 OOVL5 20 OOVL4 19 OOVL3 18 OOVL2 17 OOVL1 16 OOVL0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 OOVH7 6 OOVH6 5 OOVH5 4 OOVH4 3 OOVH3 2 OOVH2 1 OOVH1 0 OOVH0 • OOVHx: Output Override Value for PWMH output of the channel x 0 = Override value is 0 for PWMH output of channel x.
38.7.18 PWM Output Selection Register Name: PWM_OS Address: 0x40094048 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 OSL7 22 OSL6 21 OSL5 20 OSL4 19 OSL3 18 OSL2 17 OSL1 16 OSL0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 OSH7 6 OSH6 5 OSH5 4 OSH4 3 OSH3 2 OSH2 1 OSH1 0 OSH0 • OSHx: Output Selection for PWMH output of the channel x 0 = Dead-time generator output DTOHx selected as PWMH output of channel x.
38.7.19 PWM Output Selection Set Register Name: PWM_OSS Address: 0x4009404C Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 OSSL7 22 OSSL6 21 OSSL5 20 OSSL4 19 OSSL3 18 OSSL2 17 OSSL1 16 OSSL0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 OSSH7 6 OSSH6 5 OSSH5 4 OSSH4 3 OSSH3 2 OSSH2 1 OSSH1 0 OSSH0 • OSSHx: Output Selection Set for PWMH output of the channel x 0 = No effect. 1 = Output override value OOVHx selected as PWMH output of channel x.
38.7.20 PWM Output Selection Clear Register Name: PWM_OSC Address: 0x40094050 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 OSCL7 22 OSCL6 21 OSCL5 20 OSCL4 19 OSCL3 18 OSCL2 17 OSCL1 16 OSCL0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 OSCH7 6 OSCH6 5 OSCH5 4 OSCH4 3 OSCH3 2 OSCH2 1 OSCH1 0 OSCH0 • OSCHx: Output Selection Clear for PWMH output of the channel x 0 = No effect. 1 = Dead-time generator output DTOHx selected as PWMH output of channel x.
38.7.21 PWM Output Selection Set Update Register Name: PWM_OSSUPD Address: 0x40094054 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 OSSUPL7 22 OSSUPL6 21 OSSUPL5 20 OSSUPL4 19 OSSUPL3 18 OSSUPL2 17 OSSUPL1 16 OSSUPL0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 OSSUPH7 6 OSSUPH6 5 OSSUPH5 4 OSSUPH4 3 OSSUPH3 2 OSSUPH2 1 OSSUPH1 0 OSSUPH0 • OSSUPHx: Output Selection Set for PWMH output of the channel x 0 = No effect.
38.7.22 PWM Output Selection Clear Update Register Name: PWM_OSCUPD Address: 0x40094058 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 OSCUPL7 22 OSCUPDL6 21 OSCUPL5 20 OSCUPL4 19 OSCUPL3 18 OSCUPL2 17 OSCUPL1 16 OSCUPL0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 OSCUPH7 6 OSCUPH6 5 OSCUPH5 4 OSCUPH4 3 OSCUPH3 2 OSCUPH2 1 OSCUPH1 0 OSCUPH0 • OSCUPHx: Output Selection Clear for PWMH output of the channel x 0 = No effect.
38.7.23 PWM Fault Mode Register Name: PWM_FMR Address: 0x4009405C Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 – 23 22 21 20 FFIL 15 14 13 12 FMOD 7 6 5 4 FPOL This register can only be written if the bits WPSWS5 and WPHWS5 are cleared in “PWM Write Protect Status Register” on page 1039.
38.7.24 PWM Fault Status Register Name: PWM_FSR Address: 0x40094060 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 – 23 22 21 20 – 15 14 13 12 FS 7 6 5 4 FIV • FIV: Fault Input Value (fault input bit varies from 0 to 5) For each field bit y (fault input number): 0 = The current sampled value of the fault input y is 0 (after filtering if enabled). 1 = The current sampled value of the fault input y is 1 (after filtering if enabled).
38.7.25 PWM Fault Clear Register Name: PWM_FCR Address: 0x40094064 Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 – 23 22 21 20 – 15 14 13 12 – 7 6 5 4 FCLR • FCLR: Fault Clear (fault input bit varies from 0 to 5) For each field bit y (fault input number): 0 = No effect.
38.7.26 PWM Fault Protection Value Register Name: PWM_FPV Address: 0x40094068 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 FPVL7 22 FPVL6 21 FPVL5 20 FPVL4 19 FPVL3 18 FPVL2 17 FPVL1 16 FPVL0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 FPVH7 6 FPVH6 5 FPVH5 4 FPVH4 3 FPVH3 2 FPVH2 1 FPVH1 0 FPVH0 This register can only be written if the bits WPSWS5 and WPHWS5 are cleared in “PWM Write Protect Status Register” on page 1039.
38.7.27 PWM Fault Protection Enable Register 1 Name: PWM_FPE1 Address: 0x4009406C Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 FPE3 23 22 21 20 FPE2 15 14 13 12 FPE1 7 6 5 4 FPE0 This register can only be written if the bits WPSWS5 and WPHWS5 are cleared in “PWM Write Protect Status Register” on page 1039. Only the first 6 bits (number of fault input pins) of fields FPE0, FPE1, FPE2 and FPE3 are significant.
38.7.28 PWM Fault Protection Enable Register 2 Name: PWM_FPE2 Address: 0x40094070 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 FPE7 23 22 21 20 FPE6 15 14 13 12 FPE5 7 6 5 4 FPE4 This register can only be written if the bits WPSWS5 and WPHWS5 are cleared in “PWM Write Protect Status Register” on page 1039. Only the first 6 bits (number of fault input pins) of fields FPE4, FPE5, FPE6 and FPE7 are significant.
38.7.29 PWM Event Line x Register Name: PWM_ELMRx Address: 0x4009407C Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 CSEL7 6 CSEL6 5 CSEL5 4 CSEL4 3 CSEL3 2 CSEL2 1 CSEL1 0 CSEL0 • CSELy: Comparison y Selection 0 = A pulse is not generated on the event line x when the comparison y matches. 1 = A pulse is generated on the event line x when the comparison y match.
38.7.30 PWM Stepper Motor Mode Register Name: PWM_SMMR Address: 0x400940B0 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 DOWN3 18 DOWN2 17 DOWN1 16 DOWN0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 GCEN3 2 GCEN2 1 GCEN1 0 GCEN0 • GCENx: Gray Count ENable 0 = Disable gray count generation on PWML[2*x], PWMH[2*x], PWML[2*x +1], PWMH[2*x +1] 1 = enable gray count generation on PWML[2*x], PWMH[2*x], PWML[2*x +1], PWMH[2*x +1.
38.7.31 PWM Write Protect Control Register Name: PWM_WPCR Address: 0x400940E4 Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 WPRG1 2 WPRG0 1 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 WPRG5 6 WPRG4 5 WPRG3 4 WPRG2 0 WPCMD • WPCMD: Write Protect Command This command is performed only if the WPKEY value is correct. 0 = Disable the Write Protect SW of the register groups of which the bit WPRGx is at 1.
• Register group 3: – “PWM Channel Period Register” on page 1048 – “PWM Channel Period Update Register” on page 1049 • Register group 4: – “PWM Channel Dead Time Register” on page 1051 – “PWM Channel Dead Time Update Register” on page 1052 • Register group 5: – “PWM Fault Mode Register” on page 1029 – “PWM Fault Protection Value Register” on page 1032 – “PWM Fault Protection Enable Register 1” on page 1033 – “PWM Fault Protection Enable Register 2” on page 1034 1038 SAM3X / SAM3A [DATASHEET] Atmel-11057C-
38.7.32 PWM Write Protect Status Register Name: PWM_WPSR Address: 0x400940E8 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 WPVSRC 23 22 21 20 WPVSRC 15 – 14 – 13 WPHWS5 12 WPHWS4 11 WPHWS3 10 WPHWS2 9 WPHWS1 8 WPHWS0 7 WPVS 6 – 5 WPSWS5 4 WPSWS4 3 WPSWS3 2 WPSWS2 1 WPSWS1 0 WPSWS0 • WPSWSx: Write Protect SW Status 0 = The Write Protect SW x of the register group x is disabled. 1 = The Write Protect SW x of the register group x is enabled.
38.7.33 PWM Comparison x Value Register Name: PWM_CMPVx Address: 0x40094130 [0], 0x40094140 [1], 0x40094150 [2], 0x40094160 [3], 0x40094170 [4], 0x40094180 [5], 0x40094190 [6], 0x400941A0 [7] Access: Read-write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 CVM 19 18 17 16 11 10 9 8 3 2 1 0 CV 15 14 13 12 CV 7 6 5 4 CV Only the first 16 bits (channel counter size) of field CV are significant.
38.7.34 PWM Comparison x Value Update Register Name: PWM_CMPVUPDx Address: 0x40094134 [0], 0x40094144 [1], 0x40094154 [2], 0x40094164 [3], 0x40094174 [4], 0x40094184 [5], 0x40094194 [6], 0x400941A4 [7] Access: Write-only 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 CVMUPD 19 18 17 16 11 10 9 8 3 2 1 0 CVUPD 15 14 13 12 CVUPD 7 6 5 4 CVUPD This register acts as a double buffer for the CV and CVM values. This prevents an unexpected comparison x match.
38.7.35 PWM Comparison x Mode Register Name: PWM_CMPMx Address: 0x40094138, 0x40094148, 0x40094158, 0x40094168, 0x40094178, 0x40094188, 0x40094198,0x400941A8 Access: Read-write 31 – 30 – 23 22 29 – 28 – 27 – 26 – 21 20 19 18 CUPRCNT 15 14 13 6 24 – 17 16 9 8 1 – 0 CEN CUPR 12 11 10 CPRCNT 7 25 – CPR 5 4 CTR 3 – 2 – • CEN: Comparison x Enable 0 = The comparison x is disabled and can not match. 1 = The comparison x is enabled and can match.
38.7.36 PWM Comparison x Mode Update Register Name: PWM_CMPMUPDx Address: 0x4009413C [0], 0x4009414C [1], 0x4009415C [2], 0x4009416C [3], 0x4009417C [4], 0x4009418C [5], 0x4009419C [6], 0x400941AC [7] Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 23 – 22 – 21 – 20 – 19 18 15 – 14 – 13 – 12 – 11 7 6 5 4 3 – CTRUPD 25 – 24 – 17 16 9 8 1 – 0 CENUPD CUPRUPD 10 CPRUPD 2 – This register acts as a double buffer for the CEN, CTR, CPR and CUPR values.
38.7.37 PWM Channel Mode Register Name: PWM_CMRx [x=0..
• CES: Counter Event Selection The bit CES defines when the channel counter event occurs when the period is center aligned (flag CHIDx in the “PWM Interrupt Status Register 1” on page 1013). CALG = 0 (Left Alignment): 0/1 = The channel counter event occurs at the end of the PWM period. CALG = 1 (Center Alignment): 0 = The channel counter event occurs at the end of the PWM period. 1 = The channel counter event occurs at the end of the PWM period and at half the PWM period.
38.7.38 PWM Channel Duty Cycle Register Name: PWM_CDTYx [x=0..7] Address: 0x40094204 [0], 0x40094224 [1], 0x40094244 [2], 0x40094264 [3], 0x40094284 [4], 0x400942A4 [5], 0x400942C4 [6], 0x400942E4 [7] Access: Read-write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 2 1 0 CDTY 15 14 13 12 CDTY 7 6 5 4 CDTY Only the first 16 bits (channel counter size) are significant. • CDTY: Channel Duty-Cycle Defines the waveform duty-cycle.
38.7.39 PWM Channel Duty Cycle Update Register Name: PWM_CDTYUPDx [x=0..7] Address: 0x40094208 [0], 0x40094228 [1], 0x40094248 [2], 0x40094268 [3], 0x40094288 [4], 0x400942A8 [5], 0x400942C8 [6], 0x400942E8 [7] Access: Write-only. 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 2 1 0 CDTYUPD 15 14 13 12 CDTYUPD 7 6 5 4 CDTYUPD This register acts as a double buffer for the CDTY value.
38.7.40 PWM Channel Period Register Name: PWM_CPRDx [x=0..7] Address: 0x4009420C [0], 0x4009422C [1], 0x4009424C [2], 0x4009426C [3], 0x4009428C [4], 0x400942AC [5], 0x400942CC [6], 0x400942EC [7] Access: Read-write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 2 1 0 CPRD 15 14 13 12 CPRD 7 6 5 4 CPRD This register can only be written if the bits WPSWS3 and WPHWS3 are cleared in “PWM Write Protect Status Register” on page 1039.
38.7.41 PWM Channel Period Update Register Name: PWM_CPRDUPDx [x=0..
38.7.42 PWM Channel Counter Register Name: PWM_CCNTx [x=0..7] Address: 0x40094214 [0], 0x40094234 [1], 0x40094254 [2], 0x40094274 [3], 0x40094294 [4], 0x400942B4 [5], 0x400942D4 [6], 0x400942F4 [7] Access: Read-only 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 2 1 0 CNT 15 14 13 12 CNT 7 6 5 4 CNT Only the first 16 bits (channel counter size) are significant. • CNT: Channel Counter Register Channel counter value.
38.7.43 PWM Channel Dead Time Register Name: PWM_DTx [x=0..7] Address: 0x40094218 [0], 0x40094238 [1], 0x40094258 [2], 0x40094278 [3], 0x40094298 [4], 0x400942B8 [5], 0x400942D8 [6], 0x400942F8 [7] Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 DTL 23 22 21 20 DTL 15 14 13 12 DTH 7 6 5 4 DTH This register can only be written if the bits WPSWS4 and WPHWS4 are cleared in “PWM Write Protect Status Register” on page 1039.
38.7.44 PWM Channel Dead Time Update Register Name: PWM_DTUPDx [x=0..7] Address: 0x4009421C [0], 0x4009423C [1], 0x4009425C [2], 0x4009427C [3], 0x4009429C [4], 0x400942BC [5], 0x400942DC [6], 0x400942FC [7] Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 DTLUPD 23 22 21 20 DTLUPD 15 14 13 12 DTHUPD 7 6 5 4 DTHUPD This register can only be written if the bits WPSWS4 and WPHWS4 are cleared in “PWM Write Protect Status Register” on page 1039.
39. USB On-The-Go Interface (UOTGHS) 39.1 Description The Universal Serial Bus (USB) MCU device complies with the Universal Serial Bus (USB) 2.0 specification in all speeds. Each pipe/endpoint can be configured in one of several USB transfer types. It can be associated with one, two or three banks of a DPRAM used to store the current data payload. If two or three banks are used, then one DPRAM bank is read or written by the CPU or the DMA, while the other is read or written by the UOTGHS core.
39.3 Block Diagram The UOTGHS provides a hardware device to interface a USB link to a data flow stored in a dual-port RAM (DPRAM). In normal operation (SPDCONF = 1), the UTMI transceiver requires the UTMI PLL (480 MHz). In case of Full or Low speed only, for a lower consumption (SPDCONF = 0), the UTMI transceiver only requires 48 MHz. Figure 39-1. UOTGHS Block Diagram APB Interface APB bus ctrl status DHSDP DHSDM AHB1 AHB bus Rd/Wr/Ready UTMI DMA AHB0 DFSDP DP DFSDM DM USB2.
39.3.1 Application Block Diagram 39.3.1.1 Device Mode Bus-Powered Device Figure 39-2. Bus-Powered Device Application Block Diagram VDD 3.3 V Regulator OTG USB USB Connector VBUS I/O Controller 2.0 Core UOTGID VBus UOTGVBOF ID DFSDM 39 ohms DFSDP 39 ohms D- UTMI D+ DHSDM GND DHSDP Figure 39-3. Self-powered Device Application Block Diagram OTG USB I/O Controller 2.
39.3.1.2 Host and OTG Modes Figure 39-4. Host and OTG Application Block Diagram VDD 5V DC/DC Generator OTG USB I/O Controller 2.0 Core USB Connector VBUS VBus UOTGID UOTGVBOF ID DFSDM 39 ohms DFSDP 39 ohms D- UTMI D+ DHSDM GND DHSDP 39.3.2 I/O Lines Description Table 39-2.
39.4 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 39.4.1 I/O Lines The UOTGVBOF and UOTGID pins are multiplexed with I/O Controller lines and may also be multiplexed with lines of other peripherals. In order to use them with the USB, the user must first configure the I/O Controller to assign them to their USB peripheral functions.
39.5 Functional Description 39.5.1 USB General Operation 39.5.1.1 Introduction After a hardware reset, the UOTGHS is disabled. When enabled, the UOTGHS runs either in device mode or in host mode according to the ID detection. If the UOTGID pin is not connected to the ground, the UOTGID Pin State bit in the General Status register (UOTGHS_SR.ID) is set (the internal pull-up resistor of the UOTGID pin must be enabled by the I/O Controller) and device mode is engaged. The UOTGHS_SR.
The UOTGHS can be disabled at any time by writing a zero to UOTGHS_CTRL.USBE. In fact, writing a zero to U O T G H S _ C T R L . U S B E a c t s a s a h a r d w a r e r e s e t , e x c e p t t h a t t h e U O T G H S _ C T R L . O T G PA D E , UOTGHS_CTRL.VBUSPO, UOTGHS_CTRL.FRZCLK, UOTGHS_CTRL.UIDE, UOTGHS_CTRL.UIMOD and, UOTGHS_DEVCTRL.LS bits are not reset. 39.5.1.3 Interrupts One interrupt vector is assigned to the USB interface. Figure 39-6 on page 1059 shows the structure of the USB interrupt system.
There are two kinds of general interrupts: processing, i.e. their generation is part of the normal processing, and exception, i.e. errors (not related to CPU exceptions). The processing general interrupts are: The ID Transition Interrupt (UOTGHS_SR.IDTI) The VBus Transition Interrupt (UOTGHS_SR.VBUSTI) The SRP Interrupt (UOTGHS_SR.SRPI) The Role Exchange Interrupt (UOTGHS_SR.ROLEEXI) The exception general interrupts are: The VBus Error Interrupt (UOTGHS_SR.
39.5.1.5 Speed Control Device mode When the USB interface is in device mode, the speed selection (full-speed or high-speed) is performed automatically by the UOTGHS during the USB reset according to the host speed capability. At the end of the USB reset, the UOTGHS enables or disables high-speed terminations and pull-up. It is possible to restraint the UOTGHS to full-speed or low-speed mode by handling the UOTGHS_DEVCTRL.LS and the Speed Configuration (UOTGHS_DEVCTRL.SPDCONF) bits in UOTGHS_DEVCTRL.
Figure 39-7 on page 1062 illustrates the allocation and reorganization of the DPRAM in a typical example. Figure 39-7. Allocation and Reorganization of the DPRAM Free Memory Free Memory Free Memory Free Memory PEP5 PEP5 PEP5 PEP5 PEP4 PEP4 PEP4 PEP3 PEP3 (ALLOC stays at 1) PEP4 PEP3 (larger size) PEP2 PEP2 PEP2 PEP2 PEP1 PEP1 PEP1 PEP1 PEP0 PEP0 PEP0 PEP0 Device: Device: UOTGHS_DEVEPT.EPENx = 1 UOTGHS_DEVEPT.EPEN3 = 0 UOTGHS_DEVEPTCFGx.ALLOC = 1 Device: UOTGHS_DEVEPTCFG3.
Figure 39-8. Pad Behavior Idle UOTGHS_CTRL.USBE = 1 & UOTGHS_DEVCTRL.DETACH = 0 & Suspend UOTGHS_CTRL.USBE = 0 | UOTGHS_DEVCTRL.DETACH = 1 | Suspend Active In the Idle state, the pad is put in low-power consumption mode, i.e., the differential receiver of the USB pad is off, and internal pull-downs with strong value (15 K) are set in both DP/DM to avoid floating lines. In the Active state, the pad is working. Figure 39-9 on page 1063 illustrates the pad events leading to a PAD state change.
39.5.1.8 Customizing of OTG Timers It is possible to refine some OTG timers thanks to the Timer Page (UOTGHS_CTRL.TIMPAGE) and Timer Value (UOTGHS_CTRL.TIMVALUE) fields, as shown in Table 39-4 on page 1064. Table 39-4. Customizing of OTG Timers TIMVALUE TIMPAGE 0b00 AWaitVrise Time-Out (see OTG Standard(1) Section 6.6.5.1) 0b01 VbBusPulsing Time-Out (see OTG Standard(1) Section5.3.4) 0b10 PdTmOutCnt Time-Out (see OTG Standard(1) Section 5.3.
In host mode, the UOTGHS_SR.VBUS bit follows an hysteresis based on Session_valid and Va_Vbus_valid: It is set when the voltage on the VBUS pad is higher than or equal to 4.4V. It is cleared when the voltage on the VBUS pad is lower than 1.4V. The VBus Transition interrupt (UOTGHS_SR.VBUSTI) bit is set on each transition of the UOTGHS_SR.VBUS bit. The UOTGHS_SR.VBUS bit is effective whether the UOTGHS is enabled or not. 39.5.1.
Figure 39-12. Device Mode States UOTGHS_CTRL.USBE = 0 | UOTGHS_SR.ID = 0 UOTGHS_CTRL.USBE = 0 | UOTGHS_SR.ID = 0 Reset Idle UOTGHS_CTRL.USBE = 1 & UOTGHS_SR.ID = 1 HW UOTGHS_HSTCTRL.RESET After a hardware reset, the UOTGHS device mode is in Reset state. In this state: the macro clock is stopped to minimize the power consumption (UOTGHS_CTRL.
39.5.2.4 Endpoint Reset An endpoint can be reset at any time by writing a one to the Endpoint x Reset (UOTGHS_DEVEPT.EPRSTx) bit. This is recommended before using an endpoint upon hardware reset or when a USB bus reset has been received.
See Section 39.5.1.6 for more details about DPRAM management. 39.5.2.6 Address Setup The USB device address is set up according to the USB protocol. After all kinds of resets, the USB device address is 0. The host starts a SETUP transaction with a SET_ADDRESS (addr) request. The user writes this address to the USB Address (UOTGHS_DEVCTRL.UADD) field, and writes a zero to the Address Enable (UOTGHS_DEVCTRL.ADDEN) bit, so the actual address is still 0.
When the controller sends the upstream resume, the Upstream Resume (UOTGHS_DEVISR.UPRSM) interrupt is set and UOTGHS_DEVISR.SUSP is cleared. UOTGHS_DEVCTRL.RMWKUP is cleared at the end of the upstream resume. If the controller detects a valid “End of Resume” signal from the host, the End of Resume (UOTGHS_DEVISR.EORSM) interrupt is set. 39.5.2.10 STALL Request For each endpoint, the STALL management is performed using: The STALL Request (UOTGHS_DEVEPTIMRx.
Control write Figure 39-14 on page 1070 shows a control write transaction. During the status stage, the controller will not necessarily send a NAK on the first IN token: if the user knows the exact number of descriptor bytes that must be read, it can then anticipate the status stage and send a zero-length packet after the next IN token, or it can read the bytes and wait for the NAKed IN Interrupt (UOTGHS_DEVEPTISRx.
Once the OUT status stage has been received, the UOTGHS waits for a SETUP request. The SETUP request has priority over any other request and has to be ACKed. This means that any other bit should be cleared and the FIFO reset when a SETUP is received. The user has to consider that the byte counter is reset when a zero-length OUT packet is received. 39.5.2.12 Management of IN Endpoints Overview IN packets are sent by the USB device controller upon IN requests from the host.
Figure 39-17. Example of an IN Endpoint with 2 Data Banks DATA (bank 0) IN ACK IN DATA (bank 1) ACK HW UOTGHS_DEVEPTISRx.TXINI UOTGHS_DEVEPTIMRx.FIFOCON SW write data to CPU BANK 0 SW SW write data to CPU BANK 1 SW SW write data to CPU BANK0 Detailed description The data is written, following the next flow: When the bank is empty, UOTGHS_DEVEPTISRx.TXINI and UOTGHS_DEVEPTIMRx.FIFOCON are set, which triggers a PEP_x interrupt if UOTGHS_DEVEPTIMRx.TXINE is one.
Figure 39-18. Abort Algorithm Endpoint Abort Disable the UOTGHS_DEVEPTISRx.TXINI interrupt. UOTGHS_DEVEPTIDRx.TXINEC = 1 UOTGHS_DEVEPTISRx.NBUSYBK == 0? Abort is based on the fact that no bank is busy, i.e., that nothing has to be sent No Yes UOTGHS_DEVEPT. EPRSTx = 1 Yes UOTGHS_DEVEPTIERx.KILLBKS = 1 Kill the last written bank. UOTGHS_DEVEPTIMRx.KILLBK == 1? Wait for the end of the procedure No Abort Done 39.5.2.13 Management of OUT Endpoints Overview OUT packets are sent by the host.
Figure 39-19. Example of an OUT Endpoint with one Data Bank DATA (bank 0) OUT NAK ACK DATA (bank 0) OUT ACK HW HW UOTGHS_DEVEPTISRx.RXOUTI SW SW read data from CPU BANK 0 UOTGHS_DEVEPTIMRx.FIFOCON read data from CPU BANK 0 SW Figure 39-20. Example of an OUT Endpoint with two Data Banks OUT DATA (bank 0) ACK OUT DATA (bank 1) HW UOTGHS_DEVEPTISRx.RXOUTI ACK HW SW SW UOTGHS_DEVEPTIMRx.
39.5.2.14 Underflow This error only exists for isochronous IN/OUT endpoints. It sets the Underflow Interrupt (UOTGHS_DEVEPTISRx.UNDERFI) bit, which triggers a PEP_x interrupt if the Underflow Interrupt Enable (UOTGHS_DEVEPTIMRx.UNDERFE) bit is one. An underflow can occur during the IN stage if the host attempts to read from an empty bank. A zero-length packet is then automatically sent by the UOTGHS.
39.5.2.19 Interrupts See the structure of the USB device interrupt system on Figure 39-6 on page 1059. There are two kinds of device interrupts: processing, i.e. their generation is part of the normal processing, and exception, i.e. errors (not related to CPU exceptions). Global interrupts The processing device global interrupts are: The Suspend (UOTGHS_DEVISR.SUSP) interrupt The Start of Frame (UOTGHS_DEVISR.SOF) interrupt with no frame number CRC error - the Frame Number CRC Error (UOTGHS_DEVFNUM.
DMA interrupts The processing device DMA interrupts are: The End of USB Transfer Status (UOTGHS_DEVDMASTATUSx.END_TR_ST) interrupt The End of Channel Buffer Status (UOTGHS_DEVDMASTATUSx.END_BF_ST) interrupt The Descriptor Loaded Status (UOTGHS_DEVDMASTATUSx.DESC_LDST) interrupt There is no exception device DMA interrupt. 39.5.2.20 Test Modes When written to one, the UOTGHS_DEVCTRL.
39.5.3.2 Power-On and Reset Figure 39-22 on page 1078 describes the UOTGHS host mode main states. Figure 39-22. Host Mode States Device Disconnection Macro off Clock stopped Idle Device Connection Device Disconnection Ready SOFE = 0 SOFE = 1 Suspend After a hardware reset, the UOTGHS host mode is in the Reset state. When the UOTGHS is enabled (UOTGHS_CTRL.USBE is one) in host mode (UOTGHS_SR.ID is zero), it goes to the Idle state.
39.5.3.5 Pipe Reset A pipe can be reset at any time by writing a one to the Pipe x Reset (UOTGHS_HSTPIP.PRSTx) bit. This is recommended before using a pipe upon hardware reset or when a USB bus reset has been sent. This resets: the internal state machine of this pipe, the receive and transmit bank FIFO counters, all the registers of this pipe (UOTGHS_HSTPIPCFGx, UOTGHS_HSTPIPISRx, UOTGHS_HSTPIPIMRx), except its configuration (UOTGHS_HSTPIPCFGx.ALLOC, UOTGHS_HSTPIPCFGx.PBK, UOTGHS_HSTPIPCFGx.
See Section 39.5.1.6 for more details about DPRAM management. Once the pipe is correctly configured (UOTGHS_HSTPIPISRx.CFGOK is one), only the UOTGHS_HSTPIPCFGx.PTOKEN and UOTGHS_HSTPIPCFGx.INTFRQ fields can be written by software. UOTGHS_HSTPIPCFGx.INTFRQ is meaningless for non-interrupt pipes. When starting an enumeration, the user gets the device descriptor by sending a GET_DESCRIPTOR USB request.
When the host requires data from the device, the user has to select beforehand the IN request mode with the IN Request Mode bit in the Pipe x IN Request register (UOTGHS_HSTPIPINRQx.INMODE): When UOTGHS_HSTPIPINRQx.INMODE is written to zero, the UOTGHS will perform (INRQ + 1) IN requests before freezing the pipe. When UOTGHS_HSTPIPINRQx.INMODE is written to one, the UOTGHS will perform IN requests endlessly when the pipe is not frozen by the user.
39.5.3.11 Management of OUT Pipes OUT packets are sent by the host. All data which acknowledges or not the bank can be written when it is full. The pipe must be configured and unfrozen first. The Transmitted OUT Data Interrupt (UOTGHS_HSTPIPISRx.TXOUTI) bit is set at the same time as UOTGHS_HSTPIPIMRx.FIFOCON when the current bank is free. This triggers a PEP_x interrupt if the Transmitted OUT Data Interrupt Enable (UOTGHS_HSTPIPIMRx.TXOUTE) bit is one. UOTGHS_HSTPIPISRx.
Figure 39-28. Example of an OUT Pipe with two Data Banks and a Bank Switching Delay OUT DATA (bank 0) ACK OUT DATA (bank 1) ACK HW UOTGHS_HSTPIPISRx.TXOUTI UOTGHS_HSTPIPIMRx.FIFOCON SW SW write data to CPU BANK 0 SW SW write data to CPU BANK 1 SW write data to CPU BANK0 39.5.3.12 CRC Error This error exists only for isochronous IN pipes. It sets the CRC Error Interrupt (UOTGHS_HSTPIPISRx.
The exception host pipe interrupts are: The Underflow Interrupt (UOTGHS_HSTPIPISRx.UNDERFI) The Pipe Error Interrupt (UOTGHS_HSTPIPISRx.PERRI) The NAKed Interrupt (UOTGHS_HSTPIPISRx.NAKEDI) The Overflow Interrupt (UOTGHS_HSTPIPISRx.OVERFI) The Received STALLed Interrupt (UOTGHS_HSTPIPISRx.RXSTALLDI) The CRC Error Interrupt (UOTGHS_HSTPIPISRx.CRCERRI) DMA interrupts The processing host DMA interrupts are: The End of USB Transfer Status (UOTGHS_HSTDMASTATUSx.
Figure 39-29. Example of DMA Chained List Transfer Descriptor USB DMA Channel X Registers (Current Transfer Descriptor) Next Descriptor Address Next Descriptor Address AHB Address Transfer Descriptor Control Next Descriptor Address AHB Address Control AHB Address Transfer Descriptor Control Next Descriptor Address AHB Address Status Control NULL Memory Area Data Buffer 1 Data Buffer 2 Data Buffer 3 39.5.
39.6 USB On-The-Go Interface (UOTGHS) User Interface Table 39-5.
Table 39-5.
39.6.1 USB General Registers 39.6.1.1 General Control Register Name: UOTGHS_CTRL Address: 0x400AC800 Access: Read-write 31 – 23 – 15 USBE 7 STOE 30 – 22 UNLOCK 14 FRZCLK 6 HNPERRE 29 – 21 28 – 20 TIMPAGE 13 12 VBUSPO OTGPADE 5 4 ROLEEXE BCERRE 27 – 19 – 11 HNPREQ 3 VBERRE 26 – 18 – 10 SRPREQ 2 SRPE 25 24 UIMOD UIDE 17 16 TIMVALUE 9 8 SRPSEL VBUSHWC 1 0 VBUSTE IDTE • UIMOD: UOTGHS Mode This bit has no effect when UIDE is one (UOTGID input pin activated).
• FRZCLK: Freeze USB Clock 0: The clock inputs are enabled. 1: The clock inputs are disabled (the resume detection is still active).This reduces the power consumption. Unless explicitly stated, all registers then become read-only. This bit can be written even if USBE is zero. Disabling the UOTGHS (by writing a zero to the USBE bit) does not reset this bit, but this freezes the clock inputs whatever its value. • VBUSPO: VBus Polarity Off 0: The UOTGVBOF output signal is in its default mode (active high).
• STOE: Suspend Time-Out Interrupt Enable 0: The Suspend Time-Out Interrupt (UOTGHS_SR.STOI) is disabled. 1: The Suspend Time-Out Interrupt (UOTGHS_SR.STOI) is enabled. • HNPERRE: HNP Error Interrupt Enable 0: The HNP Error Interrupt (UOTGHS_SR.HNPERRI) is disabled. 1: The HNP Error Interrupt (UOTGHS_SR.HNPERRI) is enabled. • ROLEEXE: Role Exchange Interrupt Enable 0: The Role Exchange Interrupt (UOTGHS_SR.ROLEEXI) is disabled. 1: The Role Exchange Interrupt (UOTGHS_SR.ROLEEXI) is enabled.
39.6.1.2 General Status Register Name: UOTGHS_SR Address: 0x400AC804 Access: Read-only 31 – 23 – 15 – 7 STOI 30 – 22 – 14 CLKUSABLE 6 HNPERRI 29 – 21 – 13 28 – 20 – 12 SPEED 5 ROLEEXI 4 BCERRI 27 – 19 – 11 VBUS 3 VBERRI 26 – 18 – 10 ID 2 SRPI 25 – 17 – 9 VBUSRQ 1 VBUSTI 24 – 16 – 8 – 0 IDTI • CLKUSABLE: UTMI Clock Usable This bit is set when the UTMI 30 MHz is usable. This bit is cleared when the UTMI 30 MHz is not usable.
• STOI: Suspend Time-Out Interrupt This bit is set when a time-out error (more than 200ms) has been detected after a suspend. This triggers a USB interrupt if UOTGHS_CTRL.STOE is one. This bit is cleared when the UOTGHS_SCR.STOIC bit is written to one. This bit shall only be used in host mode. • HNPERRI: HNP Error Interrupt This bit is set when an error has been detected during a HNP negotiation. This triggers a USB interrupt if UOTGHS_CTRL.HNPERRE is one. This bit is cleared when the UOTGHS_SCR.
• IDTI: ID Transition Interrupt This bit is set when a transition (high to low, low to high) has been detected on the UOTGID input pin. This triggers a USB interrupt if UOTGHS_CTRL.IDTE is one. This bit is cleared when the UOTGHS_SCR.IDTIC bit is written to one. This interrupt is generated even if the clock is frozen by the UOTGHS_CTRL.FRZCLK bit.
39.6.1.3 General Status Clear Register Name: UOTGHS_SCR Address: 0x400AC808 Access: Write-only 31 – 23 – 15 – 7 STOIC 30 – 22 – 14 – 6 HNPERRIC 29 – 21 – 13 – 5 ROLEEXIC 28 – 20 – 12 – 4 BCERRIC • VBUSRQC: VBus Request Clear Writing a one will clear VBUSRQ bit in UOTGHS_SR. Writing a zero to this bit has no effect. This bit always read as zero. • STOIC: Suspend Time-Out Interrupt Clear Writing a one will clear STOI bit in UOTGHS_SR. Writing a zero to this bit has no effect.
• SRPIC: SRP Interrupt Clear Writing a one will clear SRPI bit in UOTGHS_SR. Writing a zero to this bit has no effect. This bit always read as zero. • VBUSTIC: VBus Transition Interrupt Clear Writing a one will clear VBUSTI bit in UOTGHS_SR. Writing a zero to this bit has no effect. This bit always read as zero. • IDTIC: ID Transition Interrupt Clear Writing a one will clear IDTI bit in UOTGHS_SR. Writing a zero to this bit has no effect. This bit always read as zero.
39.6.1.4 General Status Set Register Name: UOTGHS_SFR Address: 0x400AC80C Access: Write-only 31 – 23 – 15 – 7 STOIS 30 – 22 – 14 – 6 HNPERRIS 29 – 21 – 13 – 5 ROLEEXIS 28 – 20 – 12 – 4 BCERRIS 27 – 19 – 11 – 3 VBERRIS 26 – 18 – 10 – 2 SRPIS 25 – 17 – 9 VBUSRQS 1 VBUSTIS • VBUSRQS: VBus Request Set Writing a one will set VBUSRQ bit in UOTGHS_SR. Writing a zero to this bit has no effect. This bit always read as zero.
• SRPIS: SRP Interrupt Set Writing a one will set SRPI bit in UOTGHS_SR, which may be useful for test or debug purposes. Writing a zero to this bit has no effect. This bit always read as zero. • VBUSTIS: VBus Transition Interrupt Set Writing a one will set VBUSTI bit in UOTGHS_SR, which may be useful for test or debug purposes. Writing a zero to this bit has no effect. This bit always read as zero.
39.6.1.5 General Finite State Machine Register Name: UOTGHS_FSM Address: 0x400AC82C Access: Read-only 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 – 0 DRDSTATE • DRDSTATE This field indicates the state of the UOTGHS. Refer to the OTG specification for more details.
39.6.2 USB Device Registers 39.6.2.1 Device General Control Register Name: UOTGHS_DEVCTRL Address: 0x400AC000 Access: Read-write 31 – 23 – 15 TSTPCKT 7 ADDEN 30 – 22 – 14 TSTK 6 29 – 21 – 13 TSTJ 5 28 – 20 – 12 LS 4 27 – 19 – 11 26 – 18 – 10 SPDCONF 3 UADD 2 25 – 17 – 9 RMWKUP 1 24 – 16 OPMODE2 8 DETACH 0 • OPMODE2: Specific Operational mode 0: The UTMI transceiver is in normal operation mode.
• RMWKUP: Remote Wake-Up Writing a one to this bit will send an upstream resume to the host for a remote wake-up. Writing a zero to this bit has no effect. This bit is cleared when the UOTGHS receives a USB reset or once the upstream resume has been sent. • DETACH: Detach Writing a one to this bit will physically detach the device (disconnect internal pull-up resistor from D+ and D-). Writing a zero to this bit will reconnect the device.
39.6.2.2 Device Global Interrupt Status Register Name: UOTGHS_DEVISR Address: 0x400AC004 Access: Read-only 31 – 23 – 15 PEP_3 7 – 30 DMA_6 22 – 14 PEP_2 6 UPRSM 29 DMA_5 21 PEP_9 13 PEP_1 5 EORSM 28 DMA_4 20 PEP_8 12 PEP_0 4 WAKEUP 27 DMA_3 19 PEP_7 11 – 3 EORST 26 DMA_2 18 PEP_6 10 – 2 SOF 25 DMA_1 17 PEP_5 9 – 1 MSOF 24 – 16 PEP_4 8 – 0 SUSP • DMA_x: DMA Channel x Interrupt This bit is set when an interrupt is triggered by the DMA channel x. This triggers a USB interrupt if DMA_x is one.
• SOF: Start of Frame Interrupt This bit is set when a USB “Start of Frame” PID (SOF) has been detected (every 1 ms). This triggers a USB interrupt if SOFE is one. The FNUM field is updated. In High-speed mode, the MFNUM field is cleared. This bit is cleared when the UOTGHS_DEVICR.SOFC bit is written to one to acknowledge the interrupt. • MSOF: Micro Start of Frame Interrupt This bit is set in High-speed mode when a USB “Micro Start of Frame” PID (SOF) has been detected (every 125 us).
39.6.2.3 Device Global Interrupt Clear Register Name: UOTGHS_DEVICR Address: 0x400AC008 Access: Write-only 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 UPRSMC 29 – 21 – 13 – 5 EORSMC 28 – 20 – 12 – 4 WAKEUPC 27 – 19 – 11 – 3 EORSTC 26 – 18 – 10 – 2 SOFC 25 – 17 – 9 – 1 MSOFC 24 – 16 – 8 – 0 SUSPC • UPRSMC: Upstream Resume Interrupt Clear Writing a one to this bit will clear UPRSM bit in UOTGHS_DEVISR. Writing a zero to this bit has no effect. This bit always reads as zero.
• SUSPC: Suspend Interrupt Clear Writing a one to this bit will clear SUSP bit in UOTGHS_DEVISR. Writing a zero to this bit has no effect. This bit always reads as zero.
39.6.2.4 Device Global Interrupt Set Register Name: UOTGHS_DEVIFR Address: 0x400AC00C Access: Write-only 31 – 23 – 15 – 7 – 30 DMA_6 22 – 14 – 6 UPRSMS 29 DMA_5 21 – 13 – 5 EORSMS 28 DMA_4 20 – 12 – 4 WAKEUPS 27 DMA_3 19 – 11 – 3 EORSTS 26 DMA_2 18 – 10 – 2 SOFS 25 DMA_1 17 – 9 – 1 MSOFS 24 – 16 – 8 – 0 SUSPS • DMA_x: DMA Channel x Interrupt Set Writing a one to this bit will set the corresponding bit in UOTGHS_DEVISR, which may be useful for test or debug purposes.
• MSOFS: Micro Start of Frame Interrupt Set Writing a one to this bit will set MSOF bit in UOTGHS_DEVISR, which may be useful for test or debug purposes. Writing a zero to this bit has no effect. This bit always reads as zero. • SUSPS: Suspend Interrupt Set Writing a one to this bit will set SUSP bit in UOTGHS_DEVISR, which may be useful for test or debug purposes. Writing a zero to this bit has no effect. This bit always reads as zero.
39.6.2.5 Device Global Interrupt Mask Register Name: UOTGHS_DEVIMR Address: 0x400AC010 Access: Read-only 31 – 23 – 15 PEP_3 7 – 30 DMA_6 22 – 14 PEP_2 6 UPRSME 29 DMA_5 21 PEP_9 13 PEP_1 5 EORSME 28 DMA_4 20 PEP_8 12 PEP_0 4 WAKEUPE 27 DMA_3 19 PEP_7 11 – 3 EORSTE 26 DMA_2 18 PEP_6 10 – 2 SOFE 25 DMA_1 17 PEP_5 9 – 1 MSOFE 24 – 16 PEP_4 8 – 0 SUSPE • DMA_x: DMA Channel x Interrupt Mask 0: The interrupt is disabled. 1: The interrupt is enabled.
• EORSTE: End of Reset Interrupt Mask 0: The interrupt is disabled. 1: The interrupt is enabled. This bit is set when EORSTES bit in UOTGHS_DEVIER is written to one. This bit is cleared when EORSTEC bit in UOTGHS_DEVIDR is written to one. • SOFE: Start of Frame Interrupt Mask 0: The interrupt is disabled. 1: The interrupt is enabled. This bit is set when SOFES bit in UOTGHS_DEVIER is written to one. This bit is cleared when SOFEC bit in UOTGHS_DEVIDR is written to one.
39.6.2.6 Device Global Interrupt Disable Register Name: UOTGHS_DEVIDR Address: 0x400AC014 Access: Write-only 31 – 23 – 15 PEP_3 7 – 30 DMA_6 22 – 14 PEP_2 6 UPRSMEC 29 DMA_5 21 PEP_9 13 PEP_1 5 EORSMEC 28 DMA_4 20 PEP_8 12 PEP_0 4 WAKEUPEC 27 DMA_3 19 PEP_7 11 – 3 EORSTEC 26 DMA_2 18 PEP_6 10 – 2 SOFEC 25 DMA_1 17 PEP_5 9 – 1 MSOFEC 24 – 16 PEP_4 8 – 0 SUSPEC • DMA_x: DMA Channel x Interrupt Disable Writing a one to this bit will clear the corresponding bit in UOTGHS_DEVIMR.
• SOFEC: Start of Frame Interrupt Disable Writing a one to this bit will clear SOFE bit in UOTGHS_DEVIMR. Writing a zero to this bit has no effect. This bit always reads as zero. • MSOFEC: Micro Start of Frame Interrupt Disable Writing a one to this bit will clear MSOFE bit in UOTGHS_DEVIMR. Writing a zero to this bit has no effect. This bit always reads as zero. • SUSPEC: Suspend Interrupt Disable Writing a one to this bit will clear SUSPE bit in UOTGHS_DEVIMR. Writing a zero to this bit has no effect.
39.6.2.7 Device Global Interrupt Enable Register Name: UOTGHS_DEVIER Address: 0x400AC018 Access: Write-only 31 – 23 – 15 PEP_3 7 – 30 DMA_6 22 – 14 PEP_2 6 UPRSMES 29 DMA_5 21 PEP_9 13 PEP_1 5 EORSMES 28 DMA_4 20 PEP_8 12 PEP_0 4 WAKEUPES 27 DMA_3 19 PEP_7 11 – 3 EORSTES 26 DMA_2 18 PEP_6 10 – 2 SOFES 25 DMA_1 17 PEP_5 9 – 1 MSOFES 24 – 16 PEP_4 8 – 0 SUSPES • DMA_x: DMA Channel x Interrupt Enable Writing a one to this bit will set the corresponding bit in UOTGHS_DEVIMR.
• SOFES: Start of Frame Interrupt Enable Writing a one to this bit will set SOFE bit in UOTGHS_DEVIMR. Writing a zero to this bit has no effect. This bit always reads as zero. • MSOFES: Micro Start of Frame Interrupt Enable Writing a one to this bit will set MSOFE bit in UOTGHS_DEVIMR. Writing a zero to this bit has no effect. This bit always reads as zero. • SUSPES: Suspend Interrupt Enable Writing a one to this bit will set SUSPE bit in UOTGHS_DEVIMR. Writing a zero to this bit has no effect.
39.6.2.
39.6.2.9 Device Frame Number Register Name: UOTGHS_DEVFNUM Address: 0x400AC020 Access: Read-only 31 – 23 – 15 FNCERR 7 30 – 22 – 14 – 6 29 – 21 – 13 28 – 20 – 12 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 2 1 MFNUM 0 FNUM 5 FNUM 4 3 • FNCERR: Frame Number CRC Error This bit is set when a corrupted frame number (or micro-frame number) is received. This bit and the SOF (or MSOF) interrupt bit are updated at the same time. This bit is cleared upon receiving a USB reset.
39.6.2.10 Device Endpoint x Configuration Register Name: UOTGHS_DEVEPTCFGx [x=0..
• EPSIZE: Endpoint Size This field shall be written to select the size of each endpoint bank: Value Name Description 0 8_BYTE 8 bytes 1 16_BYTE 16 bytes 2 32_BYTE 32 bytes 3 64_BYTE 64 bytes 4 128_BYTE 128 bytes 5 256_BYTE 256 bytes 6 512_BYTE 512 bytes 7 1024_BYTE 1024 bytes This field is cleared upon receiving a USB reset (except for the endpoint 0).
39.6.2.11 Device Endpoint x Status Register Name: UOTGHS_DEVEPTISRx [x=0..9] Address: 0x400AC130 Access: Read-only 0x0100 31 30 29 28 – 27 26 25 24 BYCT 23 22 21 20 BYCT 15 14 13 CURRBK 12 NBUSYBK 7 6 SHORTPACKET STALLEDI/ CRCERRI 19 18 17 16 – CFGOK CTRLDIR RWALL 11 10 9 – ERRORTRANS 8 DTSEQ 5 4 3 2 1 0 OVERFI NAKINI/ HBISOFLUSHI NAKOUTI/ HBISOINERRI RXSTPI/ UNDERFI RXOUTI TXINI • BYCT: Byte Count This field is set with the byte count of the FIFO.
• CURRBK: Current Bank This bit is set for non-control endpoints, to indicate the current bank: Value Name Description 0 BANK0 Current bank is bank0 1 BANK1 Current bank is bank1 2 BANK2 Current bank is bank2 3 Reserved This field may be updated one clock cycle after the RWALL bit changes, so the user should not poll this field as an interrupt bit.
• DTSEQ: Data Toggle Sequence This field is set to indicate the PID of the current bank: Value Name Description 0 DATA0 Data0 toggle sequence 1 DATA1 Data1 toggle sequence 2 DATA2 Data2 toggle sequence (for high-bandwidth isochronous endpoint) 3 MDATA MData toggle sequence (for high-bandwidth isochronous endpoint) For IN transfers, it indicates the data toggle sequence that will be used for the next packet to be sent. This is not relative to the current bank.
• NAKINI: NAKed IN Interrupt This bit is set when a NAK handshake has been sent in response to an IN request from the host. This triggers a PEP_x interrupt if NAKINE is one. This bit is cleared when the NAKINIC bit is written to one. This will acknowledge the interrupt.
Shall be cleared for isochronous, bulk and, interrupt OUT endpoints, by writing a one to the RXOUTIC bit. This will acknowledge the interrupt, what has no effect on the endpoint FIFO. The user then reads from the FIFO and clears the UOTGHS_DEVEPTIMRx.FIFOCON bit to free the bank. If the OUT endpoint is composed of multiple banks, this also switches to the next bank. The UOTGHS_DEVEPTISRx.RXOUTI and UOTGHS_DEVEPTIMRx.FIFOCON bits are set/cleared in accordance with the status of the next bank.
39.6.2.12 Device Endpoint x Clear Register Name: UOTGHS_DEVEPTICRx [x=0..
• NAKOUTIC: NAKed OUT Interrupt Clear Writing a one to this bit will clear NAKOUTI in UOTGHS_DEVEPTISRx. Writing a zero to this bit has no effect. This bit always reads as zero. • HBISOINERRIC: High bandwidth isochronous IN Underflow Error Interrupt Clear Writing a one to this bit will clear HBISOINERRI in UOTGHS_DEVEPTISRx. Writing a zero to this bit has no effect. This bit always reads as zero. • RXSTPIC: Received SETUP Interrupt Clear Writing a one to this bit will clear RXSTPI in UOTGHS_DEVEPTISRx.
39.6.2.13 Device Endpoint x Set Register Name: UOTGHS_DEVEPTIFRx [x=0..
• HBISOFLUSHIS: High Bandwidth Isochronous IN Flush Interrupt Set Writing a one to this bit will set HBISOFLUSHI in UOTGHS_DEVEPTISRx, which may be useful for test or debug purposes. Writing a zero to this bit has no effect. This bit always reads as zero. • NAKOUTIS: NAKed OUT Interrupt Set Writing a one to this bit will set NAKOUTI in UOTGHS_DEVEPTISRx, which may be useful for test or debug purposes. Writing a zero to this bit has no effect. This bit always reads as zero.
39.6.2.14 Device Endpoint x Mask Register Name: UOTGHS_DEVEPTIMRx [x=0..
• FIFOCON: FIFO Control For control endpoints: The FIFOCON and RWALL bits are irrelevant. The software shall therefore never use them on these endpoints. When read, their value is always 0. For IN endpoints: This bit is set when the current bank is free, at the same time as UOTGHS_DEVEPTISRx.TXINI. This bit is cleared (by writing a one to UOTGHS_DEVEPTIDRx.FIFOCONC bit) to send the FIFO data and to switch to the next bank.
• MDATAE: MData Interrupt This bit is set when UOTGHS_DEVEPTIERx.MDATAES bit is written to one. This will enable the Multiple DATA interrupt. (see DTSEQ bits) This bit is cleared when UOTGHS_DEVEPTIDRx.MDATAEC bit is written to one. This will disable the Multiple DATA interrupt.
• NAKOUTE: NAKed OUT Interrupt This bit is set when UOTGHS_DEVEPTIERx.NAKOUTES bit is written to one. This will enable the NAKed OUT interrupt (UOTGHS_DEVEPTISRx.NAKOUTI). This bit is cleared when UOTGHS_DEVEPTIDRx.NAKOUTEC bit is written to one. This will disable the NAKed OUT interrupt (UOTGHS_DEVEPTISRx.NAKOUTI). • HBISOINERRE: High Bandwidth Isochronous IN Error Interrupt This bit is set when UOTGHS_DEVEPTIERx.HBISOINERRES bit is written to one. This will enable the HBISOINERRI interrupt.
39.6.2.15 Device Endpoint x Disable Register Name: UOTGHS_DEVEPTIDRx [x=0..
• DATAXEC: DataX Interrupt Clear Writing a one to this bit will clear DATAXE bit in UOTGHS_DEVEPTIMRx. Writing a zero to this bit has no effect. This bit always reads as zero. • MDATEC: MData Interrupt Clear Writing a one to this bit will clear MDATE bit in UOTGHS_DEVEPTIMRx. Writing a zero to this bit has no effect. This bit always reads as zero. • SHORTPACKETEC: Shortpacket Interrupt Clear Writing a one to this bit will clear SHORTPACKETE bit in UOTGHS_DEVEPTIMRx. Writing a zero to this bit has no effect.
• HBISOINERREC: High Bandwidth Isochronous IN Error Interrupt Clear Writing a one to this bit will clear HBISOINERRE bit in UOTGHS_DEVEPTIMRx. Writing a zero to this bit has no effect. This bit always reads as zero. • RXSTPEC: Received SETUP Interrupt Clear Writing a one to this bit will clear RXSTPE bit in UOTGHS_DEVEPTIMRx. Writing a zero to this bit has no effect. This bit always reads as zero. • UNDERFEC: Underflow Interrupt Clear Writing a one to this bit will clear UNDERFE bit in UOTGHS_DEVEPTIMRx.
39.6.2.16 Device Endpoint x Enable Register Name: UOTGHS_DEVEPTIERx [x=0..
• NBUSYBKES: Number of Busy Banks Interrupt Enable Writing a one to this bit will set NBUSYBKE bit in UOTGHS_DEVEPTIMRx. Writing a zero to this bit has no effect. This bit always reads as zero. • ERRORTRANSES: Transaction Error Interrupt Enable Writing a one to this bit will set ERRORTRANSE bit in UOTGHS_DEVEPTIMRx. Writing a zero to this bit has no effect. This bit always reads as zero. • DATAXES: DataX Interrupt Enable Writing a one to this bit will set DATAXE bit in UOTGHS_DEVEPTIMRx.
• HBISOFLUSHES: High Bandwidth Isochronous IN Flush Interrupt Enable Writing a one to this bit will set HBISOFLUSHE bit in UOTGHS_DEVEPTIMRx. Writing a zero to this bit has no effect. This bit always reads as zero. • NAKOUTES: NAKed OUT Interrupt Enable Writing a one to this bit will set NAKOUTE bit in UOTGHS_DEVEPTIMRx. Writing a zero to this bit has no effect. This bit always reads as zero.
39.6.2.17 Device DMA Channel x Next Descriptor Address Register Name: UOTGHS_DEVDMANXTDSCx [x=1..6] Address: 0x400AC310 [1], 0x400AC320 [2], 0x400AC330 [3], 0x400AC340 [4], 0x400AC350 [5], 0x400AC360 [6], 0x400AC370 [7] Access: Read-write 31 30 29 23 22 21 15 14 13 7 6 5 28 27 NXT_DSC_ADD 20 19 NXT_DSC_ADD 12 11 NXT_DSC_ADD 4 3 NXT_DSC_ADD 26 25 24 18 17 16 10 9 8 2 1 0 • NXT_DSC_ADD: Next Descriptor Address This field points to the next channel descriptor to be processed.
39.6.2.18 Device DMA Channel x Address Register Name: UOTGHS_DEVDMAADDRESSx [x=1..6] Address: 0x400AC314 [1], 0x400AC324 [2], 0x400AC334 [3], 0x400AC344 [4], 0x400AC354 [5], 0x400AC364 [6], 0x400AC374 [7] Access: Read-write 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 BUFF_ADD BUFF_ADD 15 14 13 12 7 6 5 4 BUFF_ADD BUFF_ADD • BUFF_ADD: Buffer Address This field determines the AHB bus starting address of a DMA channel transfer.
39.6.2.19 Device DMA Channel x Control Register Name: UOTGHS_DEVDMACONTROLx [x=1..
• END_TR_EN: End of Transfer Enable Control Used for OUT transfers only. 0: USB end of transfer is ignored. 1: UOTGHS device can put an end to the current buffer transfer. When set, a BULK or INTERRUPT short packet or the last packet of an ISOCHRONOUS (micro) frame (DATAX) will close the current buffer and the UOTGHS_DEVDMASTATUSx.END_TR_ST flag will be raised. This is intended for UOTGHS non-prenegotiated end of transfer (BULK or INTERRUPT) or ISOCHRONOUS microframe data buffer closure.
39.6.2.20 Device DMA Channel x Status Register Name: UOTGHS_DEVDMASTATUSx [x=1..
• DESC_LDST: Descriptor Loaded Status 0: cleared automatically when read by software. 1: set by hardware when a descriptor has been loaded from the system bus. Valid until the CHANN_ENB flag is cleared at the end of the next buffer transfer. • BUFF_COUNT: Buffer Byte Count This field determines the current number of bytes still to be transferred for this buffer. This field is decremented from the AHB source bus access byte width at the end of this bus address phase.
39.6.3 USB Host Registers 39.6.3.1 Host General Control Register Name: UOTGHS_HSTCTRL Address: 0x400AC400 Access: Read-write 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 28 – 20 – 12 SPDCONF 5 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 RESUME 2 – 25 – 17 – 9 RESET 1 – 24 – 16 – 8 SOFE 0 – • SPDCONF: Mode Configuration This field contains the host speed capability:.
39.6.3.2 Host Global Interrupt Status Register Name: UOTGHS_HSTISR Address: 0x400AC404 Access: Read-only 31 – 23 – 15 PEP_7 7 – 30 DMA_6 22 – 14 PEP_6 6 HWUPI 29 DMA_5 21 – 13 PEP_5 5 HSOFI 28 DMA_4 20 – 12 PEP_4 4 RXRSMI 27 DMA_3 19 – 11 PEP_3 3 RSMEDI 26 DMA_2 18 – 10 PEP_2 2 RSTI 25 DMA_1 17 PEP_9 9 PEP_1 1 DDISCI 24 – 16 PEP_8 8 PEP_0 0 DCONNI • DMA_x: DMA Channel x Interrupt This bit is set when an interrupt is triggered by the DMA channel x.
• RSTI: USB Reset Sent Interrupt This bit is set when a USB Reset has been sent to the device. This bit is cleared when UOTGHS_HSTICR.RSTIC bit is written to one. • DDISCI: Device Disconnection Interrupt This bit is set when the device has been removed from the USB bus. This bit is cleared when UOTGHS_HSTICR.DDISCIC bit is written to one. • DCONNI: Device Connection Interrupt This bit is set when a new device has been connected to the USB bus. This bit is cleared when UOTGHS_HSTICR.
39.6.3.3 Host Global Interrupt Clear Register Name: UOTGHS_HSTICR Address: 0x400AC408 Access: Write-only 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 HWUPIC 29 – 21 – 13 – 5 HSOFIC 28 – 20 – 12 – 4 RXRSMIC 27 – 19 – 11 – 3 RSMEDIC 26 – 18 – 10 – 2 RSTIC 25 – 17 – 9 – 1 DDISCIC 24 – 16 – 8 – 0 DCONNIC • HWUPIC: Host Wake-Up Interrupt Clear Writing a one to this bit will clear HWUPI bit in UOTGHS_HSTISR. Writing a zero to a bit in this register has no effect. This bit always reads as zero.
• DCONNIC: Device Connection Interrupt Clear Writing a one to this bit will clear DCONNI bit in UOTGHS_HSTISR. Writing a zero to a bit in this register has no effect. This bit always reads as zero.
39.6.3.4 Host Global Interrupt Set Register Name: UOTGHS_HSTIFR Address: 0x400AC40C Access: Write-only 31 – 23 – 15 – 7 – 30 DMA_6 22 – 14 – 6 HWUPIS 29 DMA_5 21 – 13 – 5 HSOFIS 28 DMA_4 20 – 12 – 4 RXRSMIS 27 DMA_3 19 – 11 – 3 RSMEDIS 26 DMA_2 18 – 10 – 2 RSTIS 25 DMA_1 17 – 9 – 1 DDISCIS 24 – 16 – 8 – 0 DCONNIS • DMA_x: DMA Channel x Interrupt Set Writing a one to this bit will set the corresponding bit in UOTGHS_HSTISR, which may be useful for test or debug purposes.
• DDISCIS: Device Disconnection Interrupt Set Writing a one to this bit will set DDISCI bit in UOTGHS_HSTISR, which may be useful for test or debug purposes. Writing a zero to this bit has no effect. This bit always reads as zero. • DCONNIS: Device Connection Interrupt Set Writing a one to this bit will set DCONNI bit in UOTGHS_HSTISR, which may be useful for test or debug purposes. Writing a zero to this bit has no effect. This bit always reads as zero.
39.6.3.5 Host Global Interrupt Mask Register Name: UOTGHS_HSTIMR Address: 0x400AC410 Access: Read-only 31 – 23 – 15 PEP_7 7 – 30 DMA_6 22 – 14 PEP_6 6 HWUPIE 29 DMA_5 21 – 13 PEP_5 5 HSOFIE 28 DMA_4 20 – 12 PEP_4 4 RXRSMIE 27 DMA_3 19 – 11 PEP_3 3 RSMEDIE 26 DMA_2 18 – 10 PEP_2 2 RSTIE 25 DMA_1 17 PEP_9 9 PEP_1 1 DDISCIE 24 – 16 PEP_8 8 PEP_0 0 DCONNIE • DMA_x: DMA Channel x Interrupt Enable This bit is set when the corresponding bit in UOTGHS_HSTIER is written to one.
• RSTIE: USB Reset Sent Interrupt Enable This bit is set when UOTGHS_HSTIER.RSTIES bit is written to one. This will enable the USB Reset Sent interrupt (UOTGHS_HSTISR.RSTI). This bit is cleared when UOTGHS_HSTIDR.RSTIEC bit is written to one. This will disable the USB Reset Sent interrupt (UOTGHS_HSTISR.RSTI). • DDISCIE: Device Disconnection Interrupt Enable This bit is set when UOTGHS_HSTIER.DDISCIES bit is written to one. This will enable the Device Disconnection interrupt (UOTGHS_HSTISR.DDISCI).
39.6.3.6 Host Global Interrupt Disable Register Name: UOTGHS_HSTIDR Address: 0x400AC414 Access: Write-only 31 – 23 – 15 PEP_7 7 – 30 DMA_6 22 – 14 PEP_6 6 HWUPIEC 29 DMA_5 21 – 13 PEP_5 5 HSOFIEC 28 DMA_4 20 – 12 PEP_4 4 RXRSMIEC 27 DMA_3 19 – 11 PEP_3 3 RSMEDIEC 26 DMA_2 18 – 10 PEP_2 2 RSTIEC 25 DMA_1 17 PEP_9 9 PEP_1 1 DDISCIEC 24 – 16 PEP_8 8 PEP_0 0 DCONNIEC • DMA_x: DMA Channel x Interrupt Disable Writing a one to this bit will clear the corresponding bit in UOTGHS_HSTIMR.
• RSTIEC: USB Reset Sent Interrupt Disable Writing a one to this bit will clear RSTIE bit in UOTGHS_HSTIMR. Writing a zero to this bit has no effect. This bit always reads as zero. • DDISCIEC: Device Disconnection Interrupt Disable Writing a one to this bit will clear DDISCIE bit in UOTGHS_HSTIMR. Writing a zero to this bit has no effect. This bit always reads as zero. • DCONNIEC: Device Connection Interrupt Disable Writing a one to this bit will clear DCONNIE bit in UOTGHS_HSTIMR.
39.6.3.7 Host Global Interrupt Enable Register Name: UOTGHS_HSTIER Address: 0x400AC418 Access: Write-only 31 – 23 – 15 PEP_7 7 – 30 DMA_6 22 – 14 PEP_6 6 HWUPIES 29 DMA_5 21 – 13 PEP_5 5 HSOFIES 28 DMA_4 20 – 12 PEP_4 4 RXRSMIES 27 DMA_3 19 – 11 PEP_3 3 RSMEDIES 26 DMA_2 18 – 10 PEP_2 2 RSTIES 25 DMA_1 17 PEP_9 9 PEP_1 1 DDISCIES 24 – 16 PEP_8 8 PEP_0 0 DCONNIES • DMA_x: DMA Channel x Interrupt Enable Writing a one to this bit will set the corresponding bit in UOTGHS_HSTISR.
• RSTIES: USB Reset Sent Interrupt Enable Writing a one to this bit will set RSTI bit in UOTGHS_HSTISR. Writing a zero to this bit has no effect. This bit always reads as zero. • DDISCIES: Device Disconnection Interrupt Enable Writing a one to this bit will set DDISCI bit in UOTGHS_HSTISR. Writing a zero to this bit has no effect. This bit always reads as zero. • DCONNIES: Device Connection Interrupt Enable Writing a one to this bit will set DCONNI bit in UOTGHS_HSTISR.
39.6.3.8 Host Frame Number Register Name: UOTGHS_HSTFNUM Address: 0x400AC420 Access: Read-write 31 – 23 30 – 22 29 – 21 28 – 20 15 – 7 14 – 6 13 12 27 – 19 26 – 18 25 – 17 24 – 16 10 9 8 2 1 MFNUM 0 FLENHIGH 11 FNUM 5 FNUM 4 3 • FLENHIGH: Frame Length In High speed mode, this field contains the 8 high-order bits of the 16-bit internal frame counter (at 30MHz, counter length is 3750 to ensure a SOF generation every 125 us).
39.6.3.9 Host Address 1 Register Name: UOTGHS_HSTADDR1 Address: 0x400AC424 Access: Read-write 31 – 23 – 15 – 7 – 30 29 28 22 21 20 14 13 12 6 5 4 27 HSTADDRP3 19 HSTADDRP2 11 HSTADDRP1 3 HSTADDRP0 • HSTADDRP3: USB Host Address This field contains the address of the Pipe3 of the USB Device. This field is cleared when a USB reset is requested. • HSTADDRP2: USB Host Address This field contains the address of the Pipe2 of the USB Device. This field is cleared when a USB reset is requested.
39.6.3.10 Host Address 2 Register Name: UOTGHS_HSTADDR2 Address: 0x400AC428 Access: Read-write 31 – 23 – 15 – 7 – 30 29 28 22 21 20 14 13 12 6 5 4 27 HSTADDRP7 19 HSTADDRP6 11 HSTADDRP5 3 HSTADDRP4 26 25 24 18 17 16 10 9 8 2 1 0 • HSTADDRP7: USB Host Address This field contains the address of the Pipe7 of the USB Device. This field is cleared when a USB reset is requested. • HSTADDRP6: USB Host Address This field contains the address of the Pipe6 of the USB Device.
39.6.3.11 Host Address 3 Register Name: UOTGHS_HSTADDR3 Address: 0x400AC42C Access: Read-write 31 – 23 – 15 – 7 – 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 6 5 4 27 – 19 – 11 HSTADDRP9 3 HSTADDRP8 • HSTADDRP9: USB Host Address This field contains the address of the Pipe9 of the USB Device. This field is cleared when a USB reset is requested. • HSTADDRP8: USB Host Address This field contains the address of the Pipe8 of the USB Device. This field is cleared when a USB reset is requested.
39.6.3.12 Host Pipe Register Name: UOTGHS_HSTPIP Address: 0x400AC41C Access: Read-write 31 – 23 PRST7 15 – 7 PEN7 30 – 22 PRST6 14 – 6 PEN6 29 – 21 PRST5 13 – 5 PEN5 28 – 20 PRST4 12 – 4 PEN4 27 – 19 PRST3 11 – 3 PEN3 26 – 18 PRST2 10 – 2 PEN2 25 – 17 PRST1 9 – 1 PEN1 24 PRST8 16 PRST0 8 PEN8 0 PEN0 • PRSTx: Pipe x Reset Writing a one to this bit will reset the Pipe x FIFO.
39.6.3.13 Host Pipe x Configuration Register Name: UOTGHS_HSTPIPCFGx [x=0..9] Address: 0x400AC500 Access: Read-write 31 30 29 23 – 15 – 7 – 22 – 14 – 6 21 – 13 5 PSIZE 28 27 INTFRQ/BINTERVAL 20 19 PINGEN 12 11 PTYPE – 4 3 26 18 25 24 17 16 PEPNUM 10 AUTOSW 2 PBK 9 8 PTOKEN 1 ALLOC 0 – • INTFRQ: Pipe Interrupt Request Frequency This field contains the maximum value in millisecond of the polling period for an Interrupt Pipe. This value has no effect for a non-Interrupt Pipe.
• PTYPE: Pipe Type This field contains the pipe type. Value Name Description 0 CTRL Control 1 ISO Isochronous 2 BLK Bulk 3 INTRPT Interrupt This field is cleared upon sending a USB reset. • AUTOSW: Automatic Switch This bit is cleared upon sending a USB reset. 0: The automatic bank switching is disabled. 1: The automatic bank switching is enabled. • PTOKEN: Pipe Token This field contains the endpoint token.
• PBK: Pipe Banks This field contains the number of banks for the pipe. Value Name 0 1_BANK Single-bank pipe 1 2_BANK Double-bank pipe 2 3_BANK Triple-bank pipe 3 Description Reserved For control endpoints, a single-bank pipe (0b00) should be selected. This field is cleared upon sending a USB reset. • ALLOC: Pipe Memory Allocate Writing a one to this bit will allocate the pipe memory. Writing a zero to this bit will free the pipe memory. This bit is cleared when a USB Reset is requested.
39.6.3.14 Host Pipe x Status Register Name: UOTGHS_HSTPIPISRx [x=0..9] Address: 0x400AC530 Access: Read-only 31 30 29 28 – 23 22 21 20 PBYCT 15 14 13 CURRBK 7 27 26 25 24 19 18 17 16 – CFGOK – RWALL 11 10 9 – – PBYCT 12 NBUSYBK 6 SHORTPACKET RXSTALLDI/ I CRCERRI 5 OVERFI 4 NAKEDI 8 DTSEQ 3 2 1 0 PERRI TXSTPI/ UNDERFI TXOUTI RXINI • PBYCT: Pipe Byte Count This field contains the byte count of the FIFO.
• CURRBK: Current Bank For non-control pipe, this field indicates the number of the current bank. Value Name Description 0 BANK0 Current bank is bank0 1 BANK1 Current bank is bank1 2 BANK2 Current bank is bank2 3 Reserved This field may be updated 1 clock cycle after the RWALL bit changes, so the user shall not poll this field as an interrupt bit. • NBUSYBK: Number of Busy Banks This field indicates the number of busy banks.
• CRCERRI: CRC Error Interrupt This bit is set, for isochronous endpoint, when a CRC error occurs on the current bank of the Pipe. This triggers an interrupt if UOTGHS_HSTPIPIMR.TXSTPE bit is one. This bit is cleared when UOTGHS_HSTPIPICR.CRCERRIC bit is written to one. • OVERFI: Overflow Interrupt This bit is set when the current pipe has received more data than the maximum length of the current pipe. An interrupt is triggered if UOTGHS_HSTPIPIMR.OVERFIE bit is one.
39.6.3.15 Host Pipe x Clear Register Name: UOTGHS_HSTPIPICRx [x=0..9] Address: 0x400AC560 Access: Write-only 31 – 23 – 15 – 7 SHORT PACKETIC 30 – 22 – 14 – 6 RXSTALLDIC /CRCERRIC 29 – 21 – 13 – 5 28 – 20 – 12 – 4 27 – 19 – 11 – 3 OVERFIC NAKEDIC – 26 – 18 – 10 – 2 TXSTPIC/ UNDERFIC • SHORTPACKETIC: Short Packet Interrupt Clear Writing a one to this bit will clear SHORTPACKETI bit in UOTGHS_HSTPIPISRx. Writing a zero to this bit has no effect. This bit always reads as zero.
• UNDERFIC: Underflow Interrupt Clear Writing a one to this bit will clear UNDERFI bit in UOTGHS_HSTPIPISRx. Writing a zero to this bit has no effect. This bit always reads as zero. • TXOUTIC: Transmitted OUT Data Interrupt Clear Writing a one to this bit will clear TXOUTI bit in UOTGHS_HSTPIPISRx. Writing a zero to this bit has no effect. This bit always reads as zero. • RXINIC: Received IN Data Interrupt Clear Writing a one to this bit will clear RXINI bit in UOTGHS_HSTPIPISRx.
39.6.3.16 Host Pipe x Set Register Name: UOTGHS_HSTPIPIFRx [x=0..
• PERRIS: Pipe Error Interrupt Set Writing a one to this bit will set PERRI bit in UOTGHS_HSTPIPISRx, which may be useful for test or debug purposes. Writing a zero to this bit has no effect. This bit always reads as zero. • TXSTPIS: Transmitted SETUP Interrupt Set Writing a one to this bit will set TXSTPI bit in UOTGHS_HSTPIPISRx, which may be useful for test or debug purposes. Writing a zero to this bit has no effect. This bit always reads as zero.
39.6.3.17 Host Pipe x Mask Register Name: UOTGHS_HSTPIPIMRx [x=0..9] Address: 0x400AC5C0 Access: Read-only 31 – 23 – 15 – 7 SHORT PACKETIE 30 – 22 – 14 FIFOCON 6 RXSTALLDE/ CRCERRE 29 – 21 – 13 – 5 28 – 20 – 12 NBUSYBKE 4 27 – 19 – 11 – 3 OVERFIE NAKEDE PERRE 26 – 18 RSTDT 10 – 2 TXSTPE/ UNDERFIE 25 – 17 PFREEZE 9 – 1 24 – 16 PDISHDMA 8 – 0 TXOUTE RXINE • RSTDT: Reset Data Toggle This bit is set when UOTGHS_HSTPIPIER.RSTDTS bit is written to one.
• SHORTPACKETIE: Short Packet Interrupt Enable If this bit is set for non-control OUT pipes, a short packet transmission is guaranteed upon ending a DMA transfer, thus signaling an end of transfer, provided that the End of DMA Buffer Output Enable (UOTGHS_HSTDMACONTROL.END_B_EN) bit and the Automatic Switch (UOTGHS_HSTPIPCFG.AUTOSW) bit are written to one. This bit is set when UOTGHS_HSTPIPIER.SHORTPACKETIES bit is written to one. This will enable the Transmitted IN Data IT (UOTGHS_HSTPIPIMR.SHORTPACKETIE).
• UNDERFIE: Underflow Interrupt Enable This bit is set when UOTGHS_HSTPIPIER.UNDERFIES bit is written to one. This will enable the Transmitted IN Data interrupt (UOTGHS_HSTPIPIMR.UNDERFIE). This bit is cleared when UOTGHS_HSTPIPIDR.UNDERFIEC bit is written to one. This will disable the Transmitted IN Data interrupt (UOTGHS_HSTPIPIMR.UNDERFIE). • TXOUTE: Transmitted OUT Data Interrupt Enable This bit is set when UOTGHS_HSTPIPIER.TXOUTES bit is written to one.
39.6.3.18 Host Pipe x Disable Register Name: UOTGHS_HSTPIPIDRx [x=0..
• CRCERREC: CRC Error Interrupt Disable Writing a one to this bit will clear CRCERRE bit in UOTGHS_HSTPIPIMRx. Writing a zero to this bit has no effect. This bit always reads as zero. • OVERFIEC: Overflow Interrupt Disable Writing a one to this bit will clear OVERFIE bit in UOTGHS_HSTPIPIMRx. Writing a zero to this bit has no effect. This bit always reads as zero. • NAKEDEC: NAKed Interrupt Disable Writing a one to this bit will clear NAKEDE bit in UOTGHS_HSTPIPIMRx.
39.6.3.19 Host Pipe x Enable Register Name: UOTGHS_HSTPIPIERx [x=0..
• CRCERRES: CRC Error Interrupt Enable Writing a one to this bit will set CRCERRE bit in UOTGHS_HSTPIPIMRx. Writing a zero to this bit has no effect. This bit always reads as zero. • OVERFIES: Overflow Interrupt Enable Writing a one to this bit will set OVERFIE bit in UOTGHS_HSTPIPIMRx. Writing a zero to this bit has no effect. This bit always reads as zero. • NAKEDES: NAKed Interrupt Enable Writing a one to this bit will set NAKEDE bit in UOTGHS_HSTPIPIMRx. Writing a zero to this bit has no effect.
39.6.3.20 Host Pipe x IN Request Register Name: UOTGHS_HSTPIPINRQx [x=0..9] Address: 0x400AC650 Access: Read-write 31 – 23 – 15 – 7 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 INMODE 0 INRQ • INMODE: IN Request Mode Writing a one to this bit will allow the UOTGHS to perform infinite IN requests when the Pipe is not frozen. Writing a zero to this bit will perform a pre-defined number of IN requests.
39.6.3.21 Host Pipe x Error Register Name: UOTGHS_HSTPIPERRx [x=0..9] Address: 0x400AC680 Access: Read-write 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 29 – 21 – 13 – 5 COUNTER 28 – 20 – 12 – 4 CRC16 27 – 19 – 11 – 3 TIMEOUT 26 – 18 – 10 – 2 PID 25 – 17 – 9 – 1 DATAPID 24 – 16 – 8 – 0 DATATGL • COUNTER: Error Counter This field is incremented each time an error occurs (CRC16, TIMEOUT, PID, DATAPID or DATATGL). This field is cleared when receiving a good USB packet without any error.
39.6.3.22 Host DMA Channel x Next Descriptor Address Register Name: UOTGHS_HSTDMANXTDSCx [x=1..6] Address: 0x400AC710 [1], 0x400AC720 [2], 0x400AC730 [3], 0x400AC740 [4], 0x400AC750 [5], 0x400AC760 [6], 0x400AC770 [7] Access: Read-write 31 30 29 23 22 21 15 14 13 7 6 5 28 27 NXT_DSC_ADD 20 19 NXT_DSC_ADD 12 11 NXT_DSC_ADD 4 3 NXT_DSC_ADD 26 25 24 18 17 16 10 9 8 2 1 0 • NXT_DSC_ADD: Next Descriptor Address This field points to the next channel descriptor to be processed.
39.6.3.23 Host DMA Channel x Address Register Name: UOTGHS_HSTDMAADDRESSx [x=1..6] Address: 0x400AC714 [1], 0x400AC724 [2], 0x400AC734 [3], 0x400AC744 [4], 0x400AC754 [5], 0x400AC764 [6], 0x400AC774 [7] Access: Read-write 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 BUFF_ADD BUFF_ADD 15 14 13 12 7 6 5 4 BUFF_ADD BUFF_ADD • BUFF_ADD: Buffer Address This field determines the AHB bus starting address of a DMA channel transfer.
39.6.3.24 Host DMA Channel x Control Register Name: UOTGHS_HSTDMACONTROLx [x=1..
• END_TR_EN: End of Transfer Enable (Control) Used for OUT transfers only. 0: USB end of transfer is ignored. 1: UOTGHS device can put an end to the current buffer transfer. When set, a BULK or INTERRUPT short packet will close the current buffer and the UOTGHS_HSTDMASTATUSx.END_TR_ST flag will be raised. This is intended for a UOTGHS non-prenegotiated end of transfer (BULK or INTERRUPT) data buffer closure. • END_B_EN: End of Buffer Enable Control 0: DMA Buffer End has no impact on USB packet transfer.
39.6.3.25 Host DMA Channel x Status Register Name: UOTGHS_HSTDMASTATUSx [x=1..
• DESC_LDST: Descriptor Loaded Status 0: cleared automatically when read by software. 1: set by hardware when a descriptor has been loaded from the system bus. Valid until the CHANN_ENB flag is cleared at the end of the next buffer transfer. • BUFF_COUNT: Buffer Byte Count This field determines the current number of bytes still to be transferred for this buffer. This field is decremented from the AHB source bus access byte width at the end of this bus address phase.
40. Controller Area Network (CAN) 40.1 Description The CAN controller provides all the features required to implement the serial communication protocol CAN defined by Robert Bosch GmbH, the CAN specification as referred to by ISO/11898A (2.0 Part A and 2.0 Part B) for high speeds and ISO/11519-2 for low speeds. The CAN Controller is able to handle all types of frames (Data, Remote, Error and Overload) and achieves a bitrate of 1 Mbit/sec. CAN controller accesses are made through configuration registers.
40.3 Block Diagram Figure 40-1. CAN Block Diagram Controller Area Network CANRX CAN Protocol Controller PIO CANTX Error Counter Mailbox Priority Encoder Control & Status MB0 MB1 MCK PMC MBx (x = number of mailboxes - 1) CAN Interrupt User Interface Internal Bus 40.4 Application Block Diagram Figure 40-2.
40.5 I/O Lines Description Table 40-1. I/O Lines Description Name Description Type CANRX CAN Receive Serial Data Input CANTX CAN Transmit Serial Data Output 40.6 Product Dependencies 40.6.1 I/O Lines The pins used for interfacing the CAN may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the desired CAN pins to their peripheral function.
40.7 CAN Controller Features 40.7.1 CAN Protocol Overview The Controller Area Network (CAN) is a multi-master serial communication protocol that efficiently supports realtime control with a very high level of security with bit rates up to 1 Mbit/s. The CAN protocol supports four different frame types: Data frames: They carry data from a transmitter node to the receiver nodes. The overall maximum data frame length is 108 bits for a standard frame and 128 bits for an extended frame.
Figure 40-3. Message Acceptance Procedure CAN_MAMx CAN_MIDx & Message Received & == No Message Refused Yes Message Accepted CAN_MFIDx If a mailbox is dedicated to receiving several messages (a family of messages) with different IDs, the acceptance mask defined in the CAN_MAMx register must mask the variable part of the ID family. Once a message is received, the application must decode the masked bits in the CAN_MIDx.
40.7.2.2 Receive Mailbox When the CAN module receives a message, it looks for the first available mailbox with the lowest number and compares the received message ID with the mailbox ID. If such a mailbox is found, then the message is stored in its data registers.
40.7.3 Time Management Unit The CAN Controller integrates a free-running 16-bit internal timer. The counter is driven by the bit clock of the CAN bus line. It is enabled when the CAN controller is enabled (CANEN set in the CAN_MR register).
40.7.4 CAN 2.0 Standard Features 40.7.4.1 CAN Bit Timing Configuration All controllers on a CAN bus must have the same bit rate and bit length. At different clock frequencies of the individual controllers, the bit rate has to be adjusted by the time segments. The CAN protocol specification partitions the nominal bit time into four different segments: Figure 40-4.
SJW is programmable to be the minimum of PHASE SEG1 and 4 TQ. If the SMP field in the CAN_BR register is set, then the incoming bit stream is sampled three times with a period of half a CAN clock period, centered on sample point. In the CAN controller, the length of a bit on the CAN bus is determined by the parameters (BRP, PROPAG, PHASE1 and PHASE2).
Example of bit timing determination for CAN baudrate of 500 Kbit/s: MCK = 48MHz CAN baudrate= 500kbit/s => bit time= 2us Delay of the bus driver: 50 ns Delay of the receiver: 30ns Delay of the bus line (20m): 110ns The total number of time quanta in a bit time must be comprised between 8 and 25.
Figure 40-6.
Fault Confinement To distinguish between temporary and permanent failures, every CAN controller has two error counters: REC (Receive Error Counter) and TEC (Transmit Error Counter). The two counters are incremented upon detected errors and are decremented upon correct transmissions or receptions, respectively. Depending on the counter values, the state of the node changes: the initial state of the CAN controller is Error Active, meaning that the controller can send Error Active flags.
In Error Active Mode, the user reads: ERRA =1 ERRP = 0 BOFF = 0 In Error Passive Mode, the user reads: ERRA = 0 ERRP =1 BOFF = 0 In Bus Off Mode, the user reads: ERRA = 0 ERRP =1 BOFF =1 The CAN interrupt handler should do the following: Only enable one error mode interrupt at a time. Look at and check the REC and TEC values in the interrupt handler to determine the current state. 40.7.4.
Reception is disabled while the SLEEP signal is set to one in the CAN_SR register. It is important to note that those messages with higher priority than the last message transmitted can be received between the LPM command and entry in Low-power Mode. Once in Low-power Mode, the CAN controller clock can be switched off by programming the chip’s Power Management Controller (PMC). The CAN controller drains only the static current. Error counters are disabled while the SLEEP signal is set to one.
If there is bus activity when Low-power mode is disabled, the CAN controller is synchronized with the bus activity in the next interframe. The previous message is lost (see Figure 40-9). Figure 40-9. Disabling Low-power Mode Bus Activity Detected CAN BUS Message lost LPM (CAN_MR) Message x Interframe synchronization SLEEP (CAN_SR) WAKEUP (CAN_SR) MRDY (CAN_MSRx) 40.8 Functional Description 40.8.1 CAN Controller Initialization After power-up reset, the CAN controller is disabled.
Figure 40-10. Possible Initialization Procedure Enable CAN Controller Clock (PMC) Enable CAN Controller Interrupt Line (AIC) Configure a Mailbox in Reception Mode Change CAN_BR value (ABM == 1 and CANEN == 1) Errors ? Yes (CAN_SR or CAN_MSRx) No ABM = 0 and CANEN = 0 CANEN = 1 (ABM == 0) End of Initialization 40.8.2 CAN Controller Interrupt Handling There are two different types of interrupts.
̶ Internal timer counter overflow interrupt: This interrupt is generated when the internal timer rolls over. ̶ Timestamp interrupt: This interrupt is generated after the reception or the transmission of a start of frame or an end of frame. The value of the internal counter is copied in the CAN_TIMESTP register. All interrupts are cleared by clearing the interrupt source except for the internal timer counter overflow interrupt and the timestamp interrupt.
Receive with Overwrite Mailbox A mailbox is in Receive with Overwrite Mode once the MOT field in the CAN_MMRx register has been configured. Message ID and Message Acceptance masks must be set before Receive Mode is enabled. After Receive Mode is enabled, the MRDY flag in the CAN_MSR register is automatically cleared until the first message is received. When the first message has been accepted by the mailbox, the MRDY flag is set. An interrupt is pending for the mailbox while the MRDY flag is set.
Figure 40-13.
40.8.3.2 Transmission Handling A mailbox is in Transmit Mode once the MOT field in the CAN_MMRx register has been configured. Message ID and Message Acceptance mask must be set before Receive Mode is enabled. After Transmit Mode is enabled, the MRDY flag in the CAN_MSR register is automatically set until the first command is sent. When the MRDY flag is set, the software application can prepare a message to be sent by writing to the CAN_MDx registers.
Figure 40-15. Transmitting Messages MBx message CAN BUS MBx message MRDY (CAN_MSRx) MABT (CAN_MSRx) MTCR (CAN_MCRx) MACR (CAN_MCRx) Abort MBx message Try to Abort MBx message Reading CAN_MSRx Writing CAN_MDHx & CAN_MDLx 40.8.3.3 Remote Frame Handling Producer/consumer model is an efficient means of handling broadcasted messages. The push model allows a producer to broadcast messages; the pull model allows a customer to ask for messages. Figure 40-16.
Producer Configuration A mailbox is in Producer Mode once the MOT field in the CAN_MMRx register has been configured. Message ID and Message Acceptance masks must be set before Receive Mode is enabled. After Producer Mode is enabled, the MRDY flag in the CAN_MSR register is automatically set until the first transfer command. The software application prepares data to be sent by writing to the CAN_MDHx and the CAN_MDLx registers, then by setting the MTCR bit in the CAN_MCRx register.
case, the consumer mailbox must have a lower number than the Receive with Overwrite mailbox. The transfer command can be triggered for all mailboxes at the same time by setting several MBx fields in the CAN_TCR register. Figure 40-18. Consumer Handling CAN BUS Remote Frame Message x Remote Frame Message y MRDY (CAN_MSRx) MMI (CAN_MSRx) MTCR (CAN_MCRx) (CAN_MDLx CAN_MDHx) Message y Message x 40.8.
40.8.4.2 Time Triggered Mode In Time Triggered Mode, basic cycles can be split into several time windows. A basic cycle starts with a reference message. Each time a window is defined from the reference message, a transmit operation should occur within a pre-defined time window. A mailbox must not win the arbitration in a previous time window, and it must not be retried if the arbitration is lost in the time window. Figure 40-20.
Figure 40-21.
40.8.5 Write Protected Registers To prevent any single software error that may corrupt CAN behavior, the registers listed below can be writeprotected by setting the WPEN bit in the CAN Write Protection Mode Register (CAN_WPMR). If a write access in a write-protected register is detected, then the WPVS flag in the CAN Write Protection Status Register (CAN_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted.
40.9 Controller Area Network (CAN) User Interface Table 40-6.
40.9.1 CAN Mode Register Name: CAN_MR Address: 0x400B4000 (0), 0x400B8000 (1) Access: Read-write 31 – 23 – 15 – 7 DRPT 30 – 22 – 14 – 6 TIMFRZ 29 – 21 – 13 – 5 TTM 28 – 20 – 12 – 4 TEOF 27 – 19 – 11 – 3 OVL 26 18 – 10 – 2 ABM 25 RXSYNC 17 – 9 – 1 LPM 24 16 – 8 – 0 CANEN This register can only be written if the WPEN bit is cleared in ”CAN Write Protection Mode Register”. • CANEN: CAN Controller Enable 0: The CAN Controller is disabled. 1: The CAN Controller is enabled.
• DRPT: Disable Repeat 0: When a transmit mailbox loses the bus arbitration, the transfer request remains pending. 1: When a transmit mailbox lose the bus arbitration, the transfer request is automatically aborted. It automatically raises the MABT and MRDT flags in the corresponding CAN_MSRx.
40.9.2 CAN Interrupt Enable Register Name: CAN_IER Address: 0x400B4004 (0), 0x400B8004 (1) Access: Write-only 31 – 23 TSTP 15 – 7 MB7 30 – 22 TOVF 14 – 6 MB6 29 – 21 WAKEUP 13 – 5 MB5 • MBx: Mailbox x Interrupt Enable 0: No effect. 1: Enable Mailbox x interrupt. • ERRA: Error Active Mode Interrupt Enable 0: No effect. 1: Enable ERRA interrupt. • WARN: Warning Limit Interrupt Enable 0: No effect. 1: Enable WARN interrupt. • ERRP: Error Passive Mode Interrupt Enable 0: No effect.
• TSTP: TimeStamp Interrupt Enable 0: No effect. 1: Enable TSTP interrupt. • CERR: CRC Error Interrupt Enable 0: No effect. 1: Enable CRC Error interrupt. • SERR: Stuffing Error Interrupt Enable 0: No effect. 1: Enable Stuffing Error interrupt. • AERR: Acknowledgment Error Interrupt Enable 0: No effect. 1: Enable Acknowledgment Error interrupt. • FERR: Form Error Interrupt Enable 0: No effect. 1: Enable Form Error interrupt. • BERR: Bit Error Interrupt Enable 0: No effect. 1: Enable Bit Error interrupt.
40.9.3 CAN Interrupt Disable Register Name: CAN_IDR Address: 0x400B4008 (0), 0x400B8008 (1) Access: Write-only 31 – 23 TSTP 15 – 7 MB7 30 – 22 TOVF 14 – 6 MB6 29 – 21 WAKEUP 13 – 5 MB5 • MBx: Mailbox x Interrupt Disable 0: No effect. 1: Disable Mailbox x interrupt. • ERRA: Error Active Mode Interrupt Disable 0: No effect. 1: Disable ERRA interrupt. • WARN: Warning Limit Interrupt Disable 0: No effect. 1: Disable WARN interrupt. • ERRP: Error Passive Mode Interrupt Disable 0: No effect.
• TSTP: TimeStamp Interrupt Disable 0: No effect. 1: Disable TSTP interrupt. • CERR: CRC Error Interrupt Disable 0: No effect. 1: Disable CRC Error interrupt. • SERR: Stuffing Error Interrupt Disable 0: No effect. 1: Disable Stuffing Error interrupt. • AERR: Acknowledgment Error Interrupt Disable 0: No effect. 1: Disable Acknowledgment Error interrupt. • FERR: Form Error Interrupt Disable 0: No effect. 1: Disable Form Error interrupt. • BERR: Bit Error Interrupt Disable 0: No effect.
40.9.4 CAN Interrupt Mask Register Name: CAN_IMR Address: 0x400B400C (0), 0x400B800C (1) Access: Read-only 31 – 23 TSTP 15 – 7 MB7 30 – 22 TOVF 14 – 6 MB6 29 – 21 WAKEUP 13 – 5 MB5 • MBx: Mailbox x Interrupt Mask 0: Mailbox x interrupt is disabled. 1: Mailbox x interrupt is enabled. • ERRA: Error Active Mode Interrupt Mask 0: ERRA interrupt is disabled. 1: ERRA interrupt is enabled. • WARN: Warning Limit Interrupt Mask 0: Warning Limit interrupt is disabled. 1: Warning Limit interrupt is enabled.
• TSTP: Timestamp Interrupt Mask 0: TSTP interrupt is disabled. 1: TSTP interrupt is enabled. • CERR: CRC Error Interrupt Mask 0: CRC Error interrupt is disabled. 1: CRC Error interrupt is enabled. • SERR: Stuffing Error Interrupt Mask 0: Bit Stuffing Error interrupt is disabled. 1: Bit Stuffing Error interrupt is enabled. • AERR: Acknowledgment Error Interrupt Mask 0: Acknowledgment Error interrupt is disabled. 1: Acknowledgment Error interrupt is enabled.
40.9.5 CAN Status Register Name: CAN_SR Address: 0x400B4010 (0), 0x400B8010 (1) Access: Read-only 31 OVLSY 23 TSTP 15 – 7 MB7 30 TBSY 22 TOVF 14 – 6 MB6 29 RBSY 21 WAKEUP 13 – 5 MB5 28 BERR 20 SLEEP 12 – 4 MB4 27 FERR 19 BOFF 11 – 3 MB3 26 AERR 18 ERRP 10 – 2 MB2 25 SERR 17 WARN 9 – 1 MB1 24 CERR 16 ERRA 8 – 0 MB0 • MBx: Mailbox x Event 0: No event occurred on Mailbox x. 1: An event occurred on Mailbox x. An event corresponds to MRDY, MABT fields in the CAN_MSRx register.
• BOFF: Bus Off Mode 0: CAN controller is not in Bus Off Mode. 1: CAN controller is in Bus Off Mode. This flag is set depending on TEC counter value. A node is in bus off state when TEC counter is greater or equal to 256 (decimal). This flag is automatically reset when the above condition is not satisfied. Refer to Section “Error Interrupt Handler” on page 1196 for more information. • SLEEP: CAN controller in Low power Mode 0: CAN controller is not in low power mode. 1: CAN controller is in low power mode.
• AERR: Acknowledgment Error 0: No acknowledgment error occurred during a previous transfer. 1: An acknowledgment error occurred during a previous transfer. An acknowledgment error is detected when no detection of the dominant bit in the acknowledge slot occurs. This flag is automatically cleared by reading CAN_SR register.
40.9.6 CAN Baudrate Register Name: CAN_BR Address: 0x400B4014 (0), 0x400B8014 (1) Access: Read-write 31 – 23 – 15 – 7 – 30 – 22 29 – 21 14 – 6 13 28 – 20 12 SJW 5 PHASE1 4 27 – 19 BRP 11 – 3 – 26 – 18 25 – 17 24 SMP 16 10 9 PROPAG 1 PHASE2 8 2 0 This register can only be written if the WPEN bit is cleared in ”CAN Write Protection Mode Register”. Any modification on one of the fields of the CAN_BR register must be done while CAN module is disabled.
40.9.7 CAN Timer Register Name: CAN_TIM Address: 0x400B4018 (0), 0x400B8018 (1) Access: Read-only 31 – 23 – 15 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 7 6 5 4 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 3 2 1 0 TIMER TIMER • TIMER: Timer This field represents the internal CAN controller 16-bit timer value.
40.9.8 CAN Timestamp Register Name: CAN_TIMESTP Address: 0x400B401C (0), 0x400B801C (1) Access: Read-only 31 – 23 – 15 30 – 22 – 14 29 – 21 – 13 7 6 5 28 27 – – 20 19 – – 12 11 MTIMESTAMP 4 3 MTIMESTAMP 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 2 1 0 • MTIMESTAMP: Timestamp This field carries the value of the internal CAN controller 16-bit timer value at the start or end of frame.
40.9.9 CAN Error Counter Register Name: CAN_ECR Address: 0x400B4020 (0), 0x400B8020 (1) Access: Read-only 31 – 23 30 – 22 29 – 21 28 – 20 27 – 19 26 – 18 25 – 17 24 – 16 11 – 3 10 – 2 9 – 1 8 – 0 TEC 15 – 7 14 – 6 13 – 5 12 – 4 REC • REC: Receive Error Counter When a receiver detects an error, REC will be increased by one, except when the detected error is a BIT ERROR while sending an ACTIVE ERROR FLAG or an OVERLOAD FLAG.
40.9.10 CAN Transfer Command Register Name: CAN_TCR Address: 0x400B4024 (0), 0x400B8024 (1) Access: Write-only 31 TIMRST 23 – 15 – 7 MB7 30 – 22 – 14 – 6 MB6 29 – 21 – 13 – 5 MB5 28 – 20 – 12 – 4 MB4 27 – 19 – 11 – 3 MB3 26 – 18 – 10 – 2 MB2 25 – 17 – 9 – 1 MB1 24 – 16 – 8 – 0 MB0 This register initializes several transfer requests at the same time. • MBx: Transfer Request for Mailbox x Mailbox Object Type Description Receive It receives the next message.
40.9.11 CAN Abort Command Register Name: CAN_ACR Address: 0x400B4028 (0), 0x400B8028 (1) Access: Write-only 31 – 23 – 15 – 7 MB7 30 – 22 – 14 – 6 MB6 29 – 21 – 13 – 5 MB5 28 – 20 – 12 – 4 MB4 27 – 19 – 11 – 3 MB3 26 – 18 – 10 – 2 MB2 25 – 17 – 9 – 1 MB1 This register initializes several abort requests at the same time.
40.9.
40.9.13 CAN Write Protection Status Register Name: CAN_WPSR Address: 0x400B40E8 (0), 0x400B80E8 (1) Access: Read-only 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 WPVSRC 7 6 5 4 3 2 1 0 - - - - - - - WPVS • WPVS: Write Protection Violation Status 0 = No Write Protect Violation has occurred since the last read of the CAN_WPSR register.
40.9.14 CAN Message Mode Register Name: CAN_MMRx [x=0..
40.9.15 CAN Message Acceptance Mask Register Name: CAN_MAMx [x=0..
40.9.16 CAN Message ID Register Name: CAN_MIDx [x=0..
40.9.17 CAN Message Family ID Register Name: CAN_MFIDx [x=0..
40.9.18 CAN Message Status Register Name: CAN_MSRx [x=0..
• MABT: Mailbox Message Abort An interrupt is triggered when MABT is set. 0: Previous transfer is not aborted. 1: Previous transfer has been aborted. This flag is cleared by writing to CAN_MCRx register Mailbox Object Type Description Receive Reserved Receive with overwrite Reserved Transmit Previous transfer has been aborted Consumer The remote frame transfer request has been aborted. Producer The response to the remote frame transfer has been aborted.
• MMI: Mailbox Message Ignored 0: No message has been ignored during the previous transfer 1: At least one message has been ignored during the previous transfer Cleared by reading the CAN_MSRx register. Mailbox Object Type Description Receive Set when at least two messages intended for the mailbox have been sent. The first one is available in the mailbox data register. Others have been ignored. A mailbox with a lower priority may have accepted the message.
40.9.19 CAN Message Data Low Register Name: CAN_MDLx [x=0..
40.9.20 CAN Message Data High Register Name: CAN_MDHx [x=0..
40.9.21 CAN Message Control Register Name: CAN_MCRx [x=0..
• MACR: Abort Request for Mailbox x Mailbox Object Type Description Receive No action Receive with overwrite No action Transmit Cancels transfer request if the message has not been transmitted to the CAN transceiver. Consumer Cancels the current transfer before the remote frame has been sent. Producer Cancels the current transfer. The next remote frame will not be serviced. It is possible to set MACR field for several mailboxes in the same time, setting several bits to the CAN_ACR register.
41. Ethernet MAC 10/100 (EMAC) 41.1 Description The EMAC module implements a 10/100 Ethernet MAC compatible with the IEEE 802.3 standard using an address checker, statistics and control registers, receive and transmit blocks, and a DMA interface. The address checker recognizes four specific 48-bit addresses and contains a 64-bit hash register for matching multicast and unicast addresses. It can recognize the broadcast address of all ones, copy all frames, and act on an external address match signal. 41.
41.3 Block Diagram Figure 41-1.
41.4 Functional Description The MACB has several clock domains: System bus clock (AHB and APB): DMA and register blocks Transmit clock: transmit block Receive clock: receive and address checker block The system bus clock must run at least as fast as the receive clock and transmit clock (25 MHz at 100 Mbps, and 2.5 MHZ at 10 Mbps). Figure 41-1 illustrates the different blocks of the EMAC module.
Data is typically transferred into and out of the FIFOs in bursts of four words. For receive, a bus request is asserted when the FIFO contains four words and has space for 28 more. For transmit, a bus request is generated when there is space for four words, or when there is space for 27 words if the next transfer is to be only one or two words. Thus the bus latency must be less than the time it takes to load the FIFO and transmit or receive three words (112 bytes) of data.
Table 41-1. Receive Buffer Descriptor Entry (Continued) Bit Function 19:17 VLAN priority (only valid if bit 21 is set) 16 Concatenation format indicator (CFI) bit (only valid if bit 21 is set) 15 End of frame - when set the buffer contains the end of a frame. If end of frame is not set, then the only other valid status are bits 12, 13 and 14. 14 Start of frame - when set the buffer contains the start of a frame. If both bits 15 and 14 are set, then the buffer contains a whole frame.
If bit zero is set when the receive buffer manager reads the location of the receive buffer, then the buffer has already been used and cannot be used again until software has processed the frame and cleared bit zero. In this case, the DMA block sets the buffer not available bit in the receive status register and triggers an interrupt.
To set tx_go, write to bit 9, tx_start, of the network control register. Transmit halt does not take effect until any ongoing transmit finishes. If a collision occurs during transmission of a multi-buffer frame, transmission automatically restarts from the first buffer of the frame. If a “used” bit is read midway through transmission of a multi-buffer frame, this is treated as a transmit error. Transmission stops, tx_er is asserted and the FCS is bad.
After the first collision, 1 bit is used, after the second 2, and so on up to 10. Above 10, all 10 bits are used. An error is indicated and no further attempts are made if 16 attempts cause collisions. If transmit DMA underruns, bad CRC is automatically appended using the same mechanism as jam insertion and the tx_er signal is asserted. For a properly configured system, this should never happen.
41.4.6 Address Checking Block The address checking (or filter) block indicates to the DMA block which receive frames should be copied to memory. Whether a frame is copied depends on what is enabled in the network configuration register, the state of the external match pin, the contents of the specific address and hash registers and the frame’s destination address. In this implementation of the EMAC, the frame’s source address is not checked.
41.4.7 Broadcast Address The broadcast address of 0xFFFFFFFFFFFF is recognized if the ‘no broadcast’ bit in the network configuration register is zero. 41.4.8 Hash Addressing The hash address register is 64 bits long and takes up two locations in the memory map. The least significant bits are stored in hash register bottom and the most significant bits in hash register top.
41.4.11 VLAN Support An Ethernet encoded 802.1Q VLAN tag looks like this: Table 41-4. 802.1Q VLAN Tag TPID (Tag Protocol Identifier) 16 bits TCI (Tag Control Information) 16 bits 0x8100 First 3 bits priority, then CFI bit, last 12 bits VID The VLAN tag is inserted at the 13th byte of the frame, adding an extra four bytes to the frame. If the VID (VLAN identifier) is null (0x000), this indicates a priority-tagged frame.
Table 41-5.
41.5 Programming Interface 41.5.1 Initialization 41.5.1.1 Configuration Initialization of the EMAC configuration (e.g., loop-back mode, frequency ratios) must be done while the transmit and receive circuits are disabled. See the description of the network control register and network configuration register earlier in this document. To change loop-back mode, the following sequence of operations must be followed: 1. Write to network control register to disable transmit and receive circuits. 2.
41.5.1.3 Transmit Buffer List Transmit data is read from areas of data (the buffers) in system memory These buffers are listed in another data structure that also resides in main memory. This data structure (Transmit Buffer Queue) is a sequence of descriptor entries (as defined in Table 41-2 on page 1248) that points to this data structure. To create this list of buffers: 1. Allocate a number (n) of buffers of between 1 and 2047 bytes of data to be transmitted in system memory.
41.5.1.7 Receiving Frames When a frame is received and the receive circuits are enabled, the EMAC checks the address and, in the following cases, the frame is written to system memory: if it matches one of the four specific address registers. if it matches the hash address function. if it is a broadcast address (0xFFFFFFFFFFFF) and broadcasts are allowed. if the EMAC is configured to copy all frames.
41.6 Ethernet MAC 10/100 (EMAC) User Interface Table 41-6.
Table 41-6.
41.6.1 Network Control Register Name: EMAC_NCR Address: 0x400B0000 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 THALT 9 TSTART 8 BP 7 WESTAT 6 INCSTAT 5 CLRSTAT 4 MPE 3 TE 2 RE 1 LLB 0 LB • LB: LoopBack Asserts the loopback signal to the PHY. • LLB: Loopback local Connects txd to rxd, tx_en to rx_dv, forces full duplex and drives rx_clk and tx_clk with pclk divided by 4.
• TSTART: Start transmission Writing one to this bit starts transmission. • THALT: Transmit halt Writing one to this bit halts transmission as soon as any ongoing frame transmission ends.
41.6.2 Network Configuration Register Name: EMAC_NCFGR Address: 0x400B0004 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 IRXFCS 18 EFRHD 17 DRFCS 16 RLCE 14 13 PAE 12 RTY 11 10 9 – 8 BIG 5 NBC 4 CAF 3 JFRAME 2 – 1 FD 0 SPD 15 RBOF 7 UNI 6 MTI CLK • SPD: Speed Set to 1 to indicate 100 Mbit/s operation, 0 for 10 Mbit/s. The value of this pin is reflected on the speed pin.
• CLK: MDC clock divider Set according to system clock speed. This determines by what number system clock is divided to generate MDC. For conformance with 802.3, MDC must not exceed 2.5MHz (MDC is only active during MDIO read and write operations). Value Name Description 0 HCLK_8 MCK divided by 8 (MCK up to 20 MHz). 1 HCLK_16 MCK divided by 16 (MCK up to 40 MHz). 2 HCLK_32 MCK divided by 32 (MCK up to 80 MHz). 3 HCLK_64 MCK divided by 64 (MCK up to 160 MHz).
41.6.3 Network Status Register Name: EMAC_NSR Address: 0x400B0008 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 IDLE 1 MDIO 0 – • MDIO Returns status of the mdio_in pin. Use the PHY maintenance register for reading managed frames rather than this bit. • IDLE 0: The PHY logic is running. 1: The PHY management logic is idle (i.e., has completed).
41.6.4 Transmit Status Register Name: EMAC_TSR Address: 0x400B0014 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 UND 5 COMP 4 BEX 3 TGO 2 RLES 1 COL 0 UBR This register, when read, provides details of the status of a transmit. Once read, individual bits may be cleared by writing 1 to them. It is not possible to set a bit to 1 by writing to the register.
41.6.5 Receive Buffer Queue Pointer Register Name: EMAC_RBQP Address: 0x400B0018 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR This register points to the entry in the receive buffer queue (descriptor list) currently being used. It is written with the start location of the receive buffer descriptor list.
41.6.6 Transmit Buffer Queue Pointer Register Name: EMAC_TBQP Address: 0x400B001C Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR This register points to the entry in the transmit buffer queue (descriptor list) currently being used. It is written with the start location of the transmit buffer descriptor list.
41.6.7 Receive Status Register Name: EMAC_RSR Address: 0x400B0020 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 OVR 1 REC 0 BNA This register, when read, provides details of the status of a receive. Once read, individual bits may be cleared by writing 1 to them. It is not possible to set a bit to 1 by writing to the register.
41.6.8 Interrupt Status Register Name: EMAC_ISR Address: 0x400B0024 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 PTZ 12 PFRE 11 HRESP 10 ROVR 9 – 8 – 7 TCOMP 6 TXERR 5 RLEX 4 TUND 3 TXUBR 2 RXUBR 1 RCOMP 0 MFD • MFD: Management Frame Done The PHY maintenance register has completed its operation. Cleared on read. • RCOMP: Receive Complete A frame has been stored in memory. Cleared on read.
• PFRE: Pause Frame Received Indicates a valid pause has been received. Cleared on a read. • PTZ: Pause Time Zero Set when the pause time register, 0x38 decrements to zero. Cleared on a read.
41.6.9 Interrupt Enable Register Name: EMAC_IER Address: 0x400B0028 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 PTZ 12 PFR 11 HRESP 10 ROVR 9 – 8 – 7 TCOMP 6 TXERR 5 RLE 4 TUND 3 TXUBR 2 RXUBR 1 RCOMP 0 MFD • MFD: Management Frame sent Enable management done interrupt. • RCOMP: Receive Complete Enable receive complete interrupt. • RXUBR: Receive Used Bit Read Enable receive used bit read interrupt.
• PTZ: Pause Time Zero Enable pause time zero interrupt.
41.6.10 Interrupt Disable Register Name: EMAC_IDR Address: 0x400B002C Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 PTZ 12 PFR 11 HRESP 10 ROVR 9 – 8 – 7 TCOMP 6 TXERR 5 RLE 4 TUND 3 TXUBR 2 RXUBR 1 RCOMP 0 MFD • MFD: Management Frame sent Disable management done interrupt. • RCOMP: Receive Complete Disable receive complete interrupt. • RXUBR: Receive Used Bit Read Disable receive used bit read interrupt.
• PTZ: Pause Time Zero Disable pause time zero interrupt.
41.6.11 Interrupt Mask Register Name: EMAC_IMR Address: 0x400B0030 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 PTZ 12 PFR 11 HRESP 10 ROVR 9 – 8 – 7 TCOMP 6 TXERR 5 RLE 4 TUND 3 TXUBR 2 RXUBR 1 RCOMP 0 MFD • MFD: Management Frame sent Management done interrupt masked. • RCOMP: Receive Complete Receive complete interrupt masked. • RXUBR: Receive Used Bit Read Receive used bit read interrupt masked.
• PTZ: Pause Time Zero Pause time zero interrupt masked.
41.6.12 PHY Maintenance Register Name: EMAC_MAN Address: 0x400B0034 Access: Read-write 31 30 29 SOF 28 27 26 RW 23 PHYA 22 15 14 21 13 25 24 17 16 PHYA 20 REGA 19 18 CODE 12 11 10 9 8 3 2 1 0 DATA 7 6 5 4 DATA • DATA For a write operation this is written with the data to be written to the PHY. After a read operation this contains the data read from the PHY. • CODE: Must be written to 10. Reads as written.
41.6.13 Pause Time Register Name: EMAC_PTR Address: 0x400B0038 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 PTIME 7 6 5 4 PTIME • PTIME: Pause Time Stores the current value of the pause time register which is decremented every 512 bit times.
41.6.14 Hash Register Bottom Name: EMAC_HRB Address: 0x400B0090 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR • ADDR: Bits 31:0 of the hash address register. See “Hash Addressing” on page 1251. 41.6.
41.6.16 Specific Address 1 Bottom Register Name: EMAC_SA1B Address: 0x400B0098 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR • ADDR Least significant bits of the destination address. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received.
41.6.17 Specific Address 1 Top Register Name: EMAC_SA1T Address: 0x400B009C Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 ADDR 7 6 5 4 ADDR • ADDR The most significant bits of the destination address, that is bits 47 to 32.
41.6.18 Specific Address 2 Bottom Register Name: EMAC_SA2B Address: 0x400B00A0 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR • ADDR Least significant bits of the destination address. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received.
41.6.19 Specific Address 2 Top Register Name: EMAC_SA2T Address: 0x400B00A4 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 ADDR 7 6 5 4 ADDR • ADDR The most significant bits of the destination address, that is bits 47 to 32.
41.6.20 Specific Address 3 Bottom Register Name: EMAC_SA3B Address: 0x400B00A8 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR • ADDR Least significant bits of the destination address. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received.
41.6.21 Specific Address 3 Top Register Name: EMAC_SA3T Address: 0x400B00AC Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 ADDR 7 6 5 4 ADDR • ADDR The most significant bits of the destination address, that is bits 47 to 32.
41.6.22 Specific Address 4 Bottom Register Name: EMAC_SA4B Address: 0x400B00B0 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR • ADDR Least significant bits of the destination address. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received.
41.6.23 Specific Address 4 Top Register Name: EMAC_SA4T Address: 0x400B00B4 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 ADDR 7 6 5 4 ADDR • ADDR The most significant bits of the destination address, that is bits 47 to 32.
41.6.24 Type ID Checking Register Name: EMAC_TID Address: 0x400B00B8 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 TID 7 6 5 4 TID • TID: Type ID checking For use in comparisons with received frames TypeID/Length field.
41.6.25 User Input/Output Register Name: EMAC_USRIO Address: 0x400B00C0 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 CLKEN 0 RMII • RMII: Reduce MII When set, this bit enables the RMII operation mode. When reset, it selects the MII mode. • CLKEN: Clock Enable When set, this bit enables the transceiver input clock.
41.6.26 EMAC Statistic Registers These registers reset to zero on a read and stick at all ones when they count to their maximum value. They should be read frequently enough to prevent loss of data. The receive statistics registers are only incremented when the receive enable bit is set in the network control register. To write to these registers, bit 7 must be set in the network control register. The statistics register block contains the following registers. 41.6.26.
41.6.26.2Frames Transmitted OK Register Name: EMAC_FTO Address: 0x400B0040 Access: Read-write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 2 1 0 FTOK 15 14 13 12 FTOK 7 6 5 4 FTOK • FTOK: Frames Transmitted OK A 24-bit register counting the number of frames successfully transmitted, i.e., no underrun and not too many retries.
41.6.26.3Single Collision Frames Register Name: EMAC_SCF Address: 0x400B0044 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 SCF 7 6 5 4 SCF • SCF: Single Collision Frames A 16-bit register counting the number of frames experiencing a single collision before being successfully transmitted, i.e., no underrun.
41.6.26.4Multicollision Frames Register Name: EMAC_MCF Address: 0x400B0048 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 MCF 7 6 5 4 MCF • MCF: Multicollision Frames A 16-bit register counting the number of frames experiencing between two and fifteen collisions prior to being successfully transmitted, i.e., no underrun and not too many retries.
41.6.26.5Frames Received OK Register Name: EMAC_FRO Address: 0x400B004C Access: Read-write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 2 1 0 FROK 15 14 13 12 FROK 7 6 5 4 FROK • FROK: Frames Received OK A 24-bit register counting the number of good frames received, i.e., address recognized and successfully copied to memory.
41.6.26.6Frames Check Sequence Errors Register Name: EMAC_FCSE Address: 0x400B0050 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 FCSE • FCSE: Frame Check Sequence Errors An 8-bit register counting frames that are an integral number of bytes, have bad CRC and are between 64 and 1518 bytes in length (1536 if bit 8 set in network configuration register).
41.6.26.
41.6.26.8Deferred Transmission Frames Register Name: EMAC_DTF Address: 0x400B0058 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 DTF 7 6 5 4 DTF • DTF: Deferred Transmission Frames A 16-bit register counting the number of frames experiencing deferral due to carrier sense being active on their first attempt at transmission.
41.6.26.9Late Collisions Register Name: EMAC_LCOL Address: 0x400B005C Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 LCOL • LCOL: Late Collisions An 8-bit register counting the number of frames that experience a collision after the slot time (512 bits) has expired. A late collision is counted twice; i.e., both as a collision and a late collision.
41.6.26.10Excessive Collisions Register Name: EMAC_ECOL Address: 0x400B0060 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 EXCOL • EXCOL: Excessive Collisions An 8-bit register counting the number of frames that failed to be transmitted because they experienced 16 collisions.
41.6.26.11Transmit Underrun Errors Register Name: EMAC_TUND Address: 0x400B0064 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 TUND • TUND: Transmit Underruns An 8-bit register counting the number of frames not transmitted due to a transmit DMA underrun. If this register is incremented, then no other statistics register is incremented.
41.6.26.
41.6.26.13Receive Resource Errors Register Name: EMAC_RRE Address: 0x400B006C Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 RRE 7 6 5 4 RRE • RRE: Receive Resource Errors A 16-bit register counting the number of frames that were address matched but could not be copied to memory because no receive buffer was available.
41.6.26.14Receive Overrun Errors Register Name: EMAC_ROV Address: 0x400B0070 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 ROVR • ROVR: Receive Overrun An 8-bit register counting the number of frames that are address recognized but were not copied to memory due to a receive DMA overrun.
41.6.26.15Receive Symbol Errors Register Name: EMAC_RSE Address: 0x400B0074 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 RSE • RSE: Receive Symbol Errors An 8-bit register counting the number of frames that had rx_er asserted during reception.
41.6.26.
41.6.26.17Receive Jabbers Register Name: EMAC_RJA Address: 0x400B007C Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 RJB • RJB: Receive Jabbers An 8-bit register counting the number of frames received exceeding 1518 bytes (1536 if bit 8 set in network configuration register) in length and have either a CRC error, an alignment error or a receive symbol error.
41.6.26.18Undersize Frames Register Name: EMAC_USF Address: 0x400B0080 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 USF • USF: Undersize frames An 8-bit register counting the number of frames received less than 64 bytes in length but do not have either a CRC error, an alignment error or a receive symbol error.
41.6.26.19SQE Test Errors Register Name: EMAC_STE Address: 0x400B0084 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 SQER • SQER: SQE test errors An 8-bit register counting the number of frames where col was not asserted within 96 bit times (an interframe gap) of tx_en being deasserted in half duplex mode.
41.6.26.20Received Length Field Mismatch Register Name: EMAC_RLE Address: 0x400B0088 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 RLFM • RLFM: Receive Length Field Mismatch An 8-bit register counting the number of frames received that have a measured length shorter than that extracted from its length field.
42. True Random Number Generator (TRNG) 42.1 Description The True Random Number Generator (TRNG) passes the American NIST Special Publication 800-22 and Diehard Random Tests Suites. As soon as the TRNG is enabled (TRNG_CTRL register), the generator provides one 32-bit value every 84 clock cycles. Interrupt trng_int can be enabled through the TRNG_IER register (respectively disabled in TRNG_IDR).
42.3 True Random Number Generator (TRNG) User Interface Table 42-1.
42.3.1 TRNG Control Register Name: TRNG_CR Address: 0x400BC000 Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 KEY 23 22 21 20 KEY 15 14 13 12 KEY 7 6 5 4 3 2 1 0 – – – – – – – ENABLE • ENABLE: Enables the TRNG to provide random values 0: Disables the TRNG. 1: Enables the TRNG. • KEY: Security Key KEY = 0x524e47 (RNG in ASCII) This key is to be written when the ENABLE bit is set or cleared.
42.3.2 TRNG Interrupt Enable Register Name: TRNG_IER Address: 0x400BC010 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – DATRDY • DATRDY: Data Ready Interrupt Enable 0: No effect. 1: Enables the corresponding interrupt.
42.3.3 TRNG Interrupt Disable Register Name: TRNG_IDR Address: 0x400BC014 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – DATRDY • DATRDY: Data Ready Interrupt Disable 0: No effect. 1: Disables the corresponding interrupt.
42.3.4 TRNG Interrupt Mask Register Name: TRNG_IMR Address: 0x400BC018 Reset: 0x0000_0000 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – DATRDY • DATRDY: Data Ready Interrupt Mask 0: The corresponding interrupt is not enabled. 1: The corresponding interrupt is enabled.
42.3.5 TRNG Interrupt Status Register Name: TRNG_ISR Address: 0x400BC01C Reset: 0x0000_0000 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – DATRDY • DATRDY: Data Ready 0: Output data is not valid or TRNG is disabled. 1: New Random value is completed. DATRDY is cleared when this register is read.
42.3.6 TRNG Output Data Register Name: TRNG_ODATA Address: 0x400BC050 Reset: 0x0000_0000 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ODATA 23 22 21 20 ODATA 15 14 13 12 ODATA 7 6 5 4 ODATA • ODATA: Output Data The 32-bit Output Data register contains the 32-bit random data.
43. Analog-to-Digital Converter (ADC) 43.1 Description The ADC is based on a 12-bit Analog-to-Digital Converter (ADC) managed by an ADC Controller. Refer to the Block Diagram: Figure 43-1. It also integrates a 16-to-1 analog multiplexer, making possible the analog-to-digital conversions of 16 analog lines. The conversions extend from 0V to ADVREF.
43.
43.4 Signal Description Table 43-1. ADC Pin Description Pin Name Description VDDANA Analog power supply ADVREF Reference voltage(1) AD0 - AD15 Analog input channels ADTRG External trigger Note: 1. AD15 is not an actual pin but is connected to a temperature sensor. 43.5 Product Dependencies 43.5.1 Power Management The ADC Controller is not continuously clocked. The programmer must first enable the ADC Controller MCK in the Power Management Controller (PMC) before using the ADC Controller.
43.5.5 I/O Lines The pin ADTRG may be shared with other peripheral functions through the PIO Controller. In this case, the PIO Controller should be set accordingly to assign the pin ADTRG to the ADC function. Table 43-3.
43.6 Functional Description 43.6.1 Analog-to-digital Conversion The ADC uses the ADC Clock to perform conversions. Converting a single analog value to a 12-bit digital data requires Tracking Clock cycles as defined in the field TRACKTIM of the “ADC Mode Register” on page 1333 and Transfer Clock cycles as defined in the field TRANSFER of the same register. The ADC Clock frequency is selected in the PRESCAL field of the Mode Register (ADC_MR).
Figure 43-3. Sequence of ADC conversions when Tracking time < Conversion time Read the ADC_LCDR ADCClock Trigger event (Hard or Soft) ADC_ON Commands from controller to analog cell ADC_Start ADC_SEL CH0 CH1 LCDR CH3 CH2 CH0 CH1 CH2 DRDY Start Up Time & Tracking of CH0 Transfer Period Conversion of CH0 & Tracking of CH1 Transfer Period Conversion of CH1 & Tracking of CH2 Transfer Period Conversion of CH2 & Tracking of CH3 43.6.
Figure 43-4. EOCx and DRDY Flag Behavior Write the ADC_CR with START = 1 Read the ADC_CDRx Write the ADC_CR with START = 1 Read the ADC_LCDR CHx (ADC_CHSR) EOCx (ADC_SR) DRDY (ADC_SR) If the ADC_CDR is not read before further incoming data is converted, the corresponding Overrun Error (OVREx) flag is set in the Overrun Status Register (ADC_OVER). Likewise, new data converted when DRDY is high sets the GOVRE bit (General Overrun Error) in ADC_SR.
Figure 43-5.
43.6.5 Conversion Triggers Conversions of the active analog channels are started with a software or hardware trigger. The software trigger is provided by writing the Control Register (ADC_CR) with the START bit at 1. The hardware trigger can be one of the TIOA outputs of the Timer Counter channels, PWM Event line, or the external trigger input of the ADC (ADTRG). The hardware trigger is selected with the TRGSEL field in the Mode Register (ADC_MR).
order of channels and can program up to 16 conversions by sequence. The user is totally free to create a personal sequence, by writing channel numbers in ADC_SEQR1 and ADC_SEQR2. Not only can channel numbers be written in any sequence, channel numbers can be repeated several times. Only enabled sequence bitfields are converted, consequently to program a 15-conversion sequence, the user can simply put a disable in ADC_CHSR[15], thus disabling the 16THCH field of ADC_SEQR2. If all ADC channels (i.e.
Table 43-4. Input Pins and Channel Number in Single Ended Mode (Continued) Input Pins Channel Number AD5 CH5 AD6 CH6 AD7 CH7 AD8 CH8 AD9 CH9 AD10 CH10 AD11 CH11 AD12 CH12 AD13 CH13 AD14 CH14 AD15 CH15 Table 43-5. Input Pins and Channel Number In Differential Mode Input Pins Channel Number AD0-AD1 CH0 AD2-AD3 CH2 AD4-AD5 CH4 AD6-AD7 CH6 AD8-AD9 CH8 AD10-AD11 CH10 AD12-AD13 CH12 AD14-AD15 CH14 43.6.
To allow full range, analog offset of the ADC can be configured by the OFFSET bit of the Channel Offset Register (ADC_COR). The Offset is only available in Single Ended Mode. Table 43-7. Offset of the Sample and Hold Unit: OFFSET DIFF and Gain (G) OFFSET Bit OFFSET (DIFF = 0) 0 0 1 (G-1)Vrefin/2 OFFSET (DIFF = 1) 0 Figure 43-6.
43.6.10 ADC Timings Each ADC has its own minimal Startup Time that is programmed through the field STARTUP in the Mode Register, ADC_MR. A minimal Tracking Time is necessary for the ADC to guarantee the best converted final value between two channel selections. This time has to be programmed through the TRACKTIM bit field in the Mode Register, ADC_MR.
43.6.12 Fault Output The ADC Controller internal fault output is directly connected to PWM fault input. Fault output may be asserted according to the configuration of ADC_EMR (Extended Mode Register) and ADC_CWR (Compare Window Register) and converted values. When the Compare occurs, the ADC fault output generates a pulse of one Master Clock Cycle to the PWM fault input. This fault line can be enabled or disabled within PWM.
43.7 Analog-to-Digital Converter (ADC) User Interface Any offset not listed in Table 43-8 must be considered as “reserved”. Table 43-8.
43.7.1 ADC Control Register Name: ADC_CR Address: 0x400C0000 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 START 0 SWRST • SWRST: Software Reset 0 = No effect. 1 = Resets the ADC simulating a hardware reset. • START: Start Conversion 0 = No effect. 1 = Begins analog-to-digital conversion.
43.7.2 ADC Mode Register Name: ADC_MR Address: 0x400C0004 Access: Read-write 31 USEQ 30 – 29 23 ANACH 22 – 21 15 14 13 28 27 26 TRANSFER 25 24 17 16 TRACKTIM 20 19 18 SETTLING STARTUP 12 11 10 9 8 3 2 TRGSEL 1 0 TRGEN PRESCAL 7 FREERUN 6 FWUP 5 SLEEP 4 LOWRES This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” on page 1353. • TRGEN: Trigger Enable Value Name Description 0 DIS Hardware triggers are disabled.
• FWUP: Fast Wake Up Value Name Description 0 OFF Normal Sleep Mode: The sleep mode is defined by the SLEEP bit 1 ON Fast Wake Up Sleep Mode: The Voltage reference is ON between conversions and ADC Core is OFF • FREERUN: Free Run Mode Value Name Description 0 OFF Normal Mode 1 ON Free Run Mode: Never wait for any trigger.
• ANACH: Analog Change Value Name Description 0 NONE No analog change on channel switching: DIFF0, GAIN0 and OFF0 are used for all channels 1 ALLOWED Allows different analog settings for each channel. See ADC_CGR and ADC_COR Registers • TRACKTIM: Tracking Time Tracking Time = (TRACKTIM + 1) * ADCClock periods. • TRANSFER: Transfer Period Transfer Period = (TRANSFER * 2 + 3) ADCClock periods.
43.7.3 ADC Channel Sequence 1 Register Name: ADC_SEQR1 Address: 0x400C0008 Access: Read-write 31 30 29 28 27 26 USCH8 23 22 21 20 19 18 USCH6 15 14 13 6 24 17 16 9 8 1 0 USCH5 12 11 10 USCH4 7 25 USCH7 USCH3 5 4 USCH2 3 2 USCH1 This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” on page 1353.
43.7.4 ADC Channel Sequence 2 Register Name: ADC_SEQR2 Address: 0x400C000C Access: Read-write 31 30 29 28 27 26 USCH16 23 22 21 20 19 18 USCH14 15 14 13 6 24 17 16 9 8 1 0 USCH13 12 11 10 USCH12 7 25 USCH15 USCH11 5 4 USCH10 3 2 USCH9 This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” on page 1353.
43.7.5 ADC Channel Enable Register Name: ADC_CHER Address: 0x400C0010 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 CH15 14 CH14 13 CH13 12 CH12 11 CH11 10 CH10 9 CH9 8 CH8 7 CH7 6 CH6 5 CH5 4 CH4 3 CH3 2 CH2 1 CH1 0 CH0 This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” on page 1353. • CHx: Channel x Enable 0 = No effect. 1 = Enables the corresponding channel.
43.7.6 ADC Channel Disable Register Name: ADC_CHDR Address: 0x400C0014 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 CH15 14 CH14 13 CH13 12 CH12 11 CH11 10 CH10 9 CH9 8 CH8 7 CH7 6 CH6 5 CH5 4 CH4 3 CH3 2 CH2 1 CH1 0 CH0 This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” on page 1353. • CHx: Channel x Disable 0 = No effect. 1 = Disables the corresponding channel.
43.7.7 ADC Channel Status Register Name: ADC_CHSR Address: 0x400C0018 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 CH15 14 CH14 13 CH13 12 CH12 11 CH11 10 CH10 9 CH9 8 CH8 7 CH7 6 CH6 5 CH5 4 CH4 3 CH3 2 CH2 1 CH1 0 CH0 • CHx: Channel x Status 0 = Corresponding channel is disabled. 1 = Corresponding channel is enabled.
43.7.8 ADC Last Converted Data Register Name: ADC_LCDR Address: 0x400C0020 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 1 0 CHNB 7 6 LDATA 5 4 3 2 LDATA • LDATA: Last Data Converted The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed.
43.7.
43.7.
43.7.
43.7.12 ADC Interrupt Status Register Name: ADC_ISR Address: 0x400C0030 Access: Read-only 31 – 30 – 29 – 28 RXBUFF 27 ENDRX 26 COMPE 25 GOVRE 24 DRDY 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 EOC15 14 EOC14 13 EOC13 12 EOC12 11 EOC11 10 EOC10 9 EOC9 8 EOC8 7 EOC7 6 EOC6 5 EOC5 4 EOC4 3 EOC3 2 EOC2 1 EOC1 0 EOC0 • EOCx: End of Conversion x 0 = Corresponding analog channel is disabled, or the conversion is not finished.
43.7.13 ADC Overrun Status Register Name: ADC_OVER Address: 0x400C003C Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 OVRE15 14 OVRE14 13 OVRE13 12 OVRE12 11 OVRE11 10 OVRE10 9 OVRE9 8 OVRE8 7 OVRE7 6 OVRE6 5 OVRE5 4 OVRE4 3 OVRE3 2 OVRE2 1 OVRE1 0 OVRE0 • OVREx: Overrun Error x 0 = No overrun error on the corresponding channel since the last read of ADC_OVER.
43.7.14 ADC Extended Mode Register Name: ADC_EMR Address: 0x400C0040 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 TAG 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 12 11 – 10 – 9 CMPALL 8 – 7 6 4 3 – 2 – 1 0 CMPFILTER 5 CMPSEL CMPMODE This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” on page 1353.
43.7.15 ADC Compare Window Register Name: ADC_CWR Address: 0x400C0044 Access: Read-write 31 – 30 – 29 – 28 – 23 22 21 20 27 26 25 24 17 16 9 8 1 0 HIGHTHRES 19 18 11 10 HIGHTHRES 15 – 14 – 13 – 12 – 7 6 5 4 LOWTHRES 3 2 LOWTHRES This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” on page 1353. • LOWTHRES: Low Threshold Low threshold associated to compare settings of ADC_EMR register.
43.7.16 ADC Channel Gain Register Name: ADC_CGR Address: 0x400C0048 Access: Read-write 31 30 29 GAIN15 23 22 21 GAIN11 15 27 14 20 13 19 6 12 5 25 18 11 17 4 16 GAIN8 10 9 GAIN5 GAIN2 24 GAIN12 GAIN9 GAIN6 GAIN3 26 GAIN13 GAIN10 GAIN7 7 28 GAIN14 3 2 GAIN1 8 GAIN4 1 0 GAIN0 This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” on page 1353. • GAINx: Gain for channel x Gain applied on input of analog-to-digital converter.
43.7.17 ADC Channel Offset Register Name: ADC_COR Address: 0x400C004C Access: Read-write 31 DIFF15 30 DIFF14 29 DIFF13 28 DIFF12 27 DIFF11 26 DIFF10 25 DIFF9 24 DIFF8 23 DIFF7 22 DIFF6 21 DIFF5 20 DIFF4 19 DIFF3 18 DIFF2 17 DIFF1 16 DIFF0 15 OFF15 14 OFF14 13 OFF13 12 OFF12 11 OFF11 10 OFF10 9 OFF9 8 OFF8 7 OFF7 6 OFF6 5 OFF5 4 OFF4 3 OFF3 2 OFF2 1 OFF1 0 OFF0 This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” on page 1353.
43.7.18 ADC Channel Data Register Name: ADC_CDRx [x=0..15] Address: 0x400C0050 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 10 9 8 7 6 5 4 1 0 DATA 3 2 DATA • DATA: Converted Data The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed.
43.7.19 ADC Analog Control Register Name: ADC_ACR Address: 0x400C0094 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 7 – 6 – 5 – 4 TSON 3 – 2 – 1 – 8 IBCTL 0 – This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” on page 1353. • TSON: Temperature Sensor On 0 = temperature sensor is off. 1 = temperature sensor is on.
43.7.20 ADC Write Protect Mode Register Name: ADC_WPMR Address: 0x400C00E4 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 – – – – – – – WPEN • WPEN: Write Protect Enable 0 = Disables the Write Protect if WPKEY corresponds to 0x414443 (“ADC” in ASCII). 1 = Enables the Write Protect if WPKEY corresponds to 0x414443 (“ADC” in ASCII).
43.7.21 ADC Write Protect Status Register Name: ADC_WPSR Address: 0x400C00E8 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 11 10 9 8 WPVSRC 15 14 13 12 WPVSRC 7 6 5 4 3 2 1 0 – – – – – – – WPVS • WPVS: Write Protect Violation Status 0 = No Write Protect Violation has occurred since the last read of the ADC_WPSR register. 1 = A Write Protect Violation has occurred since the last read of the ADC_WPSR register.
44. Digital-to-Analog Converter Controller (DACC) 44.1 Description The Digital-to-Analog Converter Controller (DACC) offers up to 2 analog outputs, making it possible for the digitalto-analog conversion to drive up to 2 independent analog lines. The DACC supports 12-bit resolution. Data to be converted are sent in a common register for all channels. External triggers or free running mode are configurable. The DACC integrates a Sleep Mode and connects with a PDC channel.
44.3 Block Diagram Figure 44-1. Digital-to-Analog Converter Controller Block Diagram DAC Controller Trigger Selection DATRG Control Logic Interrupt Controller Analog Cell DAC Core PDC 44.4 Sample & Hold Sample & Hold AHB DAC0 DAC1 User Interface Signal Description Table 44-1.
44.5 Product Dependencies 44.5.1 Power Management The DACC becomes active as soon as a conversion is requested and at least one channel is enabled. The DACC is automatically deactivated when no channels are enabled. For power saving options see Section 44.6.6 ”Sleep Mode”. 44.5.2 Interrupt Sources The DACC interrupt line is connected on one of the internal sources of the interrupt controller. Using the DACC interrupt requires the interrupt controller to be programmed first. Table 44-2.
44.6 Functional Description 44.6.1 Digital-to-Analog Conversion The DACC uses the master clock (MCK) divided by two to perform conversions. This clock is named DACC Clock. Once a conversion starts the DACC takes 25 clock periods to provide the analog result on the selected analog output. 44.6.2 Conversion Results When a conversion is completed, the resulting analog value is available at the selected DACC channel output and the EOC bit in the DACC Interrupt Status Register, is set.
44.6.5 Channel Selection There are two means by which to select the channel to perform data conversion. By default, to select the channel where to convert the data, is to use the USER_SEL field of the DACC Mode Register. Data requests will merely be converted to the channel selected with the USER_SEL field. A more flexible option to select the channel for the data to be converted to is to use the tag mode, setting the TAG field of the DACC Mode Register to 1.
Figure 44-2.
44.6.8 Write Protection Registers In order to provide security to the DACC, a write protection system has been implemented. The write protection mode prevents the writing of certain registers. When this mode is enabled and one of the protected registers is written, an error is generated in the DACC Write Protect Status Register and the register write request is canceled.
44.7 Analog Converter Controller (DACC) User Interface Table 44-3.
44.7.1 DACC Control Register Name: DACC_CR Address: 0x400C8000 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 SWRST • SWRST: Software Reset 0: No effect. 1: Resets the DACC simulating a hardware reset.
44.7.2 DACC Mode Register Name: DACC_MR Address: 0x400C8004 Access: Read-write 31 – 30 – 29 28 23 – 22 – 21 MAXS 20 TAG 15 14 13 12 27 26 25 24 19 – 18 – 17 11 10 9 8 3 2 TRGSEL 1 0 TRGEN STARTUP 16 USER_SEL REFRESH 7 – 6 FASTWKUP 5 SLEEP 4 WORD This register can only be written if the WPEN bit is cleared in DACC Write Protect Mode Register. • TRGEN: Trigger Enable Value Name Description 0 DIS External trigger mode disabled. DACC in free running mode.
• SLEEP: Sleep Mode SLEEP Selected Mode 0 Normal Mode 1 Sleep Mode 0: Normal Mode: The DAC Core and reference voltage circuitry are kept ON between conversions. After reset, the DAC is in normal mode but with the voltage reference and the DAC core off. For the first conversion, a startup time must be defined in the STARTUP field. Note that in this mode, STARTUP time is only required once, at start up. 1: Sleep Mode: The DAC Core and reference voltage circuitry are OFF between conversions.
• STARTUP: Startup Time Selection Value Name 0 0 1 Description Value Name Description 0 periods of DACClock 32 2048 2048 periods of DACClock 8 8 periods of DACClock 33 2112 2112 periods of DACClock 2 16 16 periods of DACClock 34 2176 2176 periods of DACClock 3 24 24 periods of DACClock 35 2240 2240 periods of DACClock 4 64 64 periods of DACClock 36 2304 2304 periods of DACClock 5 80 80 periods of DACClock 37 2368 2368 periods of DACClock 6 96 96 periods of DACCloc
44.7.3 DACC Channel Enable Register Name: DACC_CHER Address: 0x400C8010 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 1 CH1 0 CH0 This register can only be written if the WPEN bit is cleared in DACC Write Protect Mode Register. • CHx: Channel x Enable 0: No effect. 1: Enables the corresponding channel.
44.7.4 DACC Channel Disable Register Name: DACC_CHDR Address: 0x400C8014 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 1 CH1 0 CH0 This register can only be written if the WPEN bit is cleared in DACC Write Protect Mode Register. • CHx: Channel x Disable 0: No effect. 1: Disables the corresponding channel.
44.7.5 DACC Channel Status Register Name: DACC_CHSR Address: 0x400C8018 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 1 CH1 0 CH0 • CHx: Channel x Status 0: Corresponding channel is disabled. 1: Corresponding channel is enabled.
44.7.6 DACC Conversion Data Register Name: DACC_CDR Address: 0x400C8020 Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 DATA 23 22 21 20 DATA 15 14 13 12 DATA 7 6 5 4 DATA • DATA: Data to Convert When the WORD bit in DACC_MR register is cleared, only DATA[15:0] is used else DATA[31:0] is used to write 2 data to be converted.
44.7.
44.7.8 DACC Interrupt Disable Register Name: DACC_IDR Address: 0x400C8028 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 TXBUFE 2 ENDTX 1 EOC 0 TXRDY • TXRDY: Transmit Ready Interrupt Disable.
44.7.
44.7.10 DACC Interrupt Status Register Name: DACC_ISR Address: 0x400C8030 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 TXBUFE 2 ENDTX 1 EOC 0 TXRDY • TXRDY: Transmit Ready Interrupt Flag 0: DACC is not ready to accept new conversion requests. 1: DACC is ready to accept new conversion requests.
44.7.11 DACC Analog Current Register Name: DACC_ACR Address: 0x400C8094 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 IBCTLDACCORE 7 – 6 – 5 – 4 – 3 2 1 IBCTLCH1 0 IBCTLCH0 This register can only be written if the WPEN bit is cleared in DACC Write Protect Mode Register. • IBCTLCHx: Analog Output Current Control Allows to adapt the slew rate of the analog output.
44.7.12 DACC Write Protect Mode Register Name: DACC_WPMR Address: 0x400C80E4 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 WPEN WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 – 6 – 5 – 4 – • WPEN: Write Protect Enable 0: Disables the Write Protect if WPKEY corresponds to 0x444143 (“DAC” in ASCII). 1: Enables the Write Protect if WPKEY corresponds to 0x444143 (“DAC” in ASCII).
44.7.13 DACC Write Protect Status Register Name: DACC_WPSR Address: 0x400C80E8 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 WPROTADDR 10 9 8 7 – 6 – 5 – 4 – 2 – 1 – 0 WPROTERR 3 – • WPROTADDR: Write protection error address Indicates the address of the register write request which generated the error. • WPROTERR: Write protection error Indicates a write protection error.
45. Electrical Characteristics 45.1 Absolute Maximum Ratings Table 45-1. Absolute Maximum Ratings* Operating Temperature (Industrial).....................-40°C to +85°C *NOTICE: Storage Temperature........................................-60°C to +150°C Voltage on Input Pins with Respect to Ground (except VBUS)...............-0.3V to +4.0V Voltage on VBUS Pin with Respect to Ground........................................-0.3V to +6.0V Maximum Operating Voltage (VDDCORE).................................
45.2 DC Characteristics The following characteristics are applicable to the operating temperature range TA = -40°C to 85°C, unless otherwise specified. Table 45-2. DC Characteristics Symbol Parameter VDDCORE Conditions Min Typ Max Unit DC Supply Core 1.62 1.8 1.95 V VDDIO DC Supply I/Os 1.62 3.3 3.6 V VDDBU Backup I/O Lines Power Supply 1.62 3.6 V VDDUTMII USB UTMI+ Interface Power Supply 3.0 3.6 V VDDPLL PLL A, UPLL and Main Oscillator Supply 1.62 1.
Table 45-2. Symbol DC Characteristics (Continued) Parameter Conditions Min Typ Max Unit 1.62V < VDDIO < 1.95V; VOL = 0.4V - Group 1(2) 8 (3) 4 - Group 2 3.0V < VDDIO < 3.6V; VOL = 0.4V Sink Current IOL - Group 1(2) 9 (3) 6 - Group 2 mA 1.62V < VDDIO < 3.6V; VOL = 0.4V - NRST, TDO 2 Relaxed Mode: 3.0V < VDDIO < 3.6V; VOL = 0.
Table 45-3. 1.8V Voltage Regulator Characteristics Symbol Parameter VDDIN DC Input Voltage Range VDDOUT DC Output Voltage VO(accuracy) Output Voltage Accuracy ILOAD Maximum DC Output Current ILOAD-START Maximum Peak Current during startup (3) VDROPOUT Dropout Voltage VDDIN = 1.8V ILOAD = 60 mA VLINE Line Regulation VLINE-TR VLOAD VLOAD-TR IQ Conditions Min Typ Max Unit 1.8 3.3 3.6 V Normal Mode 1.8 Standby Mode 0 V ILOAD = 0.5–150 mA -3 3 VDDIN > 2.2V 150 VDDIN ≤ 2.
Table 45-4. Symbol Core Power Supply Brownout Detector Characteristics Parameter Conditions (1) Min Typ Max Unit 1.52 1.55 1.58 V 25 38 mV 1.50 1.59 V VT- Supply Falling Threshold Vhys- Hysteresis VT- VT+ Supply Rising Threshold 1.
Figure 45-2. VDDUTMI Supply Monitor VDDIO VT + Vhys VT Reset Table 45-6. Threshold Selection Digital Code Threshold Min (V) Threshold Typ (V) Threshold Max (V) 0000 1.881 1.9 1.919 0001 1.980 2.0 2.020 0010 2.079 2.1 2.121 0011 2.178 2.2 2.222 0100 2.277 2.3 2.323 0101 2.376 2.4 2.424 0110 2.475 2.5 2.525 0111 2.574 2.6 2.626 1000 2.673 2.7 2.727 1001 2.772 2.8 2.828 1010 2.871 2.9 2.929 1011 2.970 3.0 3.030 1100 3.069 3.1 3.131 1101 3.168 3.
Figure 45-3. Zero-Power-on Reset Characteristics VDDIO VT+ VT- Reset Table 45-8. Symbol DC Flash Characteristics Parameter IDD(standby) Standby current Conditions Typ Max @ 25°C onto VDDCORE = 1.8V <1 1.5 @ 85°C onto VDDCORE = 1.8V 14 40 @ 25°C onto VDDCORE = 1.95V <1 1.8 @ 85°C onto VDDCORE = 1.95V 15 50 Maximum Read Frequency onto VDDCORE = 1.8V @ 25 °C 15 20 Maximum Read Frequency onto VDDCORE = 1.95V @ 25 °C 20 25 Maximum Read Frequency onto VDDCORE = 1.8V @ 25 °C 7.
45.3 45.3.1 Power Consumption Power consumption of the device according to the different low-power mode capabilities (Backup, Wait, Sleep) and Active mode Power consumption on power supply in different modes: Backup, Wait, Sleep, and Active Power consumption by peripheral: calculated as the difference in current measurement after having enabled then disabled the corresponding clock Backup Mode Current Consumption The Backup mode configuration and measurements are defined as follows. 45.3.1.
45.3.2 Wait and Sleep Mode Current Consumption The Wait Mode and Sleep Mode configuration and measurements are defined below. 45.3.2.1 Sleep Mode All power supplies are powered Core clock OFF Master Clock (MCK) running at various frequencies with PLLA or the fast RC oscillator Fast startup through pins WKUP0–15 Current measurement on AMP1 (VDDOUT = VDDCORE + VDDPLL) All peripheral clocks deactivated Figure 45-5. Measurement Setup for Sleep Mode VDDBU VDDANA VDDIO AMP2 3.
Figure 45-6. Current Consumption in Sleep Mode (AMP1) versus Master Clock Ranges (refer to Table 45-10) 24 VDOUT (IDDCORE + IDDPLL) in mA 22 20 18 16 14 12 10 8 6 4 2 0 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 84 88 92 96 Processor and Peripheral Clocks in MHz Table 45-10. Sleep Mode Current Consumption versus Master Clock (MCK) Variation Core Clock/MCK (MHz) AMP1 (IDDOUT) Consumption Unit 96 45.9 mA 84 29.4 mA 72 25.6 mA 60 21.7 mA 48 17.8 mA 36 14.
45.3.2.2 Wait Mode All power supplies are powered Core Clock and Master Clock Stopped Current measurement on AMP1, AMP2 and AMP3 All peripheral clocks deactivated Figure 45-7. Measurement Setup for Wait Mode VDDBU VDDANA VDDIO AMP2 3.3V VDDUTMI AMP3 VDDIN AMP1 Voltage Regulator VDDOUT VDDCORE VDDPLL Table 45-11 gives current consumption in typical conditions. Table 45-11.
Figure 45-8. Active Mode Measurement Setup for VDDCORE at 1.8V VDDBU VDDANA VDDIO AMP2 3.3V VDDUTMI VDDIN AMP1 Voltage Regulator VDDOUT VDDCORE VDDPLL Figure 45-9. Active Mode Measurement Setup for VDDCORE at 1.62V VDDBU VDDANA VDDIO AMP2 3.3V VDDUTMI VDDIN Voltage Regulator VDDOUT AMP1 1.62V VDDCORE VDDPLL The following tables give Active mode current consumption in typical conditions.
Table 45-12. Active Power Consumption with VDDCORE @ 1.8V Running from Flash Memory or SRAM CoreMark (1) 128-bit Flash Access 64-bit Flash Access(1) SRAM Core Clock (MHz) AMP1 AMP2 AMP1 AMP2 AMP1 AMP2 84 63.25 76.47 56.08 70.89 64.20 77.50 72 57.63 70.83 51.71 66.86 49.40 62.80 60 53.66 65.48 47.79 62.72 41.80 55.20 48 46.55 57.57 44.70 55.65 34.20 47.60 32 35.44 47.75 31.71 45.21 24.30 38.00 24 29.59 42.44 26.11 39.19 18.90 32.60 12 16.55 32.02 16.
Table 45-13. Active Power Consumption with VDDCORE @ 1.62V Running from Flash Memory or SRAM CoreMark (2) 128-bit Flash Access 64-bit Flash Access(2) SRAM Core Clock (MHz) AMP1 AMP2(1) AMP1 AMP2(1) AMP1 AMP2(1) 84 57.66 12.32 51.41 12.32 50.10 13.30 72 51.46 12.32 46.18 12.25 43.60 13.30 60 45.98 12.27 41.97 12.30 36.80 13.30 48 40.90 12.28 36.08 12.34 30.10 13.30 32 31.45 12.32 27.94 12.26 21.30 13.30 24 24.73 12.39 22.32 12.30 16.50 13.30 12 15.
45.3.4 Peripheral Power Consumption in Active Mode Table 45-14. Power Consumption on VDDCORE(1) Peripheral 1392 Consumption (Typ) Unit UART 11.96 µA/MHz PIOA 9.23 µA/MHz PIOB 9.63 µA/MHz PIOC 10.16 µA/MHz PIOD 9.72 µA/MHz PIOE 11.20 µA/MHz PIOF 2.58 µA/MHz USART0 31.15 µA/MHz USART1 24.64 µA/MHz USART2 25.31 µA/MHz USART3 23.98 µA/MHz HSMCI 30.54 µA/MHz PWM 65.76 µA/MHz SSC 15.00 µA/MHz TWI0 17.03 µA/MHz TWI1 17.29 µA/MHz SPI0 3.55 µA/MHz SPI1 2.
Table 45-14. Power Consumption on VDDCORE(1) Peripheral USB Note: 1. Consumption (Typ) Unit 73.63 µA/MHz VDDIO = 3.3V, VDDCORE = 1.
45.4 Crystal Oscillators Characteristics 45.4.1 32 kHz RC Oscillator Characteristics Table 45-15. 32 kHz RC Oscillator Characteristics Symbol Parameter fOSC Conditions Min Typ Max Unit RC Oscillator Frequency 20 32 44 kHz Frequency Supply Dependency -3 3 %/V -11 11 % 55 % 100 µs 870 nA Frequency Temperature Dependency Duty Duty Cycle tSTART Startup Time IDDON Current Consumption 45.4.2 Over temperature range -40 to 85 °C versus TA 25°C 45 After startup time Temp.
45.4.3 32.768 kHz Crystal Oscillator Characteristics Table 45-17. 32.
45.4.4 32.768 kHz Crystal Characteristics Table 45-18. 45.4.5 Crystal Characteristics Symbol Parameter Conditions ESR Equivalent Series Resistor (RS) Cm Motional capacitance CSHUNT Shunt capacitance Min Crystal @ 32.768 kHz Typ Max Unit 50 100 kΩ 0.6 3 fF 0.6 2 pF 32.768 kHz XIN32 Clock Input Characteristics in Bypass Mode Table 45-19.
45.4.6 3 to 20 MHz Crystal Oscillator Characteristics Table 45-20. 3 to 20 MHz Crystal Oscillator Characteristics Symbol Parameter Conditions Min Typ Max Unit fOSC Operating Frequency Normal mode with crystal 3 16 20 MHz fOSC(bypass) Operating Frequency In Bypass Mode External Clock on XIN 50 MHz Vrip(VDDPLL) Supply Ripple Voltage (on VDDPLL) RMS value, 10 kHz to 10 MHz 30 mV 60 % Duty Cycle tSTART 40 Startup Time 50 3 MHz, CSHUNT = 3 pF 14.
45.4.7 3 to 20 MHz Crystal Characteristics Table 45-21. Symbol ESR 45.4.8 Crystal Characteristics Parameter Conditions Equivalent Series Resistor (RS) Min Typ Fundamental @ 3 MHz 200 Fundamental @ 8 MHz 100 Fundamental @ 12 MHz 80 Fundamental @ 16 MHz 80 Fundamental @ 20 MHz 50 Unit Ω Cm Motional capacitance 8 fF CSHUNT Shunt capacitance 7 pF 3 to 20 MHz XIN Clock Input Characteristics in Bypass Mode Table 45-22.
45.4.9 Crystal Oscillator Design Consideration Information 45.4.9.1 Choosing a Crystal When choosing a crystal for the 32.768 kHz Slow Clock Oscillator or for the 3–20 MHz Oscillator, several parameters must be taken into account. Important parameters between crystal and SAM3 specifications are as follows: Load Capacitance Ccrystal is the equivalent capacitor value the oscillator must “show” to the crystal in order to oscillate at the target frequency.
45.5 UPLL, PLLA Characteristics Table 45-23. Supply Voltage Phase Lock Loop Characteristics Symbol Parameter VDDPLL Supply Voltage Vrip(VDDPLL) Allowable Voltage Ripple Table 45-24. PLLA Characteristics Symbol Parameter fIN Input Frequency fOUT Output Frequency IPLL Current Consumption Conditions Min Typ Max Unit 1.6 1.8 1.95 V RMS value 10 kHz to 10 MHz 30 RMS value > 10 MHz 10 Conditions Min Typ Max Unit 1 40 MHz 80 240 MHz Active mode @ 96 MHz @ 1.8V 1 1.
45.6 USB On-the-Go High Speed Port 45.6.1 Typical Connection For a typical connection, refer to Section 39. “USB On-The-Go Interface (UOTGHS)”. For an external connection of the VBG pin, see the figure below. Figure 45-16. External Connection of VBG Pin 6K8 ± 1% Ω VBG 10 pF GND 45.6.2 Electrical Characteristics Table 45-26. Electrical Parameters Symbol Parameter Conditions Min Typ Max Unit RPUI Bus Pull-up Resistor on Upstream Port (idle bus) In FS or HS Mode 1.
45.6.4 Dynamic Power Consumption Table 45-28. Dynamic Power Consumption Symbol Parameter IBIAS Bias current consumption on VBG IVDDUTMII Note: 1402 Conditions Min Typ Max Unit 0.7 0.
45.7 12-bit ADC Characteristics Table 45-29. Analog Power Supply Characteristics Symbol Parameter VDDIN ADC Analog Supply Vrip(max) Max. Voltage Ripple Conditions Min Typ Max Unit 12-bit or 10-bit resolution 2.4 3.0 3.6 V 10-bit resolution 2.0 Sleep Mode Current Consumption IVDDIN Fast Wake Up Mode Normal Mode (ADC_ACR.IBCTL = 00) (1) Normal Mode (ADC_ACR.IBCTL = 01)(2) Notes: 3.6 V 20 mV 0.1 1 µA 1.8 2.6 mA 4.7 7.
45.7.1 Static Performance Characteristics Minimal code = 0 Maximal code = 4095 ADC resolution = 12 bits (4096) Temperature range -40 to 100 °C fADC = 2 MHz, ADC_ACR.IBCTL = 01 In Table 45-32 and Table 45-33, the LSB is relative to analog scale for 12-bit ADC: Single-ended (ex: ADVREF = 3.0V), ̶ Gain = 1, LSB = (3.0V / 4096) = 732 µV ̶ Gain = 2, LSB = (1.5V / 4096) = 366 µV ̶ Gain = 4, LSB = (750mV / 4096) = 183 µV Differential (ex: ADVREF = 3.0V), ̶ Gain = 0.5, LSB = (6.
Table 45-33. Symbol Gain Error, Offset Error, 12-bit mode Parameter Conditions(1) Min Typ Max Unit VDDIN 2.4V to < 3.0V -1.56 -0.56 +0.29 % -64 -23 +12 LSB -1.56 -0.56 +0.29 % -64 -23 +12 LSB -1.56 -0.56 +0.29 % -64 -23 +12 LSB -1.56 -0.56 +0.29 % -64 -23 +12 LSB 0 +11.5 +64 LSB -54 +11.5 +80 LSB -22 +11.5 +48 LSB -30 +11.5 +56 LSB DRAFT 1405 Differential, DIFF = 1, OFF = x, GAIN = xx VDDIN 2.4V to < 3.
Table 45-34. Symbol Static Performance Characteristics - 10-bit Mode (1) Parameter Conditions Min Resolution INL Integral Non-linearity DNL Differential Non-linearity EO(uncalib) EG(uncalib) Note: 1406 Typ Max 10 Unit Bit -1 ±0.5 +1 LSB No missing code -1 ±0.5 +1 LSB Offset Error All gain, Differential or Single-ended, no calibration -8 +3 +20 LSB Gain Error without calibration All gain, Differential or Single-ended, no calibration -16 -6 +3 LSB 1.
45.7.2 Dynamic Performance Characteristics The following conditions apply for the characteristics provided in Table 45-35 and Table 45-36: ADC resolution = 12 bits Temperature range -40 to 100 °C fADC = 20 MHz ADC_ACR.IBCTL = 01 fs = 1 MHz fIN = 127 kHz FFT using 1024 points or more Frequency band = [1–500 kHz] Nyquist conditions fulfilled Table 45-35.
45.7.2.1 Track and Hold Time versus Source Output Impedance The following figure gives a simplified acquisition path. Figure 45-18. Simplified Acquisition Path ADC Input Mux. Sample & Hold 12-bit ADC ZSOURCE RON Csample During the tracking phase the ADC needs to track the input signal during the tracking time shown below: 10-bit mode: tTRACK = 0.042 × ZSOURCE + 160 12-bit mode: tTRACK = 0.054 × ZSOURCE + 205 With tTRACK expressed in ns and ZSOURCE expressed in ohms.
Table 45-37. fADC = ADC clock (MHz) ZSOURCE (kΩ) for 12 bits ZSOURCE (kΩ) for 10 bits 3.56 74 97 3.20 83 108 2.91 92 119 2.67 100 130 2.46 109 141 2.29 118 152 2.13 126 164 2.00 135 175 1.00 274 353 Table 45-38. Symbol Analog Inputs Parameter Conditions (1) VIR Input Voltage Range Ilkg Input Leakage Current Min 0 Input Capacitance Ci Note: 45.7.3 Source Impedance Values (Continued) 1. Typ Max Unit VADVREF V ±0.
45.8 Temperature Sensor The temperature sensor is connected to channel 15 of the ADC. The temperature sensor provides an output voltage (VO_TS) that is proportional to absolute temperature (PTAT). VO_TS linearly varies with a temperature slope dVO_TS/dT = 2.65 mV/°C. VO_TS equals 0.8V at TA 27°C, with a ±15% accuracy. The VO_TS slope versus temperature dVO_TS/dT = 2.65 mV/°C only shows a ±5% slight variation over process, mismatch and supply voltage.
45.9 12-bit DAC Characteristics Table 45-40. Analog Power Supply Characteristics Symbol Parameter Conditions VDDIN Analog Supply Vrip(VDDIN) Max. Voltage Ripple Current Consumption IVDDIN Table 45-41. Min Parameter fDAC Clock Frequency tCP_DAC Clock Period fS Sampling Frequency Notes: Unit 3.6 V 20 mV 1 µA 2.4 RMS value, 10 kHz to 20 MHz Sleep Mode 0.05 Fast Wake Up 1.8 mA Normal Mode with 1 Output ON (DACC_ACR.IBCTLDACCORE = 01, DACC_ACR.IBCTLCHx = 10) 3.4 4.3 7.
Table 45-44. Symbol 1412 Parameter Conditions Voltage Range VOR Note: Analog Outputs 1. Min (1/6) × VADVREF Typ (1) – Max (5/6) × VADVREF(1) Unit V External voltage reference for DAC is ADVREF. See the ADC voltage reference characteristics in Table 45-31, “External Voltage Reference Input,” on page 1403.
45.10 AC Characteristics 45.10.1 Master Clock Characteristics Table 45-45. Master Clock Waveform Parameters Symbol Parameter 1/(tCPMCK) Master Clock Frequency Conditions Min Max VDDCORE @ 1.62V 78 VDDCORE @ 1.8V 90 Unit MHz 45.10.2 I/O Characteristics Criteria used to define the maximum frequency of the I/Os: Output duty cycle (40%–60%) Minimum output swing: 100 mV to VDDIO - 100 mV Addition of rising and falling time inferior to 75% of the period Table 45-46.
45.10.3 SPI Characteristics Figure 45-19. SPI Master Mode with (CPOL = NCPHA = 0) or (CPOL = NCPHA= 1) SPCK SPI1 SPI0 MISO SPI2 MOSI Figure 45-20. SPI Master Mode with (CPOL = 0 and NCPHA = 1) or (CPOL = 1 and NCPHA = 0) SPCK SPI4 SPI3 MISO SPI5 MOSI Figure 45-21.
Figure 45-22. SPI Slave Mode with (CPOL = NCPHA = 0) or (CPOL = NCPHA = 1) NPCS0 SPI15 SPI14 SPCK SPI9 MISO SPI10 SPI11 MOSI 45.10.3.1 Maximum SPI Frequency The following formulas give maximum SPI frequency in Master read and write modes and in Slave read and write modes. Master Write Mode The SPI only sends data to a slave device such as an LCD, for example. The limit is given by SPI2 (or SPI5) timing. Since it gives a maximum frequency above the maximum pad speed (see Section 45.10.
45.10.3.2 SPI Timings SPI timings are given for the following domains: 3.3V domain: VDDIO from 3.0V to 3.6V, maximum external capacitor = 30 pF 1.8V domain: VDDIO from 1.65V to 1.95V, maximum external capacitor = 30 pF Table 45-48.
Note that in SPI master mode the SAM3X/A does not sample the data (MISO) on the opposite edge where data clocks out (MOSI) but the same edge is used as shown in Figure 45-19 and Figure 45-20. 45.10.4 MCI Timings The High Speed MultiMedia Card Interface (HSMCI) supports the MultiMedia Card (MMC) Specification V4.3, the SD Memory Card Specification V2.0, the SDIO V2.0 specification and CE-ATA V1.1.
45.10.5 SSC Timings SSC timings are given for the following domains: 1.8V domain: VDDIO from 1.62V to 1.95V, maximum external capacitor = 25 pF 3.3V domain: VDDIO from 3.0V to 3.6V, maximum external capacitor = 25 pF Figure 45-23. SSC Transmitter, TK and TF as output TK (CKI =0) TK (CKI =1) SSC0 TF/TD Figure 45-24. SSC Transmitter, TK as input and TF as output TK (CKI =0) TK (CKI =1) SSC1 TF/TD Figure 45-25.
Figure 45-26. SSC Transmitter, TK and TF as input TK (CKI=1) TK (CKI=0) SSC5 SSC6 TF SSC7 TD Figure 45-27. SSC Receiver RK and RF as input RK (CKI=0) RK (CKI=1) SSC8 SSC9 RF/RD Figure 45-28.
Figure 45-29. SSC Receiver, RK and RF as output RK (CKI=1) RK (CKI=0) SSC12 SSC11 RD SSC13 RF Figure 45-30. SSC Receiver, RK as output and RF as input RK (CKI=0) RK (CKI=1) SSC11 SSC12 RF/RD Table 45-49. Symbol SSC Timings Parameter Conditions Min Max 1.8V domain 0(1) 2.5(1) 3.3V domain 0(1) 7.3(1) 1.8V domain 6.4(1) 18.1(1) 3.3V domain 6.4(1) 19.
Table 45-49. Symbol SSC Timings (Continued) Parameter Conditions Min Max Unit Receiver SSC8 RF/RD setup time before RK edge (RK input) SSC9 RF/RD hold time after RK edge (RK input) SSC10 RK edge to RF (RK input) SSC11 RF/RD setup time before RK edge (RK output) SSC12 RF/RD hold time after RK edge (RK output) SSC13 RK edge to RF (RK output) Note: 1.8V domain 0 3.3V domain 0 1.8V domain tCPMCK 3.3V domain tCPMCK 1.8V domain 5(1) 16(1) 3.3V domain 5(1) 16(1) 1.
45.10.6 SMC Timings SMC timings are given for the following domains: 1.8V domain: VDDIO from 1.65V to 1.95V, maximum external capacitor = 30 pF 3.3V domain: VDDIO from 3.0V to 3.6V, maximum external capacitor = 50 pF Timings are given assuming a capacitance load on data, control and address pads. In the following tables tCPMCK is MCK period. 45.10.6.1 Read Timings Table 45-50. SMC Read Signals - NRD Controlled (READ_MODE = 1) Parameter Symbol Min VDDIO supply 1.8V Domain Max 3.3V Domain 1.
45.10.6.2 Write Timings Table 45-52. SMC Write Signals - NWE Controlled (WRITE_MODE = 1) Parameter Symbol Min VDDIO supply 1.8V Domain Max 3.3V Domain 1.8V Domain 3.3V Domain Unit HOLD or NO HOLD SETTINGS (NWE_HOLD ≠ 0, NWE_HOLD = 0) NWE_PULSE × tCPMCK - 7.
Figure 45-32. SMC Timings - NCS Controlled Read and Write SMC12 SMC12 SMC26 SMC24 A0/A1/NBS[3:0]/A2–A25 SMC13 SMC13 NRD SMC14 NCS SMC14 SMC8 SMC9 SMC23 SMC10 SMC11 SMC22 SMC26 D0–D15 SMC27 SMC25 NWE NCS Controlled READ with NO HOLD NCS Controlled READ with HOLD NCS Controlled WRITE Figure 45-33.
Table 45-54. SDRAM PC100 Characteristics Min Max (1) Parameter 3V Supply SDRAM Controller Clock Frequency (3)(4) 1. 2. 3. 4. Table 45-55. ns 6 ns SDRAM PC133 Characteristics Max (1) 3V Supply Control/Address/Data In Setup Control/Address/Data In Hold (3)(4) (3)(4) Data Out change time after SDCK rising Table 45-56. 3V Supply (1) 80.6 MHz 0.8 ns 5.4 5.4 ns 3.0 ns Mobile Characteristics 1.
45.10.7 USART in SPI Mode Timings USART in SPI mode timings are given for the following domains: 1.8V domain: VDDIO from 1.62V to 1.95V, maximum external capacitor = 30 pF 3.3V domain: VDDIO from 3.0V to 3.6V, maximum external capacitor = 30 pF Figure 45-34.
Figure 45-36.
Table 45-57. Symbol USART SPI Timings Parameter Conditions Min Max Unit Master Mode SPI0 tCPSCK Period SPI1 Input Data Setup Time SPI2 Input Data Hold Time SPI3 Chip Select Active to Serial Clock SPI4 Output Data Setup Time SPI5 Serial Clock to Chip Select Inactive 1.8V domain 3.3V domain 1.8V domain 3.3V domain tCPMCK / 6 ns 0.5 × tCPMCK + 7.7 ns 1.8V domain 1.5 × tCPMCK + 1.8 3.3V domain 1.5 × tCPMCK + 0.7 1.8V domain 3.3V domain 1.8V domain 3.3V domain ns 1.
45.10.8 EMAC Table 45-58. EMAC Signals Relative to EMDC Symbol Parameter Conditions EMAC1 Setup for EMDIO from EMDC rising EMAC2 Hold for EMDIO from EMDC rising EMAC3 EMDIO toggling from EMDC rising Notes: 1. Min Max Unit 10 VDDIO from 3.0V to 3.6V, maximum external capacitor = 20 pF ns 10 0(1) 300(1) For EMAC output signals, Min and Max access time are defined. The Min access time is the time between the EDMC rising edge and the signal change.
Figure 45-38.
45.10.8.2 RMII Mode Table 45-60. RMII Mode Symbol Parameter EMAC21 Conditions Min Max ETXEN toggling from EREFCK rising 2 16 EMAC22 ETX toggling from EREFCK rising 2 16 EMAC23 Setup for ERX from EREFCK rising 4 EMAC24 Hold for ERX from EREFCK rising EMAC25 Setup for ERXER from EREFCK rising EMAC26 Hold for ERXER from EREFCK rising 2 EMAC27 Setup for ECRSDV from EREFCK rising 4 EMAC28 Hold for ECRSDV from EREFCK rising 2 VDDIO from 3.0V to 3.
45.10.9 Two-wire Serial Interface Characteristics Table 45-61 describes the requirements for devices connected to the Two-wire Serial Bus. For timing symbols refer to Figure 45-40. Table 45-61. Two-wire Serial Bus Requirements Symbol Parameter VIL Conditions Min Max Unit Input Low-voltage -0.3 0.3 × VDDIO V VIH Input High-voltage 0.7 × VDDIO VCC + 0.3 V Vhys Hysteresis of Schmitt Trigger Inputs 0.150 – V VOL Output Low-voltage – 3 mA sink current 0.4 V 0.
Figure 45-40.
45.10.10 Embedded Flash Characteristics The maximum operating frequency given in Table 45-62 is limited by the Embedded Flash access time when the processor is fetching code out of it. The table provides the device maximum operating frequency defined by the value of field FWS in the EEFC_FMR. This field defines the number of wait states required to access the Embedded Flash Memory. Note: The embedded flash is fully tested during production test.
46. Mechanical Characteristics Figure 46-1. 100-lead LQFP Package Drawing Table 46-1. 100-lead LQFP Device and Package Maximum Weight 800 Table 46-2. mg 100-lead LQFP Package Reference JEDEC Drawing Reference MS-026 JESD97 Classification e3 Table 46-3.
Figure 46-2. 100-ball TFBGA Package Drawing Table 46-4. 100-ball TFBGA Package Reference - Soldering Information (Substrate Level) Ball Land Diameter 0.45 mm Soldering Mask Opening 0.35 mm Table 46-5. 100-ball TFBGA Device and Package Maximum Weight 141 Table 46-6. mg 100-ball TFBGA Package Characteristics Moisture Sensitivity Level Table 46-7.
Figure 46-3. 144-lead LQFP Package Drawing Table 46-8. 144-lead LQFP Device and Package Maximum Weight 1400 Table 46-9. mg 144-lead LQFP Package Characteristics Moisture Sensitivity Level Table 46-10.
Figure 46-4. 144-ball LFBGA Package Drawing All dimensions are in mm Table 46-11. Soldering Information (Substrate Level) Ball Land 0.380 mm Soldering Mask Opening 0.280 mm Table 46-12. 144-ball BGA Device and Package Maximum Weight 300 Table 46-13. mg 144-ball BGA Package Characteristics Moisture Sensitivity Level Table 46-14.
46.1 Soldering Profile Table 46-15 gives the recommended soldering profile from J-STD-020C. Table 46-15. Soldering Profile Profile Feature Green Package Average Ramp-up Rate (217°C to Peak) 3°C/sec. max. Preheat Temperature 175°C ± 25°C 180 sec. max. Temperature Maintained above 217°C 60 sec. to 150 sec. Time within 5°C of Actual Peak Temperature 20 sec. to 40 sec. Peak Temperature Range 260°C Ramp-down Rate 6°C/sec. max. Time 25°C to Peak Temperature 8 min. max.
47. Marking All devices are marked with the Atmel logo and the ordering code.
48. Ordering Information Table 48-1.
49. SAM3X/A Series Errata 49.1 Errata Revision A Parts The table below lists the chip IDs for revision A parts. Table 49-1. Revision A Parts Chip IDs Chip Name Revision Chip ID SAM3X8H A 0x286E0A60 SAM3X8E A 0x285E0A60 SAM3X4E A 0x285B0960 SAM3X8C A 0x284E0A60 SAM3X4C A 0x284B0960 SAM3A8C A 0x283E0A60 A 0x283B0960 (1) SAM3A4C Note: 1. This device is not commercially available. Mounted only on the SAM3X-EK evaluation kit. 49.1.1 Flash Memory 49.1.1.
49.1.1.3 Flash: Boot Flash Programming Mapping Is Wrong GPNVM2 enables to select if Flash0 or Flash1 is used for the boot. But when GPNVM2 is set, only the first 64 Kbytes of the Flash 1 are seen in the Boot Memory. The rest of the Boot memory corresponds to Flash 0 content. Problem Fix/Workaround No fix required if the code size is less than 64Kbytes. Otherwise the software needs to take into account this limitation if GPNVM2 is used. 49.1.1.
49.1.4 Analog to Digital Converter (ADC) 49.1.4.1 ADC: First Conversion After Sleep In sleep mode, first converted data incorrect after Wakeup. Problem Fix/Workaround One or more channels must be converted using sleep mode, a dummy channel as first channel of the series can be used. 49.1.4.2 ADC: Last Conversion Error In sleep mode, last converted data incorrect before Shutdown.
50. Revision History In the table that follows, the most recent version of the document appears first. Table 50-1. Issue Date SAM3X/SAM3A Datasheet Rev.
Table 50-1. Issue Date SAM3X/SAM3A Datasheet Rev. 11057C Revision History (Continued) Comments Section 7. “Memories” Inserted Section 7.1 “Product Mapping” (was previously section 8. “Product Mapping”) Updated Section 7.2.1 “Internal SRAM” Section 7.2.2 “Internal ROM”: changed “At any time, the ROM is mapped at address 0x0018 0000” to “At any time, the ROM is mapped at address 0x0010 0000” Updated Section 7.2.3.10 “GPNVM Bits” Section 7.2.
Table 50-1. Issue Date SAM3X/SAM3A Datasheet Rev. 11057C Revision History (Continued) Comments Section 36. “Timer Counter (TC)” (cont’d) Table 36-2 ”Signal Name Description”: updated descriptions of signals ‘INT’ and ‘SYNC’ Table 36-3 ”TC Pin List”: removed ‘FAULT’ pin Table 36-4 ”I/O Lines”: added TIOA3/PB0, TIOA4/PB2, TIOA5/PB4, TIOB3/PB1, TIOB4/PB3, and TIOB5/PB5 Section 36.5.3 “Interrupt Sources”: changed title (was “Interrupt”) and added Table 36-5 ”Peripheral IDs” Section 36.6.
Table 50-1. Issue Date SAM3X/SAM3A Datasheet Rev. 11057C Revision History (Continued) Comments Section 45. “Electrical Characteristics” Updated and harmonized parameter symbols Table 45-1 Absolute Maximum Ratings*: - added “(except VBUS)” to description “Voltage on Input Pins with Respect to Ground” - added “Voltage on VBUS Pin with Respect to Ground” Table 45-2 DC Characteristics: removed parameter “Input Capacitance” Table 45-3 1.
Table 50-1. Issue Date SAM3X/SAM3A Datasheet Rev. 11057C Revision History (Continued) Comments Section 45. “Electrical Characteristics” (cont’d) Section 45.10.
Doc. Rev. 11057B Comments Change Request Ref. SDRAM and 217-pin package information removed only from Section “Features”, Section 1.1 “Configuration Summary” (introduction) and Section 48. “Ordering Information”. 8251 “Write protected Registers” added to Section “Features”. 8213 Section “Features”, Section 1.1 “Configuration Summary” (introduction) updated. Figure 2-3 ”SAM3X4/8E (144 pins) Block Diagram” updated. Section 1.
Table of Contents Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.1 Configuration Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.
10.5 10.6 10.7 10.8 10.9 10.10 10.11 10.12 10.13 10.14 10.15 10.16 10.17 10.18 10.19 10.20 10.21 10.22 10.23 10.24 Memory model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Exception model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Fault handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.2 15.3 15.4 15.5 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watchdog Timer (WDT) User Interface. . . . . . . . . . . . . . . . . . .
22.7 AHB DMA Controller (DMAC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 23. External Memory Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382 23.1 23.2 23.3 23.4 23.5 23.6 23.7 23.8 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . .
27.4 27.5 27.6 27.7 Slow Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520 Main Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522 Divider and PLL Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524 UTMI Phase Lock Loop Programming . . . . . . .
32.5 32.6 32.7 32.8 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Peripheral Interface (SPI) User Interface . . . . . . . . . . . .
37.7 37.8 37.9 37.10 37.11 37.12 37.13 37.14 Bus Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High Speed MultiMediaCard Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SD/SDIO Card Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CE-ATA Operation . . . . . . . . . . . . . . . . . . . . . . .
43.2 43.3 43.4 43.5 43.6 43.7 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . .
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