Datasheet

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SAM E70/S70/V70/V71 Family

32-bit ARM Cortex-M7 MCUs with FPU, Audio and

Graphics Interfaces, High-Speed USB, Ethernet, and

Advanced Analog

Features

Core

•

ARM

Cortex

-M7 running at up to 300 MHz

• 16 Kbytes of I-Cache and 16 Kbytes of D-Cache with Error Code Correction (ECC)

• Single-precision and double-precision HW Floating Point Unit (FPU)

• Memory Protection Unit (MPU) with 16 zones

• DSP Instructions, Thumb

-2 Instruction Set

• Embedded Trace Module (ETM) with instruction trace stream, including Trace Port Interface Unit (TPIU)

Memories

• Up to 2048 Kbytes embedded Flash with unique identifier and user signature for user-defined data

• Up to 384 Kbytes embedded Multi-port SRAM

• Tightly Coupled Memory (TCM)

• 16 Kbytes ROM with embedded Bootloader routines (UART0, USB) and IAP routines

• 16-bit Static Memory Controller (SMC) with support for SRAM, PSRAM, LCD module, NOR and NAND Flash

with on-the-fly scrambling

• 16-bit SDRAM Controller (SDRAMC) interfacing up to 256 MB and with on-the-fly scrambling

System

• Embedded voltage regulator for single-supply operation

• Power-on-Reset (POR), Brown-out Detector (BOD) and Dual Watchdog for safe operation

• Quartz or ceramic resonator oscillators: 3 MHz to 20 MHz main oscillator with failure detection, 12 MHz or 16

MHz needed for USB operations. Optional low-power 32.768 kHz for RTC or device clock

• RTC with Gregorian calendar mode, waveform generation in low-power modes

• RTC counter calibration circuitry compensates for 32.768 kHz crystal frequency variations

• 32-bit low-power Real-time Timer (RTT)

• High-precision Main RC oscillator with 12 MHz default frequency.

• 32.768 kHz crystal oscillator or Slow RC oscillator as source of low-power mode device clock (SLCK)

• One 500 MHz PLL for system clock, one 480 MHz PLL for USB high-speed operations

• Temperature Sensor

• One dual-port 24-channel central DMA Controller (XDMAC)

Low-Power Features

• Low-power sleep, wait and backup modes, with typical power consumption down to 1.1 μA in Backup mode with

RTC, RTT and wakeup logic enabled

• Ultra low-power RTC and RTT

• 1 Kbyte of backup RAM (BRAM) with dedicated regulator

Peripherals

echnology Inc.

Datasheet

DS60001527D-page 1

Summary of content (1976 pages)

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SAM E70/S70/V70/V71 Family 32-bit ARM Cortex-M7 MCUs with FPU, Audio and Graphics Interfaces, High-Speed USB, Ethernet, and Advanced Analog Features Core • ARM® Cortex®-M7 running at up to 300 MHz • 16 Kbytes of I-Cache and 16 Kbytes of D-Cache with Error Code Correction (ECC) • Single-precision and double-precision HW Floating Point Unit (FPU) • Memory Protection Unit (MPU) with 16 zones • DSP Instructions, Thumb®-2 Instruction Set • Embedded Trace Module (ETM) with instruction trace stream, including Trac
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SAM E70/S70/V70/V71 Family • • • • • • • • • • • • • • • • • • One Ethernet MAC (GMAC) 10/100 Mbps in MII mode and RMII with dedicated DMA. IEEE1588 PTP frames and 802.3az Energy-efficiency support. Ethernet AVB support with IEEE802.1AS Timestamping and IEEE802.1Qav credit-based traffic-shaping hardware support. USB 2.0 Device/Mini Host High-speed (USBHS) at 480 Mbps, 4-Kbyte FIFO, up to 10 bidirectional endpoints, dedicated DMA 12-bit ITU-R BT.
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SAM E70/S70/V70/V71 Family Table of Contents Features......................................................................................................................................................... 1 1. Configuration Summary........................................................................................................................ 14 2. Ordering Information.............................................................................................................................
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SAM E70/S70/V70/V71 Family 13.2. Power-on-Reset, Brownout and Supply Monitor........................................................................ 66 13.3. Reset Controller......................................................................................................................... 66 14. Peripherals............................................................................................................................................ 67 14.1. Peripheral Identifiers..........................
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SAM E70/S70/V70/V71 Family 22.2. 22.3. 22.4. 22.5. Embedded Characteristics....................................................................................................... 127 Product Dependencies............................................................................................................. 127 Functional Description..............................................................................................................127 Register Summary..........................................
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SAM E70/S70/V70/V71 Family 29.2. Embedded Characteristics....................................................................................................... 239 29.3. Register Summary....................................................................................................................240 30. Clock Generator.................................................................................................................................. 242 30.1. 30.2. 30.3. 30.4. 30.5. 30.6. 30.7.
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SAM E70/S70/V70/V71 Family 34. SDRAM Controller (SDRAMC)............................................................................................................389 34.1. 34.2. 34.3. 34.4. 34.5. 34.6. 34.7. Description............................................................................................................................... 389 Embedded Characteristics....................................................................................................... 389 Signal Description........
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SAM E70/S70/V70/V71 Family 38.2. 38.3. 38.4. 38.5. 38.6. 38.7. 38.8. Embedded Characteristics....................................................................................................... 573 Block Diagram.......................................................................................................................... 574 Signal Interface........................................................................................................................ 574 Product Dependencies.........
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SAM E70/S70/V70/V71 Family 42.7. Register Summary..................................................................................................................1023 43. Two-wire Interface (TWIHS)..............................................................................................................1045 43.1. 43.2. 43.3. 43.4. 43.5. 43.6. 43.7. Description.............................................................................................................................
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SAM E70/S70/V70/V71 Family 48. Media Local Bus (MLB).....................................................................................................................1326 48.1. 48.2. 48.3. 48.4. 48.5. 48.6. 48.7. Description............................................................................................................................. 1326 Embedded Characteristics..................................................................................................... 1327 Block Diagram.........
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SAM E70/S70/V70/V71 Family 53.5. Product Dependencies........................................................................................................... 1707 53.6. Functional Description............................................................................................................1707 53.7. Register Summary..................................................................................................................1713 54. Analog Comparator Controller (ACC)..........................
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SAM E70/S70/V70/V71 Family 58.13. Timings for STH Conditions................................................................................................... 1845 59. Electrical Characteristics for SAM E70/S70...................................................................................... 1863 59.1. Absolute Maximum Ratings....................................................................................................1863 59.2. DC Characteristics..................................................
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SAM E70/S70/V70/V71 Family Worldwide Sales and Service...................................................................................................................1976 © 2019 Microchip Technology Inc.
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SAM E70/S70/V70/V71 Family Configuration Summary 1. Configuration Summary The SAM E70/S70/V70/V71 devices differ in memory size, package and features. The following tables summarize the different configurations. Table 1-1.
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SAM E70/S70/V70/V71 Family Configuration Summary Table 1-3.
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SAM E70/S70/V70/V71 Family Ordering Information 2.
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SAM E70/S70/V70/V71 Family Block Diagram Block Diagram Refer to the table 1. Configuration Summary for detailed configurations of memory size, package and features of the SAM E70/S70/V70/V71 devices. C IS I_ IS D[1 I_ 1 PC :0 K, ] IS I_ M IS C I_ K H SY N C ,I SI _V SY N A[ 23 : N 0], W D N AIT [15 AN , N :0 ] R DO CS AS E 0. A2 , C , NA .3, 1 AS N NR A2 /NA , D DW D, 2/ ND Q E NW A0 NA AL M0 E /N ND E ..
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SAM E70/S70/V70/V71 Family Block Diagram A[ 2 IS I_ IS D[1 I_ 1 IS PC :0] I_ K H ,I SY S I_ G TX NC MC G CK , IS K T , I_ G XE GR VS C R X Y R , G S, GT CK NC R G X , X G G ER CO DV RE R , L FC G X 0 GR , G K M ..3 X C D R G C, , G DV SD TS G TX V U M 0. C D .3 O IO C M A P C NR AN X0 TX ..1 0. .1 3: N 0], W D N AIT [15 AN , : N 0] R DO CS AS E 0 . A2 , C , NA .3, 1/ AS N NR A2 NA , D DW D, 2 N Q E NW A0 /NA DAL M0 E /N ND E ..
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SAM E70/S70/V70/V71 Family Block Diagram M L M BC L L M BS K LB IG DA T IS I_ IS D[1 I_ 1 IS PC :0] I_ K H ,I SY S N I_M C, C C AN IS K I_ C R VS AN X0 YN TX ..1 C 0. .1 H SD H M SD P A[ 23 : N 0], W D N AIT [15 AN , : N 0] R DO CS AS E 0 . A2 , C , NA .3, 1/ AS N NR A2 NA , D DW D, 2 N Q E NW A0 /NA DAL M0 E /N ND E ..1 ,S A1 LB CL D 6/ , N E C SD U K, B SD B A0 Q C SC ,A KE Q K, 17 ,S M Q /S O DA D Q S CS BA 10 M I/Q I 1 Q SO IO IO /Q 0 2. IO .
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SAM E70/S70/V70/V71 Family Block Diagram IS I_ IS D[1 I_ 1 IS PC :0] I_ K H ,I SY S I_ G TX NC MC G CK , IS K T , I_ G XE GR VS C R X Y R , G S, GT CK NC R G X , X G G ER CO DV RE R , L FC G X0 GR , G K M ..3 X C D R G C, , G DV SD TS G TX V U M 0. C D .3 O IO C M A P C NR AN X0 TX ..1 0. .1 M L M BC L L M BS K LB IG DA T H SD H M SD P A[ 23 : N 0], W D N AIT [15 AN , : N 0] R DO CS AS E 0 . A2 , C , NA .3, 1/ AS N NR A2 NA , D DW D, 2 N Q E NW A0 /NA DAL M0 E /N ND E ..
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SAM E70/S70/V70/V71 Family Signal Description 4. Signal Description The following table provides details on signal names classified by peripheral. Table 4-1.
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SAM E70/S70/V70/V71 Family Signal Description ...........
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SAM E70/S70/V70/V71 Family Signal Description ...........
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SAM E70/S70/V70/V71 Family Signal Description ...........
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SAM E70/S70/V70/V71 Family Signal Description ...........continued Signal Name Function Type Active Level Voltage Reference Comments Input – – Timer Counter (TC(x=[0:11])) TCLKx TC Channel x External Clock Input TIOAx TC Channel x I/O Line A I/O – – TIOBx TC Channel x I/O Line B I/O – – PCK6 can be used as an input clock PCK7 can be used as an input clock for TC0 only – Pulse Width Modulation Controller (PWMC(x=[0..
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SAM E70/S70/V70/V71 Family Signal Description ...........continued Signal Name Function Type Active Level Voltage Reference Comments Analog VREFP ADC, DAC and Analog Comparator Positive Reference Analog – – – VREFN ADC, DAC and Analog Comparator Negative Reference Must be connected to GND or GNDANA. Analog – – – – – 12-bit Analog Front End - (x=[0..
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SAM E70/S70/V70/V71 Family Signal Description ...........
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SAM E70/S70/V70/V71 Family Automotive Quality Grade 5. Automotive Quality Grade The SAM V70 and SAM V71 devices are developed and manufactured according to the most stringent requirements of the international standard ISO-TS-16949. This data sheet contains limited values extracted from the results of extensive characterization (temperature and voltage). The quality and reliability of the SAM V70 and SAM V71 has been verified during regular product qualification as per AEC-Q100 grade 2 (–40°C to +105°C).
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SAM E70/S70/V70/V71 Family Package and Pinout 6. Package and Pinout In the tables that follow, the column “Reset State” indicates the reset state of the line with mnemonics. • “PIO” “/” signal Indicates whether the PIO Line resets in I/O mode or in peripheral mode. If “PIO” is mentioned, the PIO line is maintained in a static state as soon as the reset is released. As a result, the bit corresponding to the PIO line in the register PIO_PSR (Peripheral Status Register) resets low.
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SAM E70/S70/V70/V71 Family Package and Pinout 6.1.2 144-ball LFBGA/TFBGA Package Outline Figure 6-2. Orientation of the 144-ball LFBGA/TFBGA Package 6.1.3 144-ball UFBGA Package Outline Figure 6-3. Orientation of the 144-ball UFBGA Package 6.2 144-lead Package Pinout Table 6-1.
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SAM E70/S70/V70/V71 Family Package and Pinout ...........
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SAM E70/S70/V70/V71 Family Package and Pinout ...........
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SAM E70/S70/V70/V71 Family Package and Pinout ...........
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SAM E70/S70/V70/V71 Family Package and Pinout ...........
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SAM E70/S70/V70/V71 Family Package and Pinout ...........
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SAM E70/S70/V70/V71 Family Package and Pinout 6.3 100-lead Packages 6.3.1 100-pin LQFP Package Outline Figure 6-4. Orientation of the 100-lead LQFP Package 75 51 76 50 100 26 1 6.3.2 25 100-ball TFBGA Package Outline The 100-ball TFBGA package has a 0.8 mm ball pitch and respects Green standards. Its dimensions are 9 x 9 x 1.1 mm. The figure below shows the orientation of the 100-ball TFBGA Package. Figure 6-5. Orientation of the 100-ball TFBGA Package TOP VIEW 10 9 8 7 6 5 4 3 2 1 BALL A1 6.3.
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SAM E70/S70/V70/V71 Family Package and Pinout 6.4 100-lead Package Pinout Table 6-2.
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SAM E70/S70/V70/V71 Family Package and Pinout ...........
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SAM E70/S70/V70/V71 Family Package and Pinout ...........
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SAM E70/S70/V70/V71 Family Package and Pinout 6.5 64-lead Package 6.5.1 64-lead QFN Wettable Flanks Package Outline Figure 6-7. Orientation of the 64-lead QFN Wettable Flanks Package 6.5.2 64-pin LQFP Package Outline Figure 6-8. Orientation of the 64-pin LQFP Package 33 48 49 32 64 17 16 1 6.6 64-lead Package Pinout Table 6-3.
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SAM E70/S70/V70/V71 Family Package and Pinout ...........
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SAM E70/S70/V70/V71 Family Package and Pinout ...........
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SAM E70/S70/V70/V71 Family Package and Pinout Note: 1. To select this extra function, refer to the 32.5.14 Parallel Capture Mode section in the Parallel Input/Output Controller (PIO) chapter. 2. PIODCEN1/PIODCx has priority over WKUPx. Refer to the 32.5.14 Parallel Capture Mode section in the PIO chapter. 3. Refer to the 23.4.2 Slow Clock Generator section in the Supply Controller (SUPC) chapter. 4. To select this extra function, refer to the 33.5.2.
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SAM E70/S70/V70/V71 Family Power Considerations 7. Power Considerations 7.1 Power Supplies The following table defines the power supply rails of the SAM E70/S70/V70/V71 and the estimated power consumption at typical voltage. Table 7-1. Power Supplies 7.2 Name Associated Ground Powers VDDCORE GND Core, embedded memories and peripherals. VDDIO GND Peripheral I/O lines (Input/Output Buffers), backup part, 1 Kbytes of backup SRAM, 32 kHz crystal oscillator, oscillator pads.
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SAM E70/S70/V70/V71 Family Power Considerations Figure 7-1. Powerup Sequence Supply (V) VDDIO VDDIN VDDPLLUSB VDDUTMII VDDx(min) VDDCORE VDDPLL VDDUTMIC VDDy(min) VT+ tRST Time (t) Related Links 58.2 DC Characteristics 23.4.6 Backup Power Supply Reset 23.4.6.1 Raising the Backup Power Supply 7.2.
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SAM E70/S70/V70/V71 Family Power Considerations To save the power consumption of the backup SRAM, the user can disable the backup SRAM power switch by clearing the bit SRAMON in the Supply Controller Mode Register (SUPC_MR). By default, after VDDIO rises, the backup SRAM power switch is enabled. 7.5 Active Mode Active mode is the normal running mode with the core clock running from the fast RC oscillator, the main crystal oscillator or the PLLA.
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SAM E70/S70/V70/V71 Family Power Considerations To enter Wait mode, first, select the Main RC oscillator as Main Clock and perform the following steps: 1. 2. 3. 4. 5. 7.6.3 Configure the FLPM field in the PMC_FSMR. Set Flash Wait State at 0. Set HCLK = MCK by configuring MDIV to 0 in the PMC Master Clock register (PMC_MCKR). Set the WAITMODE bit in the PMC Clock Generator Main Oscillator register (CKGR_MOR). Wait for MCKRDY = 1 in the PMC Status register (PMC_SR).
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SAM E70/S70/V70/V71 Family Power Considerations Note: 1. The bit SLEEPDEEP is in the Cortex-M7 System Control Register. 2. When considering wakeup time, the time required to start the PLL is not taken into account. Once started, the device works with the Main RC oscillator. The user has to add the PLL startup time if it is needed in the system. The wakeup time is defined as the time taken for wakeup until the first instruction is fetched. 3. HCLK = MCK.
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SAM E70/S70/V70/V71 Family Input/Output Lines 8. Input/Output Lines The SAM E70/S70/V70/V71 features both general purpose I/Os (GPIO) and system I/Os. GPIOs can have alternate functionality due to multiplexing capabilities of the PIO controllers. The same PIO line can be used, whether in I/O mode or by the multiplexed peripherals. System I/Os include pins such as test pins, oscillators, erase or analog inputs. 8.1 General-Purpose I/O Lines General-purpose (GPIO) lines are managed by PIO Controllers.
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SAM E70/S70/V70/V71 Family Input/Output Lines ...........continued CCFG_SYSIO Default Function Other Bit Number After Reset Function Constraints for Normal Start Configuration – PA7 XIN32 – (see Note 2) – PA8 XOUT32 – – PB9 XIN – – PB8 XOUT – (see Note 3) Note: 1. If PB12 is used as PIO input in user applications, a low level must be ensured at startup to prevent Flash erase before the user application sets PB12 into PIO mode. 2. Refer to 23.4.2 Slow Clock Generator. 3. Refer to 30.5.
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SAM E70/S70/V70/V71 Family Input/Output Lines The ERASE pin is a system I/O pin that can be used as a standard I/O. At startup, this system I/O pin defaults to the ERASE function. This pin is debounced by SLCK to improve the glitch tolerance. To avoid unexpected erase at power-up due to glitches, a minimum ERASE pin assertion time is required. This time is defined in Table 58-50. The erase operation cannot be performed when the system is in Wait mode.
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SAM E70/S70/V70/V71 Family Interconnect 9. Interconnect The system architecture is based on the ARM Cortex-M7 processor connected to the main AHB Bus Matrix, the embedded Flash, the multi-port SRAM and the ROM. The 32-bit AHBP interface is a single 32-bit wide interface that accesses the peripherals connected on the main Bus Matrix. It is used only for data access. Instruction fetches are never performed on the AHBP interface.
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SAM E70/S70/V70/V71 Family Product Mapping 10. Product Mapping Figure 10-1. SAM S70 Product Mapping Figure 10-2.
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SAM E70/S70/V70/V71 Family Memories 11. Memories 11.1 Embedded Memories 11.1.1 Internal SRAM SAM E70/S70/V70/V71 devices embed 384 Kbytes or 256 Kbytes of high-speed SRAM. The SRAM is accessible over the system Cortex-M bus at address 0x2040 0000. SAM E70/S70/V70/V71 devices embed a Multi-Port SRAM with four ports to optimize the bandwidth and latency. The priorities, defined in the Bus Matrix for each SRAM port slave are propagated, for each request, up to the SRAM slaves.
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SAM E70/S70/V70/V71 Family Memories The ROM may also be mapped at 0x00000000 depending on GPNVM bit setting and ITCM use. 11.1.4 Backup SRAM The SAM E70/S70/V70/V71 embeds 1 Kbytes of backup SRAM located at 0x4007 4000. The backup SRAM is accessible in 32-bit words only. Byte or half-word accesses are not supported. The backup SRAM is supplied by VDDCORE in Normal mode. In Backup mode, the backup SRAM supply is automatically switched to VDDIO through the backup SRAM power switch when VDDCORE falls.
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SAM E70/S70/V70/V71 Family Memories Figure 11-1. Global Flash Organization Address Sector size Sector Name 8 Kbytes Small Sector 0 8 Kbytes Small Sector 1 112 Kbytes Larger Sector 128 Kbytes Sector 1 128 Kbytes Sector n 0x000 Sector 0 Each sector is organized in pages of 512 bytes.
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SAM E70/S70/V70/V71 Family Memories Figure 11-3.
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SAM E70/S70/V70/V71 Family Memories ...........continued Flash Size (Kbytes) Number of Lock Bits Lock Region Size 1024 64 16 Kbytes 512 32 16 Kbytes Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash. 11.1.5.5 Security Bit Feature The SAM E70/S70/V70/V71 features a security bit based on the GPNVM bit 0.
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SAM E70/S70/V70/V71 Family Memories ...........continued I/O Line System Function PA7 PGMD0 PA8 PGMD1 PA9 PGMD2 PA10 PGMD3 PA11 PGMD4 PA12 PGMD5 PA13 PGMD6 PA14 PGMD7 PD0 PGMD8 PD1 PGMD9 PD2 PGMD10 PD3 PGMD11 PD4 PGMD12 PD5 PGMD13 PD6 PGMD14 PD7 PGMD15 11.1.5.9 SAM-BA Boot The SAM-BA Boot is a default boot program which provides an easy way to program in-situ the on-chip Flash memory. The SAM-BA Boot Assistant supports serial communication via the UART0 and USB.
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SAM E70/S70/V70/V71 Family Memories ...........continued GPNVM Bit Function 8:7 TCM configuration 00: 0 Kbytes DTCM + 0 Kbytes ITCM (default) 01: 32 Kbytes DTCM + 32 Kbytes ITCM 10: 64 Kbytes DTCM + 64 Kbytes ITCM 11: 128 Kbytes DTCM + 128 Kbytes ITCM Note: After programming, reboot must be done. 11.1.6 Boot Strategies The system always boots at address 0x0. To ensure maximum boot possibilities, the memory layout can be changed using GPNVM bits.
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SAM E70/S70/V70/V71 Family Event System 12. Event System The events generated by peripherals (source) are designed to be directly routed to peripherals (destination) using these events without processor intervention. The trigger source can be programmed in the destination peripheral. 12.
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SAM E70/S70/V70/V71 Family Event System 12.2 Real-time Event Mapping Table 12-1.
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SAM E70/S70/V70/V71 Family Event System ...........continued Function Application Description Event Source Event Destination Measurement trigger Power factor correction (DC-DC, lighting, etc.
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SAM E70/S70/V70/V71 Family Event System ...........continued Function Application Description Event Source Event Destination Delay measurement Motor control Propagation delay of external components (IOs, power transistor bridge driver, etc.
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SAM E70/S70/V70/V71 Family Event System Note: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. Refer to 31.15 Main Crystal Oscillator Failure Detection. Refer to 51.5.4 Fault Inputs and 51.6.2.7 Fault Protection. Refer to 54.6.4 Fault Mode. Refer to 54.5.4 Fault Output. Refer to 23.4.9.2 Low-power Tamper Detection and Anti-Tampering and 29.3.1 SYS_GPBRx. Refer to 50.6.18 Fault Mode. Refer to 51.7.49 PWM_ETRGx. Refer to 51.6.5 PWM External Trigger Mode. Refer to 52.6.
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SAM E70/S70/V70/V71 Family System Controller 13. System Controller The System Controller is a set of peripherals that handles key elements of the system, such as power, resets, clocks, time, interrupts, watchdog, and so on.. 13.1 System Controller and Peripherals Mapping Refer to the “Product Mapping” section. 13.2 Power-on-Reset, Brownout and Supply Monitor The SAM E70/S70/V70/V71 embeds three features to monitor, warn and/or reset the chip: • • • • 13.2.
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SAM E70/S70/V70/V71 Family Peripherals 14. Peripherals 14.1 Peripheral Identifiers The following table defines the peripheral identifiers of the SAM E70/S70/V70/V71. A peripheral identifier is required for the control of the peripheral interrupt with the Nested Vectored Interrupt Controller and control of the peripheral clock with the Power Management Controller. Table 14-1.
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SAM E70/S70/V70/V71 Family Peripherals ...........
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SAM E70/S70/V70/V71 Family Peripherals ...........continued 14.2 Instance ID Instance Name NVIC Interrupt PMC Description Clock Control 60 PWM1 X X Pulse Width Modulation Controller 61 ARM FPU – ARM Floating Point Unit interrupt associated with OFC, UFC, IOC, DZC and IDC bits.
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SAM E70/S70/V70/V71 Family ARM Cortex-M7 (ARM) 15. ARM Cortex-M7 (ARM) Refer to ARM reference documents Cortex-M7 Processor User Guide (ARM DUI 0644) and Cortex-M7 Technical Reference Manual (ARM DDI 0489), available on www.arm.com. 15.1 ARM Cortex-M7 Configuration The following table provides the configuration for the ARM Cortex-M7 processor in SAM E70/S70/V70/V71 devices. Table 15-1.
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SAM E70/S70/V70/V71 Family Debug and Test Features 16. Debug and Test Features 16.1 Description The device features a number of complementary debug and test capabilities. The Serial Wire Debug Port (SW-DP) is used for standard debugging functions, such as downloading code and single-stepping through programs. It also embeds a serial wire trace. 16.2 Embedded Characteristics • • • • • • • 16.
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SAM E70/S70/V70/V71 Family Debug and Test Features 16.4 Debug and Test Block Diagram Figure 16-1. Debug and Test Block Diagram TMS/SWDIO TCK/SWCLK TDI Boundary Test Access Port (TAP) JTAGSEL Serial Wire Debug Port TDO/TRACESWO POR Reset and Test Embedded Trace Macrocell TRACED0–3 PIO Cortex-M7 TST TRACECLK PCK3 16.5 Debug and Test Pin Description Table 16-1.
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SAM E70/S70/V70/V71 Family Debug and Test Features 16.6 16.6.1 Application Examples Debug Environment The figure below shows a complete debug environment example. The SW-DP interface is used for standard debugging functions, such as downloading code and single-stepping through the program and viewing core and peripheral registers. Figure 16-2.
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SAM E70/S70/V70/V71 Family Debug and Test Features 16.7 Functional Description 16.7.1 Test Pin The TST pin is used for JTAG Boundary Scan Manufacturing Test or Fast Flash Programming mode. The TST pin integrates a permanent pulldown resistor of about 15 kΩ to GND, so that it can be left unconnected for normal operations. To enable Fast Flash Programming mode, refer to 18. Fast Flash Programming Interface (FFPI). 16.7.2 Debug Architecture Figure 16-4 shows the debug architecture used.
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SAM E70/S70/V70/V71 Family Debug and Test Features Table 16-2. SW-DP Pin List Pin Name JTAG Boundary Scan Serial Wire Debug Port TMS/SWDIO TMS SWDIO TCK/SWCLK TCK SWCLK TDI TDI – TDO/TRACESWO TDO TRACESWO (optional: trace) SW-DP is selected when JTAGSEL is low. It is not possible to switch directly between SW-DP and JTAG boundary scan operations. A chip reset must be performed after JTAGSEL is changed. 16.7.
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SAM E70/S70/V70/V71 Family Debug and Test Features 3. 4. 5. – Enable ITM. – Enable Synchronization packets. – Enable SWO behavior. – Fix the ATB ID to 1. Write 0x1 into the Trace Enable register: – Enable the Stimulus port 0. Write 0x1 into the Trace Privilege register: – Stimulus port 0 only accessed in privileged mode (Clearing a bit in this register will result in the corresponding stimulus port being accessible in user mode.
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SAM E70/S70/V70/V71 Family Debug and Test Features 31 30 29 28 27 26 25 24 18 17 16 10 9 8 VERSION 23 22 21 PART NUMBER 20 19 PART NUMBER 15 14 13 12 11 PART NUMBER 7 6 5 MANUFACTURER IDENTITY 4 3 2 MANUFACTURER IDENTITY • VERSION[31:28]: Product Version Number Set to 0x0. • PART NUMBER[27:12]: Product Part Number Set to 0x0. 1 0 1 PART NUMBER 0x5B3D • MANUFACTURER IDENTITY[11:1]: Manufacturer ID Set to 0x01F. • Bit[0]: Required by IEEE Std. 1149.1 Set to 0x1.
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SAM E70/S70/V70/V71 Family SAM-BA Boot Program 17. SAM-BA Boot Program 17.1 Description The SAM-BA Boot Program integrates an array of programs permitting download and/or upload into the different memories of the product. 17.
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SAM E70/S70/V70/V71 Family SAM-BA Boot Program The SAM-BA boot program looks for a source clock, either from the embedded main oscillator with external crystal (main oscillator enabled) or from a supported frequency signal applied to the XIN pin (Main oscillator in bypass mode). If a clock is supplied by one of the two sources, the boot program checks that the frequency is one of the supported external frequencies. If the frequency is supported, USB activation is allowed.
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SAM E70/S70/V70/V71 Family SAM-BA Boot Program ...........continued Command Action Arguments Example G Go Address# G200200# V Display version No argument V# • • • • • • • 17.6.
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SAM E70/S70/V70/V71 Family SAM-BA Boot Program Figure 17-2. Xmodem Transfer Example Host Device C SOH 01 FE Data[128] CRC CRC ACK SOH 02 FD Data[128] CRC CRC ACK SOH 03 FC Data[100] CRC CRC ACK EOT ACK 17.6.3 USB Device Port The device uses the USB communication device class (CDC) drivers to take advantage of the installed PC RS-232 software to talk over the USB. The CDC class is implemented in all releases of Windows®, beginning with Windows 98SE. The CDC document, available at www.usb.
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SAM E70/S70/V70/V71 Family SAM-BA Boot Program Table 17-4. Handled Class Requests Request Definition SET_LINE_CODING Configures DTE rate, stop bits, parity and number of character bits. GET_LINE_CODING Requests current DTE rate, stop bits, parity and number of character bits. SET_CONTROL_LINE_STATE RS-232 signal used to tell the DCE device the DTE device is now present. Unhandled requests are STALLed. 17.6.3.2 Communication Endpoints There are two communication endpoints.
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SAM E70/S70/V70/V71 Family Fast Flash Programming Interface (FFPI) 18. Fast Flash Programming Interface (FFPI) 18.1 Description The Fast Flash Programming Interface (FFPI) provides parallel high-volume programming using a standard gang programmer. The parallel interface is fully handshaked and the device is considered to be a standard EEPROM. Additionally, the parallel protocol offers an optimized access to all the embedded Flash functionalities.
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SAM E70/S70/V70/V71 Family Fast Flash Programming Interface (FFPI) ...........
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SAM E70/S70/V70/V71 Family Fast Flash Programming Interface (FFPI) ...........continued 18.3.
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SAM E70/S70/V70/V71 Family Fast Flash Programming Interface (FFPI) Figure 18-2. Parallel Programming Timing, Write Sequence NCMD 2 4 5 3 RDY NOE NVALID DATA[15:0] 1 MODE[3:0] Table 18-4.
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SAM E70/S70/V70/V71 Family Fast Flash Programming Interface (FFPI) ...........continued 18.3.5 Step Programmer Action Device Action DATA I/O 4 Sets DATA signal in tristate Waits for NOE Low Input 5 Clears NOE signal – Tristate 6 Waits for NVALID low Sets DATA bus in output mode and outputs the flash contents.
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SAM E70/S70/V70/V71 Family Fast Flash Programming Interface (FFPI) • • before access to any page other than the current one when a new command is validated (MODE = CMDE) The Write Page command (WP) is optimized for consecutive writes. Write handshaking can be chained; an internal address buffer is automatically increased. Table 18-7.
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SAM E70/S70/V70/V71 Family Fast Flash Programming Interface (FFPI) ...........continued Step Handshake Sequence MODE[3:0] DATA[15:0] 2 Write handshaking DATA Bit Mask Lock bits can be read using Get Lock Bit command (GLB). The nth lock bit is active when the bit n of the bit mask is set. Table 18-10. Get Lock Bit Command Step Handshake Sequence MODE[3:0] DATA[15:0] 1 Write handshaking CMDE GLB 2 Read handshaking DATA Lock Bit Mask Status 0 = Lock bit is cleared 1 = Lock bit is set 18.3.
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SAM E70/S70/V70/V71 Family Fast Flash Programming Interface (FFPI) To erase the Flash, perform the following steps: 1. 2. 3. 4. Power off the chip. Power on the chip with TST = 0. Assert the ERASE signal for at least the ERASE pin assertion time as defined in the section “Electrical Characteristics”. Power off the chip. Return to FFPI mode to check that the Flash is erased. 18.3.5.7 Memory Write Command This command is used to perform a write access to any memory location.
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SAM E70/S70/V70/V71 Family Bus Matrix (MATRIX) 19. Bus Matrix (MATRIX) 19.1 Description The Bus Matrix (MATRIX) implements a multi-layer AHB, based on the AHB-Lite protocol, that enables parallel access paths between multiple AHB masters and slaves in a system, thus increasing the overall bandwidth. The MATRIX interconnects 13 AHB masters to 9 AHB slaves. The normal latency to connect a master to a slave is one cycle.
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SAM E70/S70/V70/V71 Family Bus Matrix (MATRIX) ...........continued Master Index Name 6 ISI DMA 7 Media LB 8 USB DMA 9 Ethernet MAC DMA 10 CAN0 DMA 11 CAN1 DMA 12 Cortex-M7 Note: Master 12 (Cortex-M7) is only on revision B. 19.2.2 Matrix Slaves The MATRIX manages the slaves listed in the following table. Each slave has its own arbiter, providing a different arbitration per slave. Table 19-2. Bus Matrix Slaves 19.2.
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SAM E70/S70/V70/V71 Family Bus Matrix (MATRIX) ...........
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SAM E70/S70/V70/V71 Family Bus Matrix (MATRIX) 19.3.2.2 Last Access Master After the end of the current access, if no other request is pending, the slave remains connected to the last master that performed an access request. This allows the MATRIX to remove the one latency cycle for the last master that accessed the slave. Other non privileged masters still get one latency clock cycle if they want to access the same slave.
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SAM E70/S70/V70/V71 Family Bus Matrix (MATRIX) 5. 6. 7. 8. 16-beat bursts: predetermined end of burst is generated at the end of each 16-beat boundary during INCR transfer. 32-beat bursts: predetermined end of burst is generated at the end of each 32-beat boundary during INCR transfer. 64-beat bursts: predetermined end of burst is generated at the end of each 64-beat boundary during INCR transfer.
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SAM E70/S70/V70/V71 Family Bus Matrix (MATRIX) If more than one master requests the slave bus, regardless of the respective masters priorities, no master will be granted the slave bus for two consecutive runs. A master can only get back-to-back grants so long as it is the only requesting master. 19.3.3.2.1 Fixed Priority Arbitration The fixed priority arbitration algorithm is the first and only arbitration algorithm applied between masters from distinct priority pools.
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SAM E70/S70/V70/V71 Family Bus Matrix (MATRIX) 19.4 Register Summary Offset Name Bit Pos. MATRIX_MCFG0 7:0 15:8 23:16 31:24 ULBT[2:0] 0x00 ULBT[2:0] 0x30 MATRIX_MCFG12 7:0 15:8 23:16 31:24 0x34 ... 0x3F Reserved ... 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C MATRIX_SCFG0 MATRIX_SCFG1 MATRIX_SCFG2 MATRIX_SCFG3 MATRIX_SCFG4 MATRIX_SCFG5 MATRIX_SCFG6 MATRIX_SCFG7 0x60 MATRIX_SCFG8 0x64 ...
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SAM E70/S70/V70/V71 Family Bus Matrix (MATRIX) ...........continued Offset Name 0x84 MATRIX_PRBS0 0x88 MATRIX_PRAS1 0x8C MATRIX_PRBS1 0x90 MATRIX_PRAS2 0x94 MATRIX_PRBS2 0x98 MATRIX_PRAS3 0x9C MATRIX_PRBS3 0xA0 MATRIX_PRAS4 0xA4 MATRIX_PRBS4 0xA8 MATRIX_PRAS5 0xAC MATRIX_PRBS5 0xB0 MATRIX_PRAS6 0xB4 MATRIX_PRBS6 0xB8 MATRIX_PRAS7 Bit Pos.
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SAM E70/S70/V70/V71 Family Bus Matrix (MATRIX) ...........continued Offset Name 0xBC MATRIX_PRBS7 0xC0 MATRIX_PRAS8 0xC4 MATRIX_PRBS8 0xC8 ... 0xFF Reserved 0x0100 MATRIX_MRCR 0x0104 ... 0x010F Reserved 0x0110 CCFG_CAN0 0x0114 CCFG_SYSIO 0x0118 CCFG_PCCR 0x011C CCFG_DYNCKG 0x0120 ... 0x0123 Reserved 0x0124 CCFG_SMCNFCS 0x0128 ... 0x01E3 Reserved 0x01E4 MATRIX_WPMR 0x01E8 MATRIX_WPSR Bit Pos.
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SAM E70/S70/V70/V71 Family Bus Matrix (MATRIX) 19.4.1 Bus Matrix Master Configuration Registers Name: Offset: Reset: Property: MATRIX_MCFGx 0x00 + x*0x04 [x=0..12] 0x00000000 Read/Write This register can only be written if the WPEN bit is cleared in the Write Protection Mode Register.
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SAM E70/S70/V70/V71 Family Bus Matrix (MATRIX) Value 7 Name Description 128BEAT_BURST 128-beat Burst—The undefined length burst or bursts sequence is split into 128beat bursts or less, allowing re-arbitration every 128 beats. Note: Unless duly needed, the ULBT should be left at its default 0 value for power saving. © 2019 Microchip Technology Inc.
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SAM E70/S70/V70/V71 Family Bus Matrix (MATRIX) 19.4.2 Bus Matrix Slave Configuration Registers Name: Offset: Reset: Property: MATRIX_SCFGx 0x40 + x*0x04 [x=0..8] 0x000001FF Read/Write This register can only be written if the WPEN bit is cleared in the Write Protection Mode Register.
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SAM E70/S70/V70/V71 Family Bus Matrix (MATRIX) This limit has been placed in order to enforce arbitration so as to meet potential latency constraints of masters waiting for slave access. This limit must not be too small. Unreasonably small values break every burst and the MATRIX arbitrates without performing any data transfer. The default maximum value is usually an optimal conservative choice. In most cases, this feature is not needed and should be disabled for power saving.
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SAM E70/S70/V70/V71 Family Bus Matrix (MATRIX) 19.4.3 Bus Matrix Priority Registers A For Slaves Name: Offset: Reset: Property: MATRIX_PRASx 0x80 + x*0x08 [x=0..8] 0x00000222 Read/Write This register can only be written if the WPE bit is cleared in the Write Protection Mode Register.
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SAM E70/S70/V70/V71 Family Bus Matrix (MATRIX) 19.4.4 Bus Matrix Priority Registers B For Slaves Name: Offset: Reset: Property: MATRIX_PRBSx 0x84 + x*0x08 [x=0..8] 0x00000222 Read/Write This register can only be written if the WPE bit is cleared in the Write Protection Mode Register.
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SAM E70/S70/V70/V71 Family Bus Matrix (MATRIX) 19.4.5 Bus Matrix Master Remap Control Register Name: Offset: Reset: Property: MATRIX_MRCR 0x0100 0x00000000 Read/Write This register can only be written if the WPEN bit is cleared in the Write Protection Mode Register.
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SAM E70/S70/V70/V71 Family Bus Matrix (MATRIX) Value 1 Description Enables remapped address decoding for the selected Master. Bit 6 – RCB6 Remap Command Bit for Master 6 Value Description 0 Disables remapped address decoding for the selected Master. 1 Enables remapped address decoding for the selected Master. Bit 5 – RCB5 Remap Command Bit for Master 5 Value Description 0 Disables remapped address decoding for the selected Master. 1 Enables remapped address decoding for the selected Master.
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SAM E70/S70/V70/V71 Family Bus Matrix (MATRIX) 19.4.
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SAM E70/S70/V70/V71 Family Bus Matrix (MATRIX) 19.4.
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SAM E70/S70/V70/V71 Family Bus Matrix (MATRIX) 19.4.8 Peripheral Clock Configuration Register Name: Offset: Reset: Property: Bit CCFG_PCCR 0x0118 0x00022224 Read/Write 31 30 29 28 27 26 25 24 23 22 I2SC1CC 21 I2SC0CC 20 TC0CC 19 18 17 16 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access Reset Bit Access Reset Bit Access Reset Bit Access Reset Bit 22 – I2SC1CC I2SC1 Clock Configuration Value Description 0 Peripheral clock of I2SC1 is used. 1 GCLK is used.
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SAM E70/S70/V70/V71 Family Bus Matrix (MATRIX) 19.4.9 Dynamic Clock Gating Register Name: Offset: Reset: Property: CCFG_DYNCKG 0x011C 0 Read/Write Note: Clearing this register optimizes the power consumption of the system bus circuitry.
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SAM E70/S70/V70/V71 Family Bus Matrix (MATRIX) 19.4.
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SAM E70/S70/V70/V71 Family Bus Matrix (MATRIX) Value 0 1 Description NCS1 is not assigned to a NAND Flash (NANDOE and NANWE not used for NCS1). NCS1 is assigned to a NAND Flash (NANDOE and NANWE used for NCS1). Bit 0 – SMC_NFCS0 SMC NAND Flash Chip Select 0 Assignment Value Description 0 NCS0 is not assigned to a NAND Flash (NANDOE and NANWE not used for NCS0). 1 NCS0 is assigned to a NAND Flash (NANDOE and NANWE used for NCS0). © 2019 Microchip Technology Inc.
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SAM E70/S70/V70/V71 Family Bus Matrix (MATRIX) 19.4.
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SAM E70/S70/V70/V71 Family Bus Matrix (MATRIX) 19.4.
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SAM E70/S70/V70/V71 Family USB Transmitter Macrocell Interface (UTMI) 20. USB Transmitter Macrocell Interface (UTMI) 20.1 Description The USB Transmitter Macrocell Interface (UTMI) registers manage specific aspects of the integrated USB transmitter macrocell functionality not controlled in USB sections. 20.2 Embedded Characteristics • 32-bit UTMI Registers Control Product-specific Behavior © 2019 Microchip Technology Inc.
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SAM E70/S70/V70/V71 Family USB Transmitter Macrocell Interface (UTMI) 20.3 Register Summary Offset Name Bit Pos. 0x10 UTMI_OHCIICR 7:0 15:8 23:16 31:24 0x14 ... 0x2F Reserved 0x30 UTMI_CKTRIM APPSTART ARIE RESx UDPPUDIS 7:0 15:8 23:16 31:24 © 2019 Microchip Technology Inc.
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SAM E70/S70/V70/V71 Family USB Transmitter Macrocell Interface (UTMI) 20.3.
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SAM E70/S70/V70/V71 Family USB Transmitter Macrocell Interface (UTMI) 20.3.
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SAM E70/S70/V70/V71 Family Chip Identifier (CHIPID) 21. Chip Identifier (CHIPID) 21.1 Description Chip Identifier (CHIPID) registers are used to recognize the device and its revision. These registers provide the sizes and types of the on-chip memories, as well as the set of embedded peripherals. Two CHIPID registers are embedded: Chip ID Register (CHIPID_CIDR) and Chip ID Extension Register (CHIPID_EXID). Both registers contain a hard-wired value that is read-only.
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SAM E70/S70/V70/V71 Family Chip Identifier (CHIPID) ...........
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SAM E70/S70/V70/V71 Family Chip Identifier (CHIPID) 21.3 Register Summary Offset Name 0x00 CHIPID_CIDR 0x04 CHIPID_EXID Bit Pos. 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 EXT © 2019 Microchip Technology Inc.
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SAM E70/S70/V70/V71 Family Chip Identifier (CHIPID) 21.3.
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SAM E70/S70/V70/V71 Family Chip Identifier (CHIPID) Value 3 4 5 6 7 8 9 10 11 12 13 14 15 Name 6K 24K 4K 80K 160K 8K 16K 32K 64K 128K 256K 96K 512K Description 6 Kbytes 24 Kbytes 4 Kbytes 80 Kbytes 160 Kbytes 8 Kbytes 16 Kbytes 32 Kbytes 64 Kbytes 128 Kbytes 256 Kbytes 96 Kbytes 512 Kbytes Bits 15:12 – NVPSIZ2[3:0] Second Nonvolatile Program Memory Size Value Name Description 0 NONE None 1 8K 8 Kbytes 2 16K 16 Kbytes 3 32K 32 Kbytes 4 – Reserved 5 64K 64 Kbytes 6 – Reserved 7 128K 128 Kbytes 8 – Reserved
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SAM E70/S70/V70/V71 Family Chip Identifier (CHIPID) Value 1 2 3 4 5 6 7 Name ARM946ES ARM7TDMI CM3 ARM920T ARM926EJS CA5 CM4 Description ARM946ES ARM7TDMI Cortex-M3 ARM920T ARM926EJS Cortex-A5 Cortex-M4 Bits 4:0 – VERSION[4:0] Version of the Device Current version of the device. © 2019 Microchip Technology Inc.
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SAM E70/S70/V70/V71 Family Chip Identifier (CHIPID) 21.3.
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SAM E70/S70/V70/V71 Family Enhanced Embedded Flash Controller (EEFC) 22. 22.1 Enhanced Embedded Flash Controller (EEFC) Description The Enhanced Embedded Flash Controller (EEFC) provides the interface of the Flash block with the 32-bit internal bus. Its 128-bit wide memory interface increases performance. It also manages the programming, erasing, locking and unlocking sequences of the Flash using a full set of commands.
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SAM E70/S70/V70/V71 Family Enhanced Embedded Flash Controller (EEFC) • • • • • Two 128-bit read buffers used for code read optimization One 128-bit read buffer used for data read optimization One write buffer that manages page programming. The write buffer size is equal to the page size. This buffer is write-only and accessible all along the 1 Mbyte address space, so that each word can be written to its final address. Several lock bits used to protect write/erase operation on several pages (lock region).
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SAM E70/S70/V70/V71 Family Enhanced Embedded Flash Controller (EEFC) Figure 22-2. Organization of Embedded Flash for Code Memory Plane Start Address Page 0 Lock Region 0 Lock Bit 0 Lock Region 1 Lock Bit 1 Lock Region (n-1) Lock Bit (n-1) Page (m-1) Start Address + Flash size -1 22.4.2 Page (n*m-1) Read Operations An optimized controller manages embedded Flash reads, thus increasing performance when the processor is running in Thumb-2 mode by means of the 128-bit-wide memory interface.
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SAM E70/S70/V70/V71 Family Enhanced Embedded Flash Controller (EEFC) Figure 22-3.
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SAM E70/S70/V70/V71 Family Enhanced Embedded Flash Controller (EEFC) Figure 22-5. Code Loop Optimization Backward address jump Flash Memory 128-bit words Mb0 B0 B1 Mb1 Mp0 Mp1 L0 L1 L2 L3 L4 L5 Ln-5 Ln-4 Ln-3 Ln-2 Ln-1 Ln B2 B3 B4 B5 B6 B7 P0 P1 P2 P3 P4 P5 2x128-bit loop entry cache P6 P7 2x128-bit prefetch buffer Mb0 Branch Cache 0 L0 Loop Entry instruction Mp0 Prefetch Buffer 0 Mb1 Branch Cache 1 Ln Loop End instruction Mp1 Prefetch Buffer 1 22.4.2.
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SAM E70/S70/V70/V71 Family Enhanced Embedded Flash Controller (EEFC) ...........
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SAM E70/S70/V70/V71 Family Enhanced Embedded Flash Controller (EEFC) Figure 22-7. Command State Chart Read Status: EEFC_FSR No Check if FRDY flag Set Yes Write FCMD and PAGENB in Flash Command Register Read Status: EEFC_FSR No Check if FRDY flag Set Yes Yes Check if FLOCKE flag Set Locking region violation No Check if FCMDE flag Set Yes Bad keyword violation No Command Successful 22.4.3.1 Get Flash Descriptor Command This command provides the system with information on the Flash organization.
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SAM E70/S70/V70/V71 Family Enhanced Embedded Flash Controller (EEFC) ...........continued Symbol Word Index Description FL_NB_PLANE 3 Number of planes FL_PLANE[0] 4 Number of bytes in the plane FL_NB_LOCK 4 + FL_NB_PLANE Number of lock bits. A bit is associated with a lock region. A lock bit is used to prevent write or erase operations in the lock region. FL_LOCK[0] 4 + FL_NB_PLANE + 1 Number of bytes in the first lock region 22.4.3.2 Write Commands DMA write accesses must be 32-bit aligned.
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SAM E70/S70/V70/V71 Family Enhanced Embedded Flash Controller (EEFC) 22.4.3.2.1 Full Page Programming To program a full page, all the bits of the page must be erased before writing the latch buffer and issuing the WP command. The latch buffer must be written in ascending order, starting from the first address of the page. See Figure 22-8. 22.4.3.2.
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SAM E70/S70/V70/V71 Family Enhanced Embedded Flash Controller (EEFC) Figure 22-8.
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SAM E70/S70/V70/V71 Family Enhanced Embedded Flash Controller (EEFC) Figure 22-9.
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SAM E70/S70/V70/V71 Family Enhanced Embedded Flash Controller (EEFC) Figure 22-10.
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SAM E70/S70/V70/V71 Family Enhanced Embedded Flash Controller (EEFC) Figure 22-11.
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SAM E70/S70/V70/V71 Family Enhanced Embedded Flash Controller (EEFC) ...........continued FARG[1:0] Number of pages to be erased with EPA command 3 32 pages (not valid for small 8-KB sectors) 2. When erasing is completed, the EEFC_FSR.FRDY bit rises. If an interrupt has been enabled by setting the EEFC_FMR.FRDY bit, the interrupt line of the interrupt controller is activated.
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SAM E70/S70/V70/V71 Family Enhanced Embedded Flash Controller (EEFC) 22.4.3.5 GPNVM Bit GPNVM bits do not interfere with the embedded Flash memory plane. For more details, refer to the “Memories” chapter. The ‘Set GPNVM Bit’ sequence is the following: 1. 2. 3. Execute the ‘Set GPNVM Bit’ command by writing EEFC_FCR.FCMD with the SGPB command and EEFC_FCR.FARG with the number of GPNVM bits to be set. When the GPNVM bit is set, the bit EEFC_FSR.FRDY rises.
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SAM E70/S70/V70/V71 Family Enhanced Embedded Flash Controller (EEFC) 2. Calibration bits can be read by the software application in EEFC_FRR. The first word read corresponds to the first 32 calibration bits. The following reads provide the next 32 calibration bits as long as it is meaningful. Extra reads to EEFC_FRR return 0. The 8/12 MHz internal RC oscillator is calibrated in production. This calibration can be read through the GCALB command. Table 22-4 shows the bit implementation.
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SAM E70/S70/V70/V71 Family Enhanced Embedded Flash Controller (EEFC) Note: During the sequence, the software cannot be fetched from the Flash or from the second plane in case of dual plane. One error can be detected in EEFC_FSR after this sequence: • Command Error: A bad keyword has been written in EEFC_FCR. The sequence to write the user signature area is the following: 1. 2. 3. Write the full page, at any page address, within the internal memory area address space.
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SAM E70/S70/V70/V71 Family Enhanced Embedded Flash Controller (EEFC) 22.5 Register Summary Offset Name 0x00 EEFC_FMR 0x04 EEFC_FCR 0x08 EEFC_FSR 0x0C EEFC_FRR 0x10 ... 0xE3 Reserved 0xE4 EEFC_WPMR Bit Pos. 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 FVALUE[7:0] FVALUE[15:8] FVALUE[23:16] FVALUE[31:24] 7:0 15:8 23:16 31:24 WPKEY[7:0] WPKEY[15:8] WPKEY[23:16] © 2019 Microchip Technology Inc.
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SAM E70/S70/V70/V71 Family Enhanced Embedded Flash Controller (EEFC) 22.5.1 EEFC Flash Mode Register Name: Offset: Property: EEFC_FMR 0x00 Read/Write This register can only be written if the WPEN bit is cleared in the “EEFC Write Protection Mode Register” .
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SAM E70/S70/V70/V71 Family Enhanced Embedded Flash Controller (EEFC) 22.5.
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SAM E70/S70/V70/V71 Family Enhanced Embedded Flash Controller (EEFC) WP, WPL, EWP, EWPL Programming commands FARG must be written with the page number to be programmed SLB, CLB Lock bit commands FARG defines the page number to be locked or unlocked SGPB, CGPB GPNVM commands FARG defines the GPNVM number to be programmed Bits 7:0 – FCMD[7:0] Flash Command Value Name Description 0x00 GETD Get Flash descriptor 0x01 WP Write page 0x02 WPL Write page and lock 0x03 EWP Erase page and write page 0x04 EWPL
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SAM E70/S70/V70/V71 Family Enhanced Embedded Flash Controller (EEFC) 22.5.
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SAM E70/S70/V70/V71 Family Enhanced Embedded Flash Controller (EEFC) Value 1 Description A Flash memory error occurred at the end of programming (EraseVerify or WriteVerify test has failed). Bit 2 – FLOCKE Flash Lock Error Status (cleared on read) This flag is automatically cleared when EEFC_FSR is read or EEFC_FCR is written. Value Description 0 No programming/erase of at least one locked region has happened since the last read of EEFC_FSR.
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SAM E70/S70/V70/V71 Family Enhanced Embedded Flash Controller (EEFC) 22.5.4 EEFC Flash Result Register Name: Offset: Property: Bit EEFC_FRR 0x0C Read-only 31 30 29 28 27 FVALUE[31:24] 26 25 24 23 22 21 20 19 FVALUE[23:16] 18 17 16 15 14 13 12 11 FVALUE[15:8] 10 9 8 7 6 5 4 2 1 0 Access Reset Bit Access Reset Bit Access Reset Bit 3 FVALUE[7:0] Access Reset Bits 31:0 – FVALUE[31:0] Flash Result Value The result of a Flash command is returned in this register.
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SAM E70/S70/V70/V71 Family Enhanced Embedded Flash Controller (EEFC) 22.5.
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SAM E70/S70/V70/V71 Family Supply Controller (SUPC) 23. Supply Controller (SUPC) 23.1 Description The Supply Controller (SUPC) controls the supply voltages of the system and manages the Backup mode. In this mode, current consumption is reduced to a few microamps for backup power retention. Exit from this mode is possible on multiple wakeup sources. The SUPC also generates the slow clock by selecting either the slow RC oscillator or the 32.768 kHz crystal oscillator. 23.
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SAM E70/S70/V70/V71 Family Supply Controller (SUPC) 23.3 Block Diagram Figure 23-1.
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SAM E70/S70/V70/V71 Family Supply Controller (SUPC) 23.4 Functional Description 23.4.1 Overview The device is divided into two power supply areas: • • VDDIO power supply: includes the Supply Controller, part of the Reset Controller, the slow clock switch, the general-purpose backup registers, the supply monitor and the clock which includes the Real-time Timer and the Real-time Clock.
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SAM E70/S70/V70/V71 Family Supply Controller (SUPC) The user can also set the 32.768 kHz crystal oscillator in Bypass mode instead of connecting a crystal. In this case, the user has to provide the external clock signal on XIN32. The input characteristics of the XIN32 pin are given in the section “Electrical Characteristics”. To enter Bypass mode, the OSCBYPASS bit in the Mode register (SUPC_MR) must be set before setting XTALSEL. Related Links 58. Electrical Characteristics for SAM V70/V71 59.
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SAM E70/S70/V70/V71 Family Supply Controller (SUPC) When no separate backup supply for VDDIO is used, since the external voltage applied on VDDIO is kept, all of the I/O configurations (i.e., WKUP pin configuration) are maintained in Backup mode. When not using backup batteries, VDDIORDY is set so the user does not need to program it. Figure 23-3. No Separate Backup Supply Powering Scheme VDDUTMII USB Transceivers VDDIO Main Supply ADC, DAC Analog Comp.
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SAM E70/S70/V70/V71 Family Supply Controller (SUPC) Figure 23-4. Battery Backup VDDUTMII Backup Battery USB Transceivers VDDIO + ADC, DAC Analog Comp. VDDIN Main Supply IN OUT LDO Regulator VDDOUT Voltage Regulator VDDCORE ON/OFF VDDPLL VDDUTMIC External Wakeup Signal WKUPx PIOx (Output) Note: The two diodes provide a “switchover circuit” between the backup battery and the main supply when the system is put in Backup mode. 23.4.
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SAM E70/S70/V70/V71 Family Supply Controller (SUPC) Figure 23-5. Supply Monitor Status Bit and Associated Interrupt Continuous Sampling (SMSMPL = 1) Supply Monitor ON Periodic Sampling 3.3 V Threshold 0V Read SUPC_SR SMS and SUPC Interrupt Related Links 58. Electrical Characteristics for SAM V70/V71 59. Electrical Characteristics for SAM E70/S70 23.4.6 Backup Power Supply Reset 23.4.6.
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SAM E70/S70/V70/V71 Family Supply Controller (SUPC) Figure 23-6. Raising the VDDIO Power Supply TON Voltage 7 x Slow Clock Cycles (5 for startup slow RC + 2 for synchro.) Regulator 3 x Slow Clock 2 x Slow Clock Cycles Cycles 6.5 x Slow Clock Cycles Zero-Power POR Backup Power Supply Zero-Power Power-On Reset Cell output 22 - 42 kHz Slow RC Oscillator output vr_on Core Power Supply Fast RC Oscillator output bodcore_in vddcore_nreset RSTC.ERSTL default = 2 NRST (no ext.
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SAM E70/S70/V70/V71 Family Supply Controller (SUPC) 23.4.8 Controlling the SRAM Power Supply The SUPC can be used to switch on or off the power supply of the backup SRAM by opening or closing the SRAM power switch. This power switch is controlled by SUPC_MR.BKUPRETON. However, the battery backup SRAM is automatically switched on when the core power supply is enabled, as the processor requires the SRAM as data memory space. • • 23.4.9 If SUPC_MR.
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SAM E70/S70/V70/V71 Family Supply Controller (SUPC) If an enabled WKUP pin is asserted for a duration longer than the debouncing period, a wakeup of the core power supply is started and the signals, WKUP0 to WKUPx as shown in “Wakeup Sources”, are latched in SUPC_SR. This allows the user to identify the source of the wakeup. However, if a new wakeup condition occurs, the primary information is lost. No new wakeup can be detected since the primary wakeup condition has disappeared.
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SAM E70/S70/V70/V71 Family Supply Controller (SUPC) Figure 23-9. Low-power Debouncer (Push-to-Make Switch, Pull-up Resistors) MCU RTCOUTx Pull-up Resistor WKUP0 Pull-up Resistor GND WKUP1 GND GND Figure 23-10. Low-power Debouncer (Push-to-Break Switch, Pull-down Resistors) MCU RTCOUTx WKUP0 WKUP1 Pull-down Resistors GND GND GND The debouncing period duration is configurable. The period is set for all debouncers (i.e., the duration cannot be adjusted for each debouncer).
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SAM E70/S70/V70/V71 Family Supply Controller (SUPC) Figure 23-11. Using WKUP Pins Without RTCOUTx Pins VDDIO MCU Pull-up Resistor WKUP0 Pull-up Resistor GND WKUP1 GND GND Related Links 27. Real-time Clock (RTC) 23.4.9.3 Clock Alarms The RTC and the RTT alarms can generate a wakeup of the core power supply. This can be enabled by setting, respectively, SUPC_WUMR.RTCEN and SUPC_WUMR.RTTEN.
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SAM E70/S70/V70/V71 Family Supply Controller (SUPC) Note: 1. 2. 3. 4. See the section "Reset Controller (RSTC)". See the section "Real Time Timer (RTT)". See the section "Real Time Clock (RTC)". See the section "General Purpose Backup Registers (GPBR)". 23.4.
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SAM E70/S70/V70/V71 Family Supply Controller (SUPC) 23.5 Register Summary Offset Name 0x00 SUPC_CR 0x04 SUPC_SMMR 0x08 SUPC_MR 0x0C SUPC_WUMR 0x10 SUPC_WUIR 0x14 0x18 ... 0xD3 0xD4 SUPC_SR Bit Pos.
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SAM E70/S70/V70/V71 Family Supply Controller (SUPC) 23.5.
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SAM E70/S70/V70/V71 Family Supply Controller (SUPC) 23.5.2 Supply Controller Supply Monitor Mode Register Name: Offset: Reset: Property: SUPC_SMMR 0x04 0x00000000 Read/Write This register is located in the VDDIO domain.
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SAM E70/S70/V70/V71 Family Supply Controller (SUPC) 23.5.
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SAM E70/S70/V70/V71 Family Supply Controller (SUPC) Value 1 Description (DISABLE): The core brownout detector is disabled. Bit 12 – BODRSTEN Brownout Detector Reset Enable Note: This bit is located in the VDDIO domain. Value 0 1 Description (NOT_ENABLE): The core reset signal vddcore_nreset is not affected when a brownout detection occurs. (ENABLE): The core reset signal, vddcore_nreset is asserted when a brownout detection occurs. © 2019 Microchip Technology Inc.
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SAM E70/S70/V70/V71 Family Supply Controller (SUPC) 23.5.4 Supply Controller Wakeup Mode Register Name: Offset: Reset: Property: SUPC_WUMR 0x0C 0x00000000 Read/Write This register is located in the VDDIO domain.
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SAM E70/S70/V70/V71 Family Supply Controller (SUPC) Bit 6 – LPDBCEN1 Low-power Debouncer Enable WKUP1 Value Description 0 (NOT_ENABLE): The WKUP1 input pin is not connected to the low-power debouncer. 1 (ENABLE): The WKUP1 input pin is connected to the low-power debouncer and forces a system wakeup. Bit 5 – LPDBCEN0 Low-power Debouncer Enable WKUP0 Value Description 0 (NOT_ENABLE): The WKUP0 input pin is not connected to the low-power debouncer.
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SAM E70/S70/V70/V71 Family Supply Controller (SUPC) 23.5.5 Supply Controller Wakeup Inputs Register Name: Offset: Reset: Property: SUPC_WUIR 0x10 0x00000000 Read/Write This register is located in the VDDIO domain. This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register (SYSC_WPMR).
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SAM E70/S70/V70/V71 Family Supply Controller (SUPC) 23.5.6 Supply Controller Status Register Name: Offset: Reset: Property: SUPC_SR 0x14 0x00000000 Read-only Note: Because of the asynchronism between the Slow Clock (SLCK) and the System Clock (MCK), the status register flag reset is taken into account only 2 slow clock cycles after the read of the SUPC_SR. This register is located in the VDDIO domain.
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SAM E70/S70/V70/V71 Family Supply Controller (SUPC) Bit 6 – SMOS Supply Monitor Output Status Value Description 0 (HIGH): The supply monitor detected VDDIO higher than its threshold at its last measurement. 1 (LOW): The supply monitor detected VDDIO lower than its threshold at its last measurement. Bit 5 – SMS Value 0 1 Supply Monitor Status (cleared on read) Description (NO): No supply monitor detection since the last read of SUPC_SR.
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SAM E70/S70/V70/V71 Family Supply Controller (SUPC) 23.5.
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SAM E70/S70/V70/V71 Family Watchdog Timer (WDT) 24. 24.1 Watchdog Timer (WDT) Description The Watchdog Timer (WDT) is used to prevent system lock-up if the software becomes trapped in a deadlock. It features a 12-bit down counter that allows a watchdog period of up to 16 seconds (slow clock around 32 kHz). It can generate a general reset or a processor reset only. In addition, it can be stopped while the processor is in Debug mode or Sleep mode (Idle mode). 24.2 Embedded Characteristics • • • • 24.
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SAM E70/S70/V70/V71 Family Watchdog Timer (WDT) 24.4 Functional Description The Watchdog Timer is used to prevent system lock-up if the software becomes trapped in a deadlock. It is supplied with VDDCORE. It restarts with initial values on processor reset. The watchdog is built around a 12-bit down counter, which is loaded with the value defined in the field WDV of the Mode Register (WDT_MR).
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SAM E70/S70/V70/V71 Family Watchdog Timer (WDT) Figure 24-2. Watchdog Behavior Watchdog Error Watchdog Underflow if WDRSTEN is 1 FFF Normal behavior if WDRSTEN is 0 WDV Forbidden Window WDD Permitted Window 0 Watchdog Fault © 2019 Microchip Technology Inc. WDT_CR.
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SAM E70/S70/V70/V71 Family Watchdog Timer (WDT) 24.5 Register Summary Offset Name 0x00 WDT_CR 0x04 0x08 WDT_MR WDT_SR Bit Pos. 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 WDRSTT WDDIS © 2019 Microchip Technology Inc.
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SAM E70/S70/V70/V71 Family Watchdog Timer (WDT) 24.5.1 Watchdog Timer Control Register Name: Offset: Reset: Property: WDT_CR 0x00 – Write-only The WDT_CR register values must not be modified within three slow clock periods following a restart of the watchdog performed by a write access in WDT_CR. Any modification will cause the watchdog to trigger an end of period earlier than expected.
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SAM E70/S70/V70/V71 Family Watchdog Timer (WDT) 24.5.2 Watchdog Timer Mode Register Name: Offset: Reset: Property: WDT_MR 0x04 0x3FFF2FFF Read/Write Once The first write access prevents any further modification of the value of this register. Read accesses remain possible. The WDT_MR register values must not be modified within three slow clock periods following a restart of the watchdog performed by a write access in WDT_CR.
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SAM E70/S70/V70/V71 Family Watchdog Timer (WDT) Value 1 Description A watchdog fault (underflow or error) triggers a watchdog reset. Bit 12 – WDFIEN Watchdog Fault Interrupt Enable Value Description 0 A watchdog fault (underflow or error) has no effect on interrupt. 1 A watchdog fault (underflow or error) asserts interrupt. Bits 11:0 – WDV[11:0] Watchdog Counter Value Defines the value loaded in the 12-bit watchdog counter. © 2019 Microchip Technology Inc.
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SAM E70/S70/V70/V71 Family Watchdog Timer (WDT) 24.5.3 Watchdog Timer Status Register Name: Offset: Reset: Property: Bit WDT_SR 0x08 0x00000000 Read-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 WDERR R 0 0 WDUNF R 0 Access Reset Bit Access Reset Bit Access Reset Bit Access Reset Bit 1 – WDERR Watchdog Error (cleared on read) Value Description 0 No watchdog error occurred since the last read of WDT_SR.
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SAM E70/S70/V70/V71 Family Reinforced Safety Watchdog Timer (RSWDT) 25. 25.1 Reinforced Safety Watchdog Timer (RSWDT) Description The Reinforced Safety Watchdog Timer (RSWDT) works in parallel with the Watchdog Timer (WDT) to reinforce safe watchdog operations. The RSWDT can be used to reinforce the safety level provided by the WDT in order to prevent system lock-up if the software becomes trapped in a deadlock. The RSWDT works in a fully operable mode, independent of the WDT.
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SAM E70/S70/V70/V71 Family Reinforced Safety Watchdog Timer (RSWDT) 25.3 Block Diagram Figure 25-1. Reinforced Safety Watchdog Timer Block Diagram main RC frequency main RC clock write RSWDT_MR RSWDT_MR WDV RSWDT_CR WDRSTT reload 1 divider Automatic selection [CKGR_MOR.MOSCRCEN = 0 and (WDT_MR.WDDIS or SUPC_MR.
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SAM E70/S70/V70/V71 Family Reinforced Safety Watchdog Timer (RSWDT) In normal operation, the user reloads the watchdog at regular intervals before the timer underflow occurs, by setting bit RSWDT_CR.WDRSTT. The watchdog counter is then immediately reloaded from the RSWDT_MR and restarted, and the slow clock 128 divider is reset and restarted. The RSWDT_CR is write-protected. As a result, writing RSWDT_CR without the correct hard-coded key has no effect.
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SAM E70/S70/V70/V71 Family Reinforced Safety Watchdog Timer (RSWDT) 25.5 Register Summary Offset Name 0x00 RSWDT_CR 0x04 0x08 RSWDT_MR RSWDT_SR Bit Pos. 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 WDRSTT WDDIS © 2019 Microchip Technology Inc.
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SAM E70/S70/V70/V71 Family Reinforced Safety Watchdog Timer (RSWDT) 25.5.
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SAM E70/S70/V70/V71 Family Reinforced Safety Watchdog Timer (RSWDT) 25.5.2 Reinforced Safety Watchdog Timer Mode Register Name: Offset: Reset: Property: RSWDT_MR 0x04 0x3FFFAFFF Read/Write Once Note: The first write access prevents any further modification of the value of this register; read accesses remain possible.
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SAM E70/S70/V70/V71 Family Reinforced Safety Watchdog Timer (RSWDT) Value 1 Description A Watchdog fault (underflow or error) asserts interrupt. Bits 11:0 – WDV[11:0] Watchdog Counter Value Defines the value loaded in the 12-bit watchdog counter. © 2019 Microchip Technology Inc.
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SAM E70/S70/V70/V71 Family Reinforced Safety Watchdog Timer (RSWDT) 25.5.3 Reinforced Safety Watchdog Timer Status Register Name: Offset: Reset: Property: Bit RSWDT_SR 0x08 0x00000000 Read-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WDUNF Access Reset Bit Access Reset Bit Access Reset Bit Access Reset 0 Bit 0 – WDUNF Watchdog Underflow Value Description 0 No watchdog underflow occurred since the last read of RSWDT_SR.
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SAM E70/S70/V70/V71 Family Reset Controller (RSTC) 26. Reset Controller (RSTC) 26.1 Description The Reset Controller (RSTC), driven by Power-On Reset (POR) cells, software, external reset pin and peripheral events, handles all the resets of the system without any external components. It reports which reset occurred last. The RSTC also drives simultaneously the external reset and the peripheral and processor resets. 26.2 Embedded Characteristics • • • • 26.
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SAM E70/S70/V70/V71 Family Reset Controller (RSTC) 26.4 Functional Description 26.4.1 Overview The RSTC is made up of an NRST manager and a reset state manager. It runs at SLCK frequency and generates the following reset signals: • • • proc_nreset: Processor reset line (also resets the Watchdog Timer) periph_nreset: Affects the whole set of embedded peripherals nrst_out: Drives the NRST pin Note: proc_nreset and periph_nreset are driven in the same way.
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SAM E70/S70/V70/V71 Family Reset Controller (RSTC) This feature allows the RSTC to shape the NRST pin level, and thus to guarantee that the NRST line is driven low for a time compliant with potential external devices connected on the system reset. RSTC_MR is backed up, making it possible to use the value of ERSTL to shape the system powerup reset for devices requiring a longer startup time than that of the MCU. 26.4.
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SAM E70/S70/V70/V71 Family Reset Controller (RSTC) The Watchdog Timer is reset by the proc_nreset signal. As the watchdog fault always causes a processor reset if WDT_MR.WDRSTEN is written to ‘1’, the Watchdog Timer is always reset after a watchdog reset, and the Watchdog is enabled by default and with a period set to a maximum. When WDT_MR.WDRSTEN is written to ‘0’, the watchdog fault has no impact on the RSTC. After a watchdog overflow occurs, the report on the RSTC_SR.
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SAM E70/S70/V70/V71 Family Reset Controller (RSTC) Figure 26-5. Software Reset Timing Diagram SLCK Up to 1 SLCK cycle Write RSTC_CR Main RC Oscillator MCK Any Frequency. Any Frequency. 3 SLCK cycles + 2 MCK cycles RSTTYP Processor and Peripherals Reset Line NRST (nrst_out) if EXTRST=1 XXX Inactive 0x3 = Software Reset Inactive Active Min = 2 SLCK cycles if ERSTL=0 (e.g. 8 if ERSTL=2) Inactive Active Inactive RSTC_SR.SRCMP 26.4.3.
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SAM E70/S70/V70/V71 Family Reset Controller (RSTC) Figure 26-6. User Reset Timing Diagram SLCK NRST pin 2 SLCK cycles Main RC Oscillator MCK RSTTYP Processor and Peripherals Reset Line Any Frequency. Any Frequency. XXX 0x4 = User Reset 6 SLCK cycles Inactive Inactive Active Min = 2 SLCK cycles if ERSTL=0 (e.g. 8 if ERSTL=2) NRST (nrst_out) 26.4.4 Inactive Active Inactive Reset State Priorities The reset state manager manages the priorities among the different reset sources.
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SAM E70/S70/V70/V71 Family Reset Controller (RSTC) 26.4.5 Offset 0x00 0x04 0x08 Register Summary Name RSTC_CR RSTC_SR RSTC_MR Bit Pos. 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 © 2019 Microchip Technology Inc.
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SAM E70/S70/V70/V71 Family Reset Controller (RSTC) 26.4.5.
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SAM E70/S70/V70/V71 Family Reset Controller (RSTC) 26.4.5.2 RSTC Status Register Name: Offset: Reset: Property: RSTC_SR 0x04 0x00000000 Read-only The register reset value assumes that a general reset has been performed; it is subject to change if other types of reset are generated.
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SAM E70/S70/V70/V71 Family Reset Controller (RSTC) Value 0 1 Description No high-to-low edge on NRST happened since the last read of RSTC_SR. At least one high-to-low transition of NRST has been detected since the last read of RSTC_SR. © 2019 Microchip Technology Inc.
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SAM E70/S70/V70/V71 Family Reset Controller (RSTC) 26.4.5.3 RSTC Mode Register Name: Offset: Reset: Property: RSTC_MR 0x08 0x00000001 Read/Write This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register (SYSC_WPMR).
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SAM E70/S70/V70/V71 Family Real-time Clock (RTC) 27. 27.1 Real-time Clock (RTC) Description The Real-time Clock (RTC) peripheral is designed for very low power consumption. For optimal functionality, the RTC requires an accurate external 32.768 kHz clock, which can be provided by a crystal oscillator. It combines a complete time-of-day clock with alarm and a Gregorian or Persian calendar, complemented by a programmable periodic interrupt. The alarm and calendar registers are accessed by a 32-bit data bus.
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SAM E70/S70/V70/V71 Family Real-time Clock (RTC) 27.4 27.4.1 Product Dependencies Power Management The Real-time Clock is continuously clocked at 32.768 kHz. The Power Management Controller has no effect on RTC behavior. 27.4.2 Interrupt Within the System Controller, the RTC interrupt is OR-wired with all the other module interrupts. Only one System Controller interrupt line is connected on one of the internal sources of the interrupt controller.
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SAM E70/S70/V70/V71 Family Real-time Clock (RTC) Note: To change one of the SEC, MIN, HOUR, DATE, MONTH fields, it is recommended to disable the field before changing the value and then re-enable it after the change has been made. This requires up to three accesses to the RTC_TIMALR or RTC_CALALR. The first access clears the enable corresponding to the field to change (SECEN, MINEN, HOUREN, DATEEN, MTHEN). If the field is already cleared, this access is not required.
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SAM E70/S70/V70/V71 Family Real-time Clock (RTC) The timing sequence of the time/calendar update is described in the figure below. When entering the programming mode of the calendar fields, the time fields remain enabled and both the time and the calendar fields are stopped. This is due to the location of the calendar logical circuity (downstream for low-power considerations). It is highly recommended to prepare all the fields to be updated before entering programming mode.
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SAM E70/S70/V70/V71 Family Real-time Clock (RTC) Figure 27-3. Gregorian and Persian Modes Update Sequence Begin Prepare Time or Calendar Fields Wait for second periodic event Set UPDTIM and/or UPDCAL bit(s) in RTC_CR Read RTC_SR Polling or IRQ (if enabled) ACKUPD = 1? No Yes Clear ACKUPD bit in RTC_SCCR Update Time and/or Calendar values in RTC_TIMR/RTC_CALR Clear UPDTIM and/or UPDCAL bit in RTC_CR End © 2019 Microchip Technology Inc.
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SAM E70/S70/V70/V71 Family Real-time Clock (RTC) RTC Accurate Clock Calibration The crystal oscillator that drives the RTC may not be as accurate as expected mainly due to temperature variation. The RTC is equipped with circuitry able to correct slow clock crystal drift.
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SAM E70/S70/V70/V71 Family Real-time Clock (RTC) Figure 27-5. Calibration Circuitry Waveforms Monotonic 1 Hz Counter value 32.768 kHz +50 ppm Phase adjustment (~4 ms) Nominal 32.768 kHz 32.
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SAM E70/S70/V70/V71 Family Real-time Clock (RTC) The clock calibration correction drives the internal RTC counters but can also be observed in the RTC output when one of the following three frequencies 1 Hz, 32 Hz or 64 Hz is configured. The correction is not visible in the RTC output if 512 Hz frequency is configured. Note: This adjustment does not consider the temperature variation.
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SAM E70/S70/V70/V71 Family Real-time Clock (RTC) Figure 27-6. Waveform Generation ‘0’ 0 ‘0’ 0 1 Hz 1 1 Hz 1 32 Hz 2 32 Hz 2 64 Hz 3 64 Hz 3 512 Hz 4 512 Hz 4 toggle_alarm 5 toggle_alarm 5 flag_alarm 6 flag_alarm 6 pulse 7 pulse 7 RTCOUT0 RTC_MR(OUT0) RTCOUT1 RTC_MR(OUT1) alarm match event 2 alarm match event 1 flag_alarm RTC_SCCR(ALRCLR) RTC_SCCR(ALRCLR) toggle_alarm pulse Thigh Tperiod Tperiod © 2019 Microchip Technology Inc.
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SAM E70/S70/V70/V71 Family Real-time Clock (RTC) 27.6 Register Summary Offset Name 0x00 RTC_CR 0x04 RTC_MR 0x08 RTC_TIMR 0x0C RTC_CALR 0x10 RTC_TIMALR 0x14 RTC_CALALR 0x18 RTC_SR 0x1C RTC_SCCR 0x20 RTC_IER 0x24 RTC_IDR 0x28 RTC_IMR 0x2C RTC_VER Bit Pos.
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SAM E70/S70/V70/V71 Family Real-time Clock (RTC) 27.6.1 RTC Control Register Name: Offset: Reset: Property: RTC_CR 0x00 0x00000000 Read/Write This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register (SYSC_WPMR).
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SAM E70/S70/V70/V71 Family Real-time Clock (RTC) Value 0 1 Description No effect or, if UPDTIM has been previously written to 1, stops the update procedure. Stops the RTC time counting. © 2019 Microchip Technology Inc.
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SAM E70/S70/V70/V71 Family Real-time Clock (RTC) 27.6.2 RTC Mode Register Name: Offset: Reset: Property: RTC_MR 0x04 0x00000000 Read/Write This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register (SYSC_WPMR).
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SAM E70/S70/V70/V71 Family Real-time Clock (RTC) Value 6 7 Name ALARM_FLAG PROG_PULSE Description Output is a copy of the alarm flag Duty cycle programmable pulse Bits 18:16 – OUT0[2:0] RTCOUT0 Output Source Selection Value Name Description 0 NO_WAVE No waveform, stuck at ‘0’ 1 FREQ1HZ 1 Hz square wave 2 FREQ32HZ 32 Hz square wave 3 FREQ64HZ 64 Hz square wave 4 FREQ512HZ 512 Hz square wave 5 ALARM_TOGGLE Output toggles when alarm flag rises 6 ALARM_FLAG Output is a copy of the alarm flag 7 PROG_PULSE Dut
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SAM E70/S70/V70/V71 Family Real-time Clock (RTC) Value 1 Description 12-hour mode is selected. © 2019 Microchip Technology Inc.
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SAM E70/S70/V70/V71 Family Real-time Clock (RTC) 27.6.
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SAM E70/S70/V70/V71 Family Real-time Clock (RTC) 27.6.
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SAM E70/S70/V70/V71 Family Real-time Clock (RTC) 27.6.5 RTC Time Alarm Register Name: Offset: Reset: Property: RTC_TIMALR 0x10 0x00000000 Read/Write This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register (SYSC_WPMR). To change one of the SEC, MIN, HOUR fields, it is recommended to disable the field before changing the value and then re-enable it after the change has been made. This requires up to three accesses to the RTC_TIMALR.
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SAM E70/S70/V70/V71 Family Real-time Clock (RTC) Value 0 1 Description The second-matching alarm is disabled. The second-matching alarm is enabled. Bits 6:0 – SEC[6:0] Second Alarm This field is the alarm field corresponding to the BCD-coded second counter. © 2019 Microchip Technology Inc.
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SAM E70/S70/V70/V71 Family Real-time Clock (RTC) 27.6.6 RTC Calendar Alarm Register Name: Offset: Reset: Property: RTC_CALALR 0x14 0x01010000 Read/Write This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register (SYSC_WPMR). To change one of the DATE, MONTH fields, it is recommended to disable the field before changing the value and then re-enable it after the change has been made. This requires up to three accesses to the RTC_CALALR.
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SAM E70/S70/V70/V71 Family Real-time Clock (RTC) 27.6.
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SAM E70/S70/V70/V71 Family Real-time Clock (RTC) Value 1 Name ALARMEVENT Description An alarm matching condition has occurred. Bit 0 – ACKUPD Acknowledge for Update Value Name Description 0 FREERUN Time and calendar registers cannot be updated. 1 UPDATE Time and calendar registers can be updated. © 2019 Microchip Technology Inc.
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SAM E70/S70/V70/V71 Family Real-time Clock (RTC) 27.6.8 RTC Status Clear Command Register Name: Offset: Reset: Property: Bit RTC_SCCR 0x1C – Write-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 TDERRCLR W – 4 CALCLR W – 3 TIMCLR W – 2 SECCLR W – 1 ALRCLR W – 0 ACKCLR W – Access Reset Bit Access Reset Bit Access Reset Bit Access Reset Bit 5 – TDERRCLR Time and/or Date Free Running Error Clear Value Description 0 No effect.
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SAM E70/S70/V70/V71 Family Real-time Clock (RTC) 27.6.9 RTC Interrupt Enable Register Name: Offset: Reset: Property: Bit RTC_IER 0x20 – Write-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 TDERREN W – 4 CALEN W – 3 TIMEN W – 2 SECEN W – 1 ALREN W – 0 ACKEN W – Access Reset Bit Access Reset Bit Access Reset Bit Access Reset Bit 5 – TDERREN Time and/or Date Error Interrupt Enable Value Description 0 No effect.
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SAM E70/S70/V70/V71 Family Real-time Clock (RTC) 27.6.10 RTC Interrupt Disable Register Name: Offset: Reset: Property: Bit RTC_IDR 0x24 – Write-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 TDERRDIS W – 4 CALDIS W – 3 TIMDIS W – 2 SECDIS W – 1 ALRDIS W – 0 ACKDIS W – Access Reset Bit Access Reset Bit Access Reset Bit Access Reset Bit 5 – TDERRDIS Time and/or Date Error Interrupt Disable Value Description 0 No effect.
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SAM E70/S70/V70/V71 Family Real-time Clock (RTC) 27.6.11 RTC Interrupt Mask Register Name: Offset: Reset: Property: Bit RTC_IMR 0x28 0x00000000 Read-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 TDERR R 0 4 CAL R 0 3 TIM R 0 2 SEC R 0 1 ALR R 0 0 ACK R 0 Access Reset Bit Access Reset Bit Access Reset Bit Access Reset Bit 5 – TDERR Time and/or Date Error Mask Value Description 0 The time and/or date error event is disabled.
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SAM E70/S70/V70/V71 Family Real-time Clock (RTC) 27.6.
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SAM E70/S70/V70/V71 Family Real-time Timer (RTT) 28. Real-time Timer (RTT) 28.1 Description The Real-time Timer (RTT) is built around a 32-bit counter used to count roll-over events of the programmable 16-bit prescaler driven from the 32-kHz slow clock source. It generates a periodic interrupt and/or triggers an alarm on a programmed value. The RTT can also be configured to be driven by the 1Hz RTC signal, thus taking advantage of a calibrated 1Hz clock.
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SAM E70/S70/V70/V71 Family Real-time Timer (RTT) The real-time 32-bit counter can also be supplied by the 1Hz RTC clock. This mode is interesting when the RTC 1Hz is calibrated (CORRECTION field ≠ 0 in RTC_MR) in order to guaranty the synchronism between RTC and RTT counters. Setting the RTC1HZ bit in the RTT_MR drives the 32-bit RTT counter from the 1Hz RTC clock. In this mode, the RTPRES field has no effect on the 32-bit counter.
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SAM E70/S70/V70/V71 Family Real-time Timer (RTT) Figure 28-2. RTT Counting SLCK RTPRES - 1 Prescaler 0 CRTV 0 ... ALMV-1 ALMV ALMV+1 ALMV+2 ALMV+3 RTTINC (RTT_SR) ALMS (RTT_SR) APB Interface APB cycle © 2019 Microchip Technology Inc.
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SAM E70/S70/V70/V71 Family Real-time Timer (RTT) 28.5 Register Summary Offset Name 0x00 RTT_MR 0x04 RTT_AR 0x08 RTT_VR 0x0C RTT_SR Bit Pos. 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 © 2019 Microchip Technology Inc.
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SAM E70/S70/V70/V71 Family Real-time Timer (RTT) 28.5.
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SAM E70/S70/V70/V71 Family Real-time Timer (RTT) RTPRES is defined as follows: • RTPRES = 0: The prescaler period is equal to 216 * SLCK periods. • RTPRES = 1 or 2: forbidden. • RTPRES ≠ 0,1 or 2: The prescaler period is equal to RTPRES * SLCK periods. © 2019 Microchip Technology Inc.
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SAM E70/S70/V70/V71 Family Real-time Timer (RTT) 28.5.2 Real-time Timer Alarm Register Name: Offset: Reset: Property: RTT_AR 0x04 0xFFFFFFFF Read/Write The alarm interrupt must be disabled (ALMIEN must be cleared in RTT_MR) when writing a new ALMV value.
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SAM E70/S70/V70/V71 Family Real-time Timer (RTT) 28.5.
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SAM E70/S70/V70/V71 Family Real-time Timer (RTT) 28.5.4 Real-time Timer Status Register Name: Offset: Reset: Property: Bit RTT_SR 0x0C 0x00000000 Read-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 RTTINC R 0 0 ALMS R 0 Access Reset Bit Access Reset Bit Access Reset Bit Access Reset Bit 1 – RTTINC Prescaler Roll-over Status (cleared on read) Value Description 0 No prescaler roll-over occurred since the last read of the RTT_SR.
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SAM E70/S70/V70/V71 Family General Purpose Backup Registers (GPBR) 29. General Purpose Backup Registers (GPBR) 29.1 Description The System Controller embeds 128 bits of General Purpose Backup registers organized as 8 32-bit registers. It is possible to generate an immediate clear of the content of General Purpose Backup registers 0 to 3 (first half) if a Low-power Debounce event is detected on one of the wakeup pins, WKUP0 or WKUP1.
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SAM E70/S70/V70/V71 Family General Purpose Backup Registers (GPBR) 29.3 Register Summary Offset Name Bit Pos. 0x00 SYS_GPBRx 7:0 15:8 23:16 31:24 © 2019 Microchip Technology Inc.
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SAM E70/S70/V70/V71 Family General Purpose Backup Registers (GPBR) 29.3.1 General Purpose Backup Register x Name: Offset: Reset: Property: SYS_GPBRx 0x00 0 R/W These registers are reset at first power-up and on each loss of VDDIO.
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SAM E70/S70/V70/V71 Family Clock Generator 30. Clock Generator 30.1 Description The Clock Generator user interface is embedded within the Power Management Controller and is described in Power Management Controller (PMC) User Interface. However, the Clock Generator registers are named CKGR_. 30.2 Embedded Characteristics The Clock Generator is comprised of the following: • • • • • • A low-power 32.
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SAM E70/S70/V70/V71 Family Clock Generator 30.3 Block Diagram Figure 30-1. Clock Generator Block Diagram Clock Generator SUPC_CR.XTALSEL Slow RC Oscillator 0 Slow Clock (SLCK) XOUT32 32.768 kHz Crystal Oscillator XIN32 1 CKGR_MOR SUPC_MR.OSCBYPASS MOSCSEL Main RC Oscillator 0 CKGR_MOR.MOSCXTBY Main Clock (MAINCK) XIN XOUT Main Crystal Oscillator Status 1 PLLA and Divider PLLA Clock (PLLACK) USB UTMI PLL UPLL Clock (UPLLCK) Control Power Management Controller User Interface 30.
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SAM E70/S70/V70/V71 Family Clock Generator Compared to the 32.768 kHz crystal oscillator, this oscillator offers a faster startup time and is less exposed to the external environment, as it is fully integrated. However, its output frequency is subject to larger variations with supply voltage, temperature and manufacturing process. Therefore, the user must take these variations into account when this oscillator is used as a time base (startup counter, frequency monitor, etc.).
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SAM E70/S70/V70/V71 Family Clock Generator Figure 30-2. Main Clock (MAINCK) Block Diagram CKGR_MOR MOSCRCEN CKGR_MOR MOSCRCF PMC_SR MOSCRCS Main RC Oscillator CKGR_MOR PMC_SR MOSCSEL MOSCSELS 0 CKGR_MOR MAINCK Main Clock MOSCXTEN 1 XIN XOUT 30.5.1 Main Crystal Oscillator Main RC Oscillator After reset, the Main RC oscillator is enabled with the 12 MHz frequency selected. This oscillator is selected as the source of MAINCK. MAINCK is the default clock selected to start the system.
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SAM E70/S70/V70/V71 Family Clock Generator By default, SEL4/SEL8/SEL12 are cleared, so the Main RC oscillator is driven with the factory-programmed Flash calibration bits which are programmed during chip production. In order to calibrate the oscillator lower frequency, SEL4 must be set to ‘1’ and a valid frequency value must be configured in CAL4. Likewise, SEL8/12 must be set to ‘1’ and a trim value must be configured in CAL8/12 in order to adjust the other frequencies of the oscillator.
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SAM E70/S70/V70/V71 Family Clock Generator 30.5.5 Bypassing the Main Crystal Oscillator Prior to bypassing the Main crystal oscillator, the external clock frequency provided on the XIN pin must be stable and within the values specified in the XIN Clock characteristics in the section “Electrical Characteristics”. The sequence is as follows: 1. Ensure that an external clock is connected on XIN. 2. Enable the bypass by setting CKGR_MOR.MOSCXTBY. 3. Disable the Main crystal oscillator by clearing CKGR_MOR.
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SAM E70/S70/V70/V71 Family Clock Generator Figure 30-3. Main Frequency Counter Block Diagram MOSCXTST PMC_SR Main Crystal Oscillator Startup Counter SLCK MOSCXTS CKGR_MOR MOSCRCEN CKGR_MOR CKGR_MCFR MOSCXTEN RCMEAS CKGR_MOR MOSCSEL CKGR_MCFR Main RC Oscillator Reference Clock 0 MAINF Main Frequency Counter CKGR_MCFR MAINFRDY Main Crystal Oscillator 1 CCSS CKGR_MCFR 30.6 PLLA Clock The PLLA clock (PLLACK) is generated from MAINCK by the PLLA and a predivider.
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SAM E70/S70/V70/V71 Family Clock Generator Whenever the PLL is re-enabled or one of its parameters is changed, the LOCK (LOCKA) bit in PMC_SR is automatically cleared. The values written in the PLLCOUNT field (PLLACOUNT) in CKGR_PLLR (CKGR_PLLAR) are loaded in the PLL counter. The PLL counter then decrements at the speed of SLCK until it reaches ‘0’. At this time, PMC_SR.LOCK is set and can trigger an interrupt to the processor.
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SAM E70/S70/V70/V71 Family Power Management Controller (PMC) 31. Power Management Controller (PMC) 31.1 Description The Power Management Controller (PMC) optimizes power consumption by controlling all system and user peripheral clocks. The PMC enables/disables the clock inputs to many of the peripherals and the Cortex-M7 processor. The Supply Controller selects either the Slow RC oscillator or the 32.768 kHz crystal oscillator as the source of SLCK.
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SAM E70/S70/V70/V71 Family Power Management Controller (PMC) 31.3 Block Diagram Figure 31-1. General Clock Distribution Block Diagram Clock Generator Processor Clock Controller SUPC_CR.XTALSEL Processor Clock (HCLK) int Sleep Mode Slow RC Oscillator 0 Divider /2 Slow Clock (SLCK) XIN32 XOUT32 32.
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SAM E70/S70/V70/V71 Family Power Management Controller (PMC) Refer to the section “ARM Cortex-M7 Processor” for details on selecting the SysTick external clock. Related Links 15. ARM Cortex-M7 (ARM) 31.7 USB Full-speed Clock Controller The user can select the PLLA or the UPLL output as the USB FS clock (USB_48M) by writing a ‘1’ to the USBS bit in the USB Clock Register (PMC_USB). The user then must program the corresponding PLL to generate an appropriate frequency depending on the USBDIV bit in PMC_USB.
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SAM E70/S70/V70/V71 Family Power Management Controller (PMC) SLCK, MAINCK, UPLLCKDIV, PLLACK and MCK. Refer to the description of each peripheral for the limitation to be applied to GCLK[PID] compared to periph_clk[PID]. To configure a peripheral’s clocks, PMC_PCR.CMD must be written to ‘1’ and PMC_PCR.PID must be written with the index of the corresponding peripheral. All other configuration fields must be correctly set. To read the current clock configuration of a peripheral, PMC_PCR.
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SAM E70/S70/V70/V71 Family Power Management Controller (PMC) 31.10.2.1 Configuration Procedure Before configuring SleepWalking for a peripheral, check that the PIDx bit in PMC_PCSR is set. This ensures that the peripheral clock is enabled. The steps to enable SleepWalking for a peripheral are the following: 1. 2. 3. 4. Check that the corresponding PIDx bit in the PMC SleepWalking Activity Status register (PMC_SLPWK_ASR) is set to ‘0’. This ensures that the peripheral has no activity in progress.
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SAM E70/S70/V70/V71 Family Power Management Controller (PMC) 3. Check that the corresponding PIDx bit in PMC_SLPWK_ASR is set to ‘0’. This ensures that no activity has started during the enable phase. If an activity has started during the enable phase, the asynchronous partial wakeup function must be immediately disabled by writing a ‘1’ to the PIDx bit in the PMC SleepWalking Disable register (PMC_SLPWK_DR). Wait for the end of peripheral activity before reinitializing the procedure. 31.
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SAM E70/S70/V70/V71 Family Power Management Controller (PMC) Figure 31-4. Fast Startup Circuitry FSTT0 WKUP0 FSTP0 FSTT13 WKUP13 FSTP13 FSTT14 GMAC Wake on LAN event FSTP14 FSTT15 fast_restart Processor CDBGPWRUPREQ FSTP15 RTTAL RTT Alarm RTCAL RTC Alarm USBAL USBHS Interrupt Line Each wakeup input pin and alarm can be enabled to generate a fast startup event by setting the corresponding bit in PMC_FSMR. The user interface does not provide any status for fast startup.
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SAM E70/S70/V70/V71 Family Power Management Controller (PMC) The failure detector can be enabled or disabled by configuring the CKGR_MOR.CFDEN, and it can also be disabled in either of the following cases: • • After a VDDCORE reset When the Main crystal oscillator is disabled (MOSCXTEN = 0) A failure is detected by means of a counter incrementing on the Main crystal oscillator output and detection logic is triggered by the Slow RC oscillator which is automatically enabled when CFDEN = 1.
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SAM E70/S70/V70/V71 Family Power Management Controller (PMC) The monitored clock frequency is declared invalid if at least 4 consecutive clock period measurement results are over the nominal period ±10%. Note that modifying the trimming values of the Main RC oscillator (PMC_OCR) may impact the monitor accuracy and lead to inappropriate failure detection. Due to the possible frequency variation of the Main RC oscillator acting as reference clock for the monitor logic, any 32.
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SAM E70/S70/V70/V71 Family Power Management Controller (PMC) 7. Select MCK and HCLK: MCK and HCLK are configurable via PMC_MCKR. CSS is used to select the clock source of MCK and HCLK. By default, the selected clock source is MAINCK. PRES is used to define the HCLK and MCK prescaler.s The user can choose between different values (1, 2, 3, 4, 8, 16, 32, 64). Prescaler output is the selected clock source frequency divided by the PRES value. MDIV is used to define the MCK divider.
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SAM E70/S70/V70/V71 Family Power Management Controller (PMC) PMC_PCKx.PRES is used to control the PCKx prescaler. It is possible to choose between different values (1 to 256). PCKx output is prescaler input divided by PRES. By default, the PRES value is cleared which means that PCKx is equal to Slow clock. Once PMC_PCKx has been configured, the corresponding PCKx must be enabled and the user must wait for PMC_SR.PCKRDYx to be set. This can be done either by polling PMC_SR.
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SAM E70/S70/V70/V71 Family Power Management Controller (PMC) 31.18.2 Clock Switching Waveforms Figure 31-6. Switch Master Clock (MCK) from Slow Clock to PLLx Clock Slow Clock PLLx Clock LOCK MCKRDY MCK Write PMC_MCKR Figure 31-7. Switch Master Clock (MCK) from Main Clock (MAINCK) to Slow Clock Slow Clock MAINCK MCKRDY MCK Write PMC_MCKR © 2019 Microchip Technology Inc.
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SAM E70/S70/V70/V71 Family Power Management Controller (PMC) Figure 31-8. Change PLLA Programming Slow Clock PLLA Clock LOCKA MCKRDY MCK Slow Clock Write CKGR_PLLAR Figure 31-9. Programmable Clock Output Programming Any PLL Clock PCKRDY PCKx Output Write PMC_PCKx PLL Clock is selected Write PMC_SCER PCKx is enabled PCKx is disabled Write PMC_SCDR 31.
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SAM E70/S70/V70/V71 Family Power Management Controller (PMC) • • • • • • • • • • • • • • • • • • • 31.
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SAM E70/S70/V70/V71 Family Power Management Controller (PMC) ...........
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SAM E70/S70/V70/V71 Family Power Management Controller (PMC) 31.20.1 PMC System Clock Enable Register Name: Offset: Property: PMC_SCER 0x0000 Write-only This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
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SAM E70/S70/V70/V71 Family Power Management Controller (PMC) 31.20.2 PMC System Clock Disable Register Name: Offset: Property: PMC_SCDR 0x0004 Write-only This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
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SAM E70/S70/V70/V71 Family Power Management Controller (PMC) 31.20.
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SAM E70/S70/V70/V71 Family Power Management Controller (PMC) 31.20.4 PMC Peripheral Clock Enable Register 0 Name: Offset: Property: PMC_PCER0 0x0010 Write-only This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
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SAM E70/S70/V70/V71 Family Power Management Controller (PMC) 31.20.5 PMC Peripheral Clock Disable Register 0 Name: Offset: Property: PMC_PCDR0 0x0014 Write-only This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
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SAM E70/S70/V70/V71 Family Power Management Controller (PMC) 31.20.
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SAM E70/S70/V70/V71 Family Power Management Controller (PMC) 31.20.7 PMC UTMI Clock Configuration Register Name: Offset: Reset: Property: CKGR_UCKR 0x001C 0x10200800 Read/Write This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
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SAM E70/S70/V70/V71 Family Power Management Controller (PMC) 31.20.8 PMC Clock Generator Main Oscillator Register Name: Offset: Reset: Property: CKGR_MOR 0x0020 0x00000008 Read/Write This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
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SAM E70/S70/V70/V71 Family Power Management Controller (PMC) Value 1 2 Name Description 8_MHz The RC oscillator frequency is at 8 MHz 12_MHz The RC oscillator frequency is at 12 MHz Note: MOSCRCF must be changed only if MOSCRCS is set in the PMC_SR. Therefore MOSCRCF and MOSCRCEN cannot be changed at the same time. Bit 3 – MOSCRCEN Main RC Oscillator Enable When MOSCRCEN is set, the MOSCRCS flag is set once the Main RC oscillator startup time is achieved.
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SAM E70/S70/V70/V71 Family Power Management Controller (PMC) 31.20.9 PMC Clock Generator Main Clock Frequency Register Name: Offset: Reset: Property: CKGR_MCFR 0x0024 0x00000000 Read/Write This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
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SAM E70/S70/V70/V71 Family Power Management Controller (PMC) 31.20.10 PMC Clock Generator PLLA Register Name: Offset: Reset: Property: CKGR_PLLAR 0x0028 0x00003F00 Read/Write Possible limitations on PLLA input frequencies and multiplier factors should be checked before using the PMC. WARNING Bit 29 must always be set to ‘1’ when programming the CKGR_PLLAR. This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
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SAM E70/S70/V70/V71 Family Power Management Controller (PMC) 31.20.11 PMC Master Clock Register Name: Offset: Reset: Property: PMC_MCKR 0x0030 0x00000001 Read/Write This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register. Bit UPLLDIV2 UPLL Clock Division 0 UPLLCK frequency is divided by 1. 1 UPLLCK frequency is divided by 2.
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SAM E70/S70/V70/V71 Family Power Management Controller (PMC) Value 0 1 2 3 Name SLOW_CLK MAIN_CLK PLLA_CLK UPLL_CLK © 2019 Microchip Technology Inc.
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SAM E70/S70/V70/V71 Family Power Management Controller (PMC) 31.20.12 PMC USB Clock Register Name: Offset: Reset: Property: PMC_USB 0x0038 0x00000000 Read/Write This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
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SAM E70/S70/V70/V71 Family Power Management Controller (PMC) 31.20.13 PMC Programmable Clock Register Name: Offset: Reset: Property: PMC_PCKx [x=0..7] 0x0040 0 Read/Write This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
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SAM E70/S70/V70/V71 Family Power Management Controller (PMC) 31.20.14 PMC Interrupt Enable Register Name: Offset: Property: PMC_IER 0x0060 Write-only The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Enables the corresponding interrupt.
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SAM E70/S70/V70/V71 Family Power Management Controller (PMC) 31.20.15 PMC Interrupt Disable Register Name: Offset: Property: PMC_IDR 0x0064 Write-only The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Disables the corresponding interrupt.
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SAM E70/S70/V70/V71 Family Power Management Controller (PMC) 31.20.
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SAM E70/S70/V70/V71 Family Power Management Controller (PMC) Bit 16 – MOSCSELS Main Clock Source Oscillator Selection Status Value Description 0 Selection is in progress. 1 Selection is done. Bits 8, 9, 10, 11, 12, 13, 14, 15 – PCKRDY Programmable Clock Ready Status Value Description 0 Programmable Clock x is not ready. 1 Programmable Clock x is ready. Bit 7 – OSCSELS Slow Clock Source Oscillator Selection Value Description 0 Slow RC oscillator is selected. 1 32.768 kHz crystal oscillator is selected.
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SAM E70/S70/V70/V71 Family Power Management Controller (PMC) 31.20.17 PMC Interrupt Mask Register Name: Offset: Reset: Property: PMC_IMR 0x006C 0x00000000 Read-only The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Enables the corresponding interrupt.
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SAM E70/S70/V70/V71 Family Power Management Controller (PMC) 31.20.18 PMC Fast Startup Mode Register Name: Offset: Reset: Property: PMC_FSMR 0x0070 0x00000000 Read/Write This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
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SAM E70/S70/V70/V71 Family Power Management Controller (PMC) Bit 16 – RTTAL RTT Alarm Enable Value Description 0 The RTT alarm has no effect on the PMC. 1 The RTT alarm enables a fast restart signal to the PMC. Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 – FSTT Fast Startup Input Enable Value Description 0 The corresponding wake-up input has no effect on the PMC. 1 The corresponding wake-up input enables a fast restart signal to the PMC. © 2019 Microchip Technology Inc.
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SAM E70/S70/V70/V71 Family Power Management Controller (PMC) 31.20.19 PMC Fast Startup Polarity Register Name: Offset: Reset: Property: PMC_FSPR 0x0074 0x00000000 Read/Write This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
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SAM E70/S70/V70/V71 Family Power Management Controller (PMC) 31.20.20 PMC Fault Output Clear Register Name: Offset: Property: Bit PMC_FOCR 0x0078 Write-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FOCLR Access Reset Bit Access Reset Bit Access Reset Bit Access Reset Bit 0 – FOCLR Fault Output Clear Clears the clock failure detector fault output. © 2019 Microchip Technology Inc.
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SAM E70/S70/V70/V71 Family Power Management Controller (PMC) 31.20.
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SAM E70/S70/V70/V71 Family Power Management Controller (PMC) 31.20.
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SAM E70/S70/V70/V71 Family Power Management Controller (PMC) 31.20.23 PMC Peripheral Clock Enable Register 1 Name: Offset: Property: PMC_PCER1 0x0100 Write-only This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
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SAM E70/S70/V70/V71 Family Power Management Controller (PMC) 31.20.
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SAM E70/S70/V70/V71 Family Power Management Controller (PMC) 31.20.
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SAM E70/S70/V70/V71 Family Power Management Controller (PMC) 31.20.
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SAM E70/S70/V70/V71 Family Power Management Controller (PMC) Bits 6:0 – PID[6:0] Peripheral ID Peripheral ID selection from PID2 to PID127. “PID2 to PID127” refers to identifiers as defined in section “Peripheral Identifiers”. © 2019 Microchip Technology Inc.
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SAM E70/S70/V70/V71 Family Power Management Controller (PMC) 31.20.27 PMC Oscillator Calibration Register Name: Offset: Reset: Property: PMC_OCR 0x0110 0x00404040 Read/Write This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
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SAM E70/S70/V70/V71 Family Power Management Controller (PMC) 31.20.28 PMC SleepWalking Enable Register 0 Name: Offset: Property: PMC_SLPWK_ER0 0x0114 Write-only This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
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SAM E70/S70/V70/V71 Family Power Management Controller (PMC) 31.20.29 PMC SleepWalking Enable Register 1 Name: Offset: Property: PMC_SLPWK_ER1 0x0134 Write-only This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
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SAM E70/S70/V70/V71 Family Power Management Controller (PMC) 31.20.30 PMC SleepWalking Disable Register 0 Name: Offset: Property: PMC_SLPWK_DR0 0x0118 Write-only This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
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SAM E70/S70/V70/V71 Family Power Management Controller (PMC) 31.20.31 PMC SleepWalking Disable Register 1 Name: Offset: Property: PMC_SLPWK_DR1 0x0138 Write-only This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
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SAM E70/S70/V70/V71 Family Power Management Controller (PMC) 31.20.
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SAM E70/S70/V70/V71 Family Power Management Controller (PMC) 31.20.
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SAM E70/S70/V70/V71 Family Power Management Controller (PMC) 31.20.
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SAM E70/S70/V70/V71 Family Power Management Controller (PMC) 31.20.35 PLL Maximum Multiplier Value Register Name: Offset: Reset: Property: PMC_PMMR 0x0130 0x000007FF Read/Write This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
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SAM E70/S70/V70/V71 Family Power Management Controller (PMC) 31.20.
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SAM E70/S70/V70/V71 Family Power Management Controller (PMC) 31.20.37 PMC SleepWalking Activity In Progress Register Name: Offset: Property: Bit PMC_SLPWK_AIPR 0x0144 Read-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AIP Access Reset Bit Access Reset Bit Access Reset Bit Access Reset Bit 0 – AIP Activity In Progress Only the following PIDs can be configured with asynchronous partial wakeup: UARTx and TWIHSx.
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) 32. 32.1 Parallel Input/Output Controller (PIO) Description The Parallel Input/Output Controller (PIO) manages up to 32 fully programmable input/output lines. Each I/O line may be dedicated as a general-purpose I/O or be assigned to a function of an embedded peripheral. This ensures effective optimization of the pins of the product.
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) 32.3 Block Diagram Figure 32-1. Block Diagram PIODCCLK Data DMA Parallel Capture Mode Events PIODC[7:0] PIODCEN1 PIODCEN2 Interrupt Controller PMC PIO Interrupt PIO Controller Peripheral Clock Data, Enable Up to x peripheral IOs Embedded Peripheral PIN 0 Data, Enable PIN 1 Up to x peripheral IOs Embedded Peripheral PIN x-1 x is an integer representing the maximum number of IOs managed by one PIO controller. APB Table 32-1.
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) hardware designer and programmer must carefully determine the configuration of the PIO Controllers required by their application. When an I/O line is general-purpose only, i.e., not multiplexed with any peripheral I/O, programming of the PIO Controller regarding the assignment to a peripheral has no effect and only the PIO Controller can control how the pin is driven by the product. 32.4.
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) Figure 32-2.
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) 32.5.2 I/O Line or Peripheral Function Selection When a pin is multiplexed with one or two peripheral functions, the selection is controlled with the Enable Register (PIO_PER) and the Disable Register (PIO_PDR). The Status Register (PIO_PSR) is the result of the set and clear registers and indicates whether the pin is controlled by the corresponding peripheral or by the PIO Controller.
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) Similarly, writing in PIO_SODR and PIO_CODR affects PIO_ODSR. This is important as it defines the first level driven on the I/O line. 32.5.5 Synchronous Data Output Clearing one or more PIO line(s) and setting another one or more PIO line(s) synchronously cannot be done by using PIO_SODR and PIO_CODR. It requires two successive write operations into two different registers.
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) The selection between glitch filtering or debounce filtering is done by writing in the PIO Input Filter Slow Clock Disable Register (PIO_IFSCDR) and the PIO Input Filter Slow Clock Enable Register (PIO_IFSCER). Writing PIO_IFSCDR and PIO_IFSCER, respectively, sets and clears bits in the Input Filter Slow Clock Status Register (PIO_IFSCSR). The current selection status can be checked by reading the PIO_IFSCSR.
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) 32.5.10 Input Edge/Level Interrupt The PIO Controller can be programmed to generate an interrupt when it detects an edge or a level on an I/O line. The Input Edge/Level interrupt is controlled by writing the Interrupt Enable Register (PIO_IER) and the Interrupt Disable Register (PIO_IDR), which enable and disable the input change interrupt respectively by setting and clearing the corresponding bit in the Interrupt Mask Register (PIO_IMR).
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) • • • • • • • • • Rising edge on PIO line 0 Falling edge on PIO line 1 Rising edge on PIO line 2 Low-level on PIO line 3 High-level on PIO line 4 High-level on PIO line 5 Falling edge on PIO line 6 Rising edge on PIO line 7 Any edge on the other lines The following table provides the required configuration for this example. Table 32-2.
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) 59. Electrical Characteristics for SAM E70/S70 32.5.13 Programmable Schmitt Trigger It is possible to configure each input for the Schmitt trigger. By default the Schmitt trigger is active. Disabling the Schmitt trigger is requested when using the QTouch® Library. 32.5.14 Parallel Capture Mode 32.5.14.
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) The Parallel Capture mode can be associated with a reception channel of the DMA Controller. This performs reception transfer from Parallel Capture mode to a memory buffer without any intervention from the CPU. The Parallel Capture mode can take into account the sensor data enable signals or not.
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) Figure 32-12. Parallel Capture Mode Waveforms (DSIZE = 2, ALWYS = 0, HALFS = 1, FRSTS = 0) MCK PIODCLK PIODC[7:0] 0x01 0x12 0x23 0x34 0x45 0x56 0x67 0x78 0x89 PIODCEN1 PIODCEN2 DRDY (PIO_PCISR) Read of PIO_PCISR 0x6745_2301 RDATA (PIO_PCRHR) Figure 32-13.
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) 32.5.14.4.2 With DMA 1. Write PIO_PCIDR and PIO_PCIER in order to configure the Parallel Capture mode interrupt mask. 2. Configure DMA transfer in DMA registers. 3. Write PIO_PCMR to set the fields DSIZE, ALWYS, HALFS and FRSTS in order to configure the Parallel Capture mode WITHOUT enabling the Parallel Capture mode. 4.
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) ...........continued Register Value to be Written PIO_PPDER 0x00F0_0000 PIO_ABCDSR1 0xF0F0_0000 PIO_ABCDSR2 0xFF00_0000 PIO_OWER 0x0000_000F PIO_OWDR 0x0FFF_FFF0 32.5.16 Register Write Protection To prevent any single software error from corrupting PIO behavior, certain registers in the address space can be write-protected by setting the WPEN bit in the PIO Write Protection Mode Register (PIO_WPMR).
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) 32.6 Register Summary Offset Name 0x00 PIO_PER 0x04 PIO_PDR 0x08 PIO_PSR 0x0C ... 0x0F Reserved 0x10 PIO_OER 0x14 PIO_ODR 0x18 PIO_OSR 0x1C ... 0x1F Reserved 0x20 PIO_IFER 0x24 PIO_IFDR 0x28 PIO_IFSR 0x2C ... 0x2F Reserved 0x30 PIO_SODR 0x34 PIO_CODR Bit Pos.
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) ...........continued Offset Name 0x38 PIO_ODSR 0x3C PIO_PDSR 0x40 PIO_IER 0x44 PIO_IDR 0x48 PIO_IMR 0x4C PIO_ISR 0x50 PIO_MDER 0x54 PIO_MDDR 0x58 PIO_MDSR 0x5C ... 0x5F Reserved 0x60 PIO_PUDR 0x64 PIO_PUER 0x68 PIO_PUSR 0x6C ... 0x6F Reserved 0x70 PIO_ABCDSR1 Bit Pos.
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) ...........continued Offset Name Bit Pos. 0x74 PIO_ABCDSR2 7:0 15:8 23:16 31:24 P7 P15 P23 P31 P6 P14 P22 P30 P5 P13 P21 P29 P4 P12 P20 P28 P3 P11 P19 P27 P2 P10 P18 P26 P1 P9 P17 P25 P0 P8 P16 P24 0x78 ...
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) ...........continued Offset Name 0xB4 PIO_AIMDR 0xB8 PIO_AIMMR 0xBC ... 0xBF Reserved 0xC0 PIO_ESR 0xC4 PIO_LSR 0xC8 PIO_ELSR 0xCC ... 0xCF Reserved 0xD0 PIO_FELLSR 0xD4 PIO_REHLSR 0xD8 PIO_FRLHSR 0xDC ... 0xDF Reserved 0xE0 PIO_LOCKSR 0xE4 PIO_WPMR 0xE8 PIO_WPSR 0xEC ... 0xFF Reserved Bit Pos.
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) ...........continued Offset Name Bit Pos. 0x0100 PIO_SCHMITT 7:0 15:8 23:16 31:24 SCHMITT7 SCHMITT15 SCHMITT23 SCHMITT31 SCHMITT6 SCHMITT14 SCHMITT22 SCHMITT30 SCHMITT5 SCHMITT13 SCHMITT21 SCHMITT29 SCHMITT4 SCHMITT12 SCHMITT20 SCHMITT28 SCHMITT3 SCHMITT11 SCHMITT19 SCHMITT27 SCHMITT2 SCHMITT10 SCHMITT18 SCHMITT26 SCHMITT1 SCHMITT9 SCHMITT17 SCHMITT25 SCHMITT0 SCHMITT8 SCHMITT16 SCHMITT24 0x0104 ...
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) 32.6.1.1 PIO Enable Register Name: Offset: Property: PIO_PER 0x0000 Write-only This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) 32.6.1.2 PIO Disable Register Name: Offset: Property: PIO_PDR 0x0004 Write-only This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) 32.6.1.
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) 32.6.1.4 PIO Output Enable Register Name: Offset: Property: PIO_OER 0x0010 Write-only This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) 32.6.1.5 PIO Output Disable Register Name: Offset: Property: PIO_ODR 0x0014 Write-only This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) 32.6.1.
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) 32.6.1.7 PIO Input Filter Enable Register Name: Offset: Property: PIO_IFER 0x0020 Write-only This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) 32.6.1.8 PIO Input Filter Disable Register Name: Offset: Property: PIO_IFDR 0x0024 Write-only This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) 32.6.1.
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) 32.6.1.
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) 32.6.1.
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) 32.6.1.
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) 32.6.1.
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) 32.6.1.
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) 32.6.1.
PAGE 341
SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) 32.6.1.
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) 32.6.1.
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) 32.6.1.18 PIO Multi-driver Enable Register Name: Offset: Property: PIO_MDER 0x0050 Write-only This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) 32.6.1.19 PIO Multi-driver Disable Register Name: Offset: Property: PIO_MDDR 0x0054 Write-only This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) 32.6.1.
PAGE 346
SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) 32.6.1.21 PIO Pull-Up Disable Register Name: Offset: Property: PIO_PUDR 0x0060 Write-only This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) 32.6.1.22 PIO Pull-Up Enable Register Name: Offset: Property: PIO_PUER 0x0064 Write-only This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) 32.6.1.
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) 32.6.1.24 PIO Peripheral ABCD Select Register 1 Name: Offset: Reset: Property: PIO_ABCDSR1 0x0070 0x00000000 Read/Write This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) 32.6.1.25 PIO Peripheral ABCD Select Register 2 Name: Offset: Reset: Property: PIO_ABCDSR2 0x0074 0x00000000 Read/Write This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) 32.6.1.
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) 32.6.1.
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) 32.6.1.
PAGE 354
SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) 32.6.1.
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) 32.6.1.30 PIO Pad Pull-Down Disable Register Name: Offset: Property: PIO_PPDDR 0x0090 Write-only This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) 32.6.1.31 PIO Pad Pull-Down Enable Register Name: Offset: Property: PIO_PPDER 0x0094 Write-only This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) 32.6.1.
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) 32.6.1.33 PIO Output Write Enable Register Name: Offset: Property: PIO_OWER 0x00A0 Write-only This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) 32.6.1.34 PIO Output Write Disable Register Name: Offset: Property: PIO_OWDR 0x00A4 Write-only This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) 32.6.1.
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) 32.6.1.
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) 32.6.1.
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) 32.6.1.
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) 32.6.1.
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) 32.6.1.
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) 32.6.1.
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) 32.6.1.
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) 32.6.1.
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) 32.6.1.
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) 32.6.1.
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) 32.6.1.
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) 32.6.1.
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) 32.6.1.
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) 32.6.1.
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) 32.6.1.50 PIO Parallel Capture Mode Register Name: Offset: Reset: Property: PIO_PCMR 0x0150 0x00000000 Read/Write This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) Value 1 Description The Parallel Capture mode is enabled. © 2019 Microchip Technology Inc.
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) 32.6.1.
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) 32.6.1.
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) 32.6.1.53 PIO Parallel Capture Interrupt Mask Register Name: Offset: Reset: Property: PIO_PCIMR 0x015C 0x00000000 Read-only The following configuration values are valid for all listed bit names of this register: 0: Corresponding interrupt is not enabled. 1: Corresponding interrupt is enabled.
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) 32.6.1.
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SAM E70/S70/V70/V71 Family Parallel Input/Output Controller (PIO) 32.6.1.
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SAM E70/S70/V70/V71 Family External Bus Interface 33. External Bus Interface 33.1 Description The External Bus Interface (EBI) is designed to ensure the successful data transfer between several external devices and the embedded Memory Controller of an ARM-based device. The Static Memory and SDRAM Controllers are all featured external Memory Controllers on the EBI.
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SAM E70/S70/V70/V71 Family External Bus Interface 33.3 EBI Block Diagram Figure 33-1.
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SAM E70/S70/V70/V71 Family External Bus Interface ...........
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SAM E70/S70/V70/V71 Family External Bus Interface 33.5 33.5.1 Application Example Hardware Interface The following table details the connections to be applied between the EBI pins and the external devices for each Memory Controller. Table 33-3.
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SAM E70/S70/V70/V71 Family External Bus Interface Note: NWR1 enables upper byte writes. NWR0 enables lower byte writes. Table 33-4.
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SAM E70/S70/V70/V71 Family External Bus Interface 33.5.2 Product Dependencies 33.5.2.1 I/O Lines The pins used for interfacing the External Bus Interface may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the External Bus Interface pins to their peripheral function. If I/O lines of the External Bus Interface are not used by the application, they can be used for other purposes by the PIO Controller. 33.5.
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SAM E70/S70/V70/V71 Family External Bus Interface 33.5.4 Implementation Examples The following hardware configurations are given for illustration only. The user should refer to the memory manufacturer web site to check current device availability. 33.5.4.1 16-bit SDRAM on NCS1 Figure 33-2. Hardware Configuration Software Configuration The following configuration has to be performed: • • Enable the SDRAM support by setting the bit SDRAMEN field in the CCFG_SMCNFCS Register in the Bus Matrix.
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SAM E70/S70/V70/V71 Family SDRAM Controller (SDRAMC) 34. SDRAM Controller (SDRAMC) 34.1 Description The SDRAM Controller (SDRAMC) extends the memory capabilities of a chip by providing the interface to external 16-bit DRAM devices. The page size supports ranges from 2048 to 8192 and the number of columns from 256 to 2048. It supports byte (8-bit), half-word (16-bit) and word (32-bit) accesses. The SDRAMC supports a read or write burst length of one location.
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SAM E70/S70/V70/V71 Family SDRAM Controller (SDRAMC) ...........continued 34.4 Name Description Type Active Level RAS Row Signal Output Low CAS Column Signal Output Low SDWE SDRAM Write Enable Output Low NBS[1:0] Data Mask Enable Signals Output Low SDRAMC_A[12:0] Address Bus Output – D[15:0] Data Bus I/O – Software Interface/SDRAM Organization, Address Mapping The SDRAM address space is organized into banks, rows, and columns.
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SAM E70/S70/V70/V71 Family SDRAM Controller (SDRAMC) ...........contin ued CPU Address Line 27 26 25 24 Bk[1:0] Bk[1:0] 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Row[12:0] Column[9:0] Row[12:0] M0 Column[10:0] M0 Note: M0 is the byte address inside a 16-bit half-word and Bk[1] = BA1, Bk[0] = BA0. 34.5 Product Dependencies 34.5.1 SDRAM Device Initialization The initialization sequence is generated by software. The sequence to initialize SDRAM devices is the following: 1.
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SAM E70/S70/V70/V71 Family SDRAM Controller (SDRAMC) Figure 34-1. SDRAM Device Initialization Sequence SDCKE tRP tRFC tMRD SDCK SDRAMC_A[9:0] A10 SDRAMC_A[12:11] SDCS RAS CAS SDWE NBS Inputs stable for 200 μs 34.5.2 Precharge All Banks 1st Autorefresh 8th Autorefresh MRS Command Valid Command I/O Lines The pins used for interfacing the SDRAMC may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the SDRAMC pins to their peripheral function.
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SAM E70/S70/V70/V71 Family SDRAM Controller (SDRAMC) Figure 34-2. Write Burst SDRAM Access tRCD SDCS SDCK SDRAMC_A[12:0] Row n col a col b col c col d col e col f col g col h col i col j col k col l Dnb Dnc Dnd Dne Dnf Dng Dnh Dni Dnj Dnk Dnl RAS CAS SDWE DATA 34.6.2 Dna SDRAM Controller Read Cycle The SDRAMC allows burst access, incremental burst of unspecified length or single access.
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SAM E70/S70/V70/V71 Family SDRAM Controller (SDRAMC) Figure 34-3. Read Burst SDRAM Access tRCD CAS SDCS SDCK SDRAMC_A[12:0] Row n col a col b col c col d col e col f RAS CAS SDWE DATA (Input) 34.6.3 Dna Dnb Dnc Dne Dnd Dnf Border Management When the memory row boundary has been reached, an automatic page break is inserted. In this case, the SDRAMC generates a precharge command, activates the new row and initiates a read or write command.
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SAM E70/S70/V70/V71 Family SDRAM Controller (SDRAMC) A refresh error interrupt is generated when the previous autorefresh command did not perform. It is acknowledged by reading the Interrupt Status register (SDRAMC_ISR). When the SDRAMC initiates a refresh of the SDRAM device, internal memory accesses are not delayed. However, if the processor tries to access the SDRAM, the slave indicates that the device is busy and the master is held by a wait signal. Refer to the following figure. Figure 34-5.
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SAM E70/S70/V70/V71 Family SDRAM Controller (SDRAMC) Figure 34-6. Self-refresh Mode Behavior Self-refresh Mode tXSR LPCB = 1 Write SDRAMC_LPR Row SDRAMC_A[12:0] SDCK SDCKE SDCS RAS CAS SDWE Access Request to the SDRAM Controller 34.6.5.2 Low-power Mode This mode is selected by configuring SDRAMC_LPR.LPCB to 2. Power consumption is greater than in Self-refresh mode. All the input and output buffers of the SDRAM device are deactivated except SDCKE, which remains low.
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SAM E70/S70/V70/V71 Family SDRAM Controller (SDRAMC) 34.6.5.3 Deep Powerdown Mode This mode is selected by configuring SDRAMC_LPR.LPCB to 3. When this mode is activated, all internal voltage generators inside the SDRAM are stopped and all data is lost. When this mode is enabled, the application must not access the SDRAM until a new initialization sequence is done (see “SDRAM Device Initialization”). Refer to the following figure. Figure 34-8.
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SAM E70/S70/V70/V71 Family SDRAM Controller (SDRAMC) 34.7 Register Summary Offset Name 0x00 SDRAMC_MR 0x04 SDRAMC_TR 0x08 SDRAMC_CR 0x0C ... 0x0F Reserved 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 SDRAMC_LPR SDRAMC_IER SDRAMC_IDR SDRAMC_IMR SDRAMC_ISR SDRAMC_MDR SDRAMC_CFR1 0x2C SDRAMC_OCMS 0x30 SDRAMC_OCMS_K EY1 0x34 SDRAMC_OCMS_K EY2 Bit Pos.
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SAM E70/S70/V70/V71 Family SDRAM Controller (SDRAMC) 34.7.1 SDRAMC Mode Register Name: Offset: Reset: Property: Bit SDRAMC_MR 0x00 0x00000000 Read/Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 MODE[2:0] R/W 0 0 Access Reset Bit Access Reset Bit Access Reset Bit Access Reset R/W 0 R/W 0 Bits 2:0 – MODE[2:0] SDRAMC Command Mode This field defines the command issued by the SDRAMC when the SDRAM device is accessed.
PAGE 400
SAM E70/S70/V70/V71 Family SDRAM Controller (SDRAMC) 34.7.
PAGE 401
SAM E70/S70/V70/V71 Family SDRAM Controller (SDRAMC) 34.7.3 SDRAMC Configuration Register Name: Offset: Reset: Property: WARNING Bit 31 SDRAMC_CR 0x08 0x852372C0 Read/Write Bit 7 (DBW) must always be set when programming the SDRAMC_CR.
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SAM E70/S70/V70/V71 Family SDRAM Controller (SDRAMC) The number of cycles is between 0 and 15. The end user must program max {tRC, tRFC}. Bits 11:8 – TWR[3:0] Write Recovery Delay Reset value is two cycles. This field defines the Write Recovery Time in number of cycles. Number of cycles is between 0 and 15. Bit 7 – DBW Data Bus Width Reset value is 16 bits. This bit defines the Data Bus Width, which is 16 bits. It must be set to 1. Value Description 0 Data bus width is 32 bits. 1 Data bus width is 16 bits.
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SAM E70/S70/V70/V71 Family SDRAM Controller (SDRAMC) 34.7.
PAGE 404
SAM E70/S70/V70/V71 Family SDRAM Controller (SDRAMC) After initialization, as soon as the PASR field is modified and Self-refresh mode is activated, the Extended Mode Register is accessed automatically and PASR bits are updated before entry in Self-refresh mode. This feature is not supported when SDRAMC shares an external bus with another controller.
PAGE 405
SAM E70/S70/V70/V71 Family SDRAM Controller (SDRAMC) 34.7.5 SDRAMC Interrupt Enable Register Name: Offset: Property: Bit SDRAMC_IER 0x14 Write-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RES W Access Reset Bit Access Reset Bit Access Reset Bit Access Reset Bit 0 – RES Value 0 1 Refresh Error Interrupt Enable Description No effect. Enables the refresh error interrupt. © 2019 Microchip Technology Inc.
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SAM E70/S70/V70/V71 Family SDRAM Controller (SDRAMC) 34.7.6 SDRAMC Interrupt Disable Register Name: Offset: Property: Bit SDRAMC_IDR 0x18 Write-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RES W Access Reset Bit Access Reset Bit Access Reset Bit Access Reset Bit 0 – RES Value 0 1 Refresh Error Interrupt Disable Description No effect. Disables the refresh error interrupt. © 2019 Microchip Technology Inc.
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SAM E70/S70/V70/V71 Family SDRAM Controller (SDRAMC) 34.7.7 SDRAMC Interrupt Mask Register Name: Offset: Reset: Property: Bit SDRAMC_IMR 0x1C 0x00000000 Read-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RES R 0 Access Reset Bit Access Reset Bit Access Reset Bit Access Reset Bit 0 – RES Value 0 1 Refresh Error Interrupt Mask Description The refresh error interrupt is disabled. The refresh error interrupt is enabled.
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SAM E70/S70/V70/V71 Family SDRAM Controller (SDRAMC) 34.7.8 SDRAMC Interrupt Status Register Name: Offset: Reset: Property: Bit SDRAMC_ISR 0x20 0x00000000 Read-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RES R 0 Access Reset Bit Access Reset Bit Access Reset Bit Access Reset Bit 0 – RES Value 0 1 Refresh Error Status (cleared on read) Description No refresh error has been detected since the register was last read.
PAGE 409
SAM E70/S70/V70/V71 Family SDRAM Controller (SDRAMC) 34.7.9 SDRAMC Memory Device Register Name: Offset: Reset: Property: Bit SDRAMC_MDR 0x24 0x00000000 Read/Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Access Reset Bit Access Reset Bit Access Reset Bit 0 MD[1:0] Access Reset R/W 0 Bits 1:0 – MD[1:0] Memory Device Type Value Name 0 SDRAM 1 LPSDRAM 2 – 3 – © 2019 Microchip Technology Inc.
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SAM E70/S70/V70/V71 Family SDRAM Controller (SDRAMC) 34.7.10 SDRAMC Configuration Register 1 Name: Offset: Reset: Property: Bit SDRAMC_CFR1 0x28 0x00000002 Read/Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 UNAL R/W 0 7 6 5 4 3 2 1 0 R/W 1 R/W 0 Access Reset Bit Access Reset Bit Access Reset Bit TMRD[3:0] Access Reset R/W 0 R/W 0 Bit 8 – UNAL Support Unaligned Access This mode is enabled with masters which have an AXI interface.
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SAM E70/S70/V70/V71 Family SDRAM Controller (SDRAMC) 34.7.11 SDRAMC OCMS Register Name: Offset: Reset: Property: Bit SDRAMC_OCMS 0x2C 0x00000000 Read/Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SDR_SE R/W 0 Access Reset Bit Access Reset Bit Access Reset Bit Access Reset Bit 0 – SDR_SE SDRAM Memory Controller Scrambling Enable Value Description 0 Disables off-chip scrambling for SDR-SDRAM access.
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SAM E70/S70/V70/V71 Family SDRAM Controller (SDRAMC) 34.7.
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SAM E70/S70/V70/V71 Family SDRAM Controller (SDRAMC) 34.7.
PAGE 414
SAM E70/S70/V70/V71 Family Static Memory Controller (SMC) 35. Static Memory Controller (SMC) 35.1 Description The External Bus Interface (EBI) is designed to ensure the successful data transfer between several external devices and the ARM-based microcontroller. The Static Memory Controller (SMC) is part of the EBI. The SMC handles several types of external memory and peripheral devices, such as SRAM, PSRAM, PROM, EPROM, EEPROM, LCD Module, NOR Flash and NAND Flash.
PAGE 415
SAM E70/S70/V70/V71 Family Static Memory Controller (SMC) ...........continued 35.4 Name Description Type Active Level NWAIT External Wait Signal Input Low NANDCS NAND Flash Chip Select Line Output Low NANDOE NAND Flash Output Enable Output Low NANDWE NAND Flash Write Enable Output Low NANDALE NAND Flash Address Latch Enable Output – NANDCLE NAND Flash Command Latch Enable Output – Multiplexed Signals Table 35-2. Static Memory Controller (SMC) Multiplexed Signals 35.5 35.5.
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SAM E70/S70/V70/V71 Family Static Memory Controller (SMC) Figure 35-1. Memory Connections for Four External Devices NCS[0] - NCS[3] NRD SMC NWE A[23:0] D[15:0] NCS3 NCS2 NCS1 NCS0 Memory Enable Memory Enable Memory Enable Memory Enable Output Enable Write Enable 24 A[23:0] 16 or 8 35.7 Connection to External Devices 35.7.1 Data Bus Width D[15:0] or D[7:0] A data bus width of 8 or 16 bits can be selected for each chip select.
PAGE 417
SAM E70/S70/V70/V71 Family Static Memory Controller (SMC) 35.7.2 Byte Write or Byte Select Access Each chip select with a 16-bit data bus can operate with one of two different types of write access: byte write or byte select. This is controlled by the BAT field of the SMC_MODE register for the corresponding chip select. 35.7.2.1 Byte Write Access Byte write access is used to connect 2 × 8-bit devices as a 16-bit memory, and supports one write signal per byte of the data bus and a single read signal.
PAGE 418
SAM E70/S70/V70/V71 Family Static Memory Controller (SMC) Table 35-3. SMC Multiplexed Signal Translation Device Type Signal Name 16-bit Bus 35.7.3 8-bit Bus 1 x 16-bit 2 x 8-bit 1 x 8-bit Byte Access Type (BAT) Byte Select Byte Write – NBS0_A0 NBS0 – A0 NWE_NWR0 NWE NWR0 NWE NBS1_NWR1 NBS1 NWR1 – A1 A1 A1 A1 NAND Flash Support The SMC integrates circuitry that interfaces to NAND Flash devices. The NAND Flash logic is driven by the SMC.
PAGE 419
SAM E70/S70/V70/V71 Family Static Memory Controller (SMC) • This restriction has been removed for “CE don’t care” NAND Flash devices. The NCSx signal can be directly connected to the CE pin of the NAND Flash device. The following figure illustrates both topologies: Standard and “CE don’t care” NAND Flash. Figure 35-6.
PAGE 420
SAM E70/S70/V70/V71 Family Static Memory Controller (SMC) 35.8.1.1 8-bit NAND Flash Hardware Configuration Figure 35-7. 8-bit NAND Flash D[0..7] U1 CLE ALE NANDOE NANDWE (ANY PIO) (ANY PIO) R1 3V3 R2 10K 16 17 8 18 9 CLE ALE RE WE CE 7 R/B 19 WP 10K 1 2 3 4 5 6 10 11 14 15 20 21 22 23 24 25 26 K9F2G08U0M N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 29 30 31 32 41 42 43 44 N.C N.C N.C N.C N.C N.C PRE N.C N.C N.C N.C N.
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SAM E70/S70/V70/V71 Family Static Memory Controller (SMC) 35.8.1.2 NOR Flash Hardware Configuration Figure 35-8. NOR Flash D[0..7] A[0..
PAGE 422
SAM E70/S70/V70/V71 Family Static Memory Controller (SMC) Figure 35-9. Standard Read Cycle MCK A[23:0] NRD NCS D[7:0] NRD_SETUP NCS_RD_SETUP NRD_PULSE NRD_HOLD NCS_RD_PULSE NCS_RD_HOLD NRD_CYCLE 35.9.1.1 NRD Waveform The NRD signal is characterized by a setup timing, a pulse width and a hold timing.
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SAM E70/S70/V70/V71 Family Static Memory Controller (SMC) Figure 35-10. No Setup, No Hold on NRD and NCS Read Signals MCK A[23:0] NRD NCS D[7:0] NRD_PULSE NRD_PULSE NRD_PULSE NCS_RD_PULSE NCS_RD_PULSE NCS_RD_PULSE NRD_CYCLE NRD_CYCLE NRD_CYCLE 35.9.1.5 Null Pulse Programming a null pulse is not permitted. The pulse must be at least set to 1. A null value leads to unpredictable behavior. 35.9.
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SAM E70/S70/V70/V71 Family Static Memory Controller (SMC) Figure 35-11. SMC_MODE.READ_MODE = 1: Data is sampled by SMC before the rising edge of NRD MCK A[23:0] NRD NCS tPACC D[7:0] Data Sampling 35.9.2.2 Read is Controlled by NCS (SMC_MODE.READ_MODE = 0) The following figure shows the typical read cycle of an LCD module. The read data is valid tPACC after the falling edge of the NCS signal and remains valid until the rising edge of NCS. Data must be sampled when NCS is raised.
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SAM E70/S70/V70/V71 Family Static Memory Controller (SMC) 35.9.3.2 NCS Waveforms The NCS signal waveforms in write operation are not the same that those applied in read operations, but are separately defined: • • • ncs_wr_setup—the NCS setup time is defined as the setup time of address before the NCS falling edge. ncs_wr_pulse—the NCS pulse length is the time between NCS falling edge and NCS rising edge; ncs_wr_hold—the NCS hold time is defined as the hold time of address after the NCS rising edge.
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SAM E70/S70/V70/V71 Family Static Memory Controller (SMC) Figure 35-14. Null Setup and Hold Values of NCS and NWE in Write Cycle MCK A[23:0] NWE NCS D[7:0] NWE_PULSE NWE_PULSE NWE_PULSE NCS_WR_PULSE NCS_WR_PULSE NCS_WR_PULSE NWE_CYCLE NWE_CYCLE NWE_CYCLE 35.9.3.5 Null Pulse Programming null pulse is not permitted. Pulse must be at least set to 1. A null value leads to unpredictable behavior. 35.9.
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SAM E70/S70/V70/V71 Family Static Memory Controller (SMC) 35.9.4.2 Write is Controlled by NCS (SMC.MODE.WRITE_MODE = 0) The following figure shows the waveforms of a write operation with SMC_MODE.WRITE_MODE cleared. The data is put on the bus during the pulse and hold steps of the NCS signal. The internal data buffers are switched to Output mode after the NCS_WR_SETUP time, and until the end of the write cycle, regardless of the programmed waveform on NWE. Figure 35-16. WRITE_MODE = 0.
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SAM E70/S70/V70/V71 Family Static Memory Controller (SMC) • NWE_CYCLE The following table shows how the timing parameters are coded and their permitted range. Table 35-4.
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SAM E70/S70/V70/V71 Family Static Memory Controller (SMC) The scrambling/unscrambling function can be enabled or disabled by configuring the CSxSE bits in the SMC Off-Chip Memory Scrambling Register (SMC_OCMS). When multiple chip selects are handled, the scrambling function per chip select is configurable using the CSxSE bits in the SMC_OCMS register.
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SAM E70/S70/V70/V71 Family Static Memory Controller (SMC) • • • if the write controlling signal has no hold time and the read controlling signal has no setup time (Figure 35-18). in NCS Write controlled mode (SMC_MODE.WRITE_MODE = 0), if there is no hold timing on the NCS signal and the NCS_RD_SETUP parameter is set to 0, regardless of the Read mode (Figure 35-19). The write operation must end with a NCS rising edge. Without an Early Read Wait State, the write operation could not complete properly.
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SAM E70/S70/V70/V71 Family Static Memory Controller (SMC) Figure 35-20. Early Read Wait State: NWE-controlled write with no hold followed by a read with one setup cycle MCK A[25:2] internal write controlling signal external write controlling signal (NWE) no hold read setup = 1 NRD D[7:0] write cycle Early Read read cycle (WRITE_MODE = 1) wait state (READ_MODE = 0 or READ_MODE = 1) 35.11.
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SAM E70/S70/V70/V71 Family Static Memory Controller (SMC) 35.12 Data Float Wait States Some memory devices are slow to release the external bus. For such devices, it is necessary to add wait states (data float wait states) after a read access: • • before starting a read access to a different external memory before starting a write access to the same device or to a different external one. The data float output time (tDF) for each external memory device is programmed in the SMC_MODE.
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SAM E70/S70/V70/V71 Family Static Memory Controller (SMC) Figure 35-22. TDF Period in NCS Controlled Read Operation (TDF = 3) MCK A[23:0] NWE NCS D[7:0] 35.12.2 TDF Optimization Enabled (SMC_MODE.TDF_MODE = 1) When SMC_MODE.TDF_MODE is set to 1 (TDF optimization is enabled), the SMC takes advantage of the setup period of the next access to optimize the number of wait states cycle to insert.
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SAM E70/S70/V70/V71 Family Static Memory Controller (SMC) 35.12.3 TDF Optimization Disabled (SMC_MODE.TDF_MODE = 0) When optimization is disabled, TDF Wait states are inserted at the end of the read transfer, so that the data float period is ended when the second access begins. If the hold period of the read1 controlling signal overlaps the data float period, no additional TDF Wait states will be inserted.
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SAM E70/S70/V70/V71 Family Static Memory Controller (SMC) Figure 35-26. TDF Mode = 0: TDF wait states between read and write accesses on the same chip select MCK A[23:0] read1 controlling signal (NRD) write2 setup = 1 read1 hold = 1 write2 controlling signal (NWE) TDF_CYCLES = 5 D[7:0] 4 TDF WAIT STATES read1 cycle TDF_CYCLES = 5 35.
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SAM E70/S70/V70/V71 Family Static Memory Controller (SMC) Figure 35-27. Write Access with NWAIT Assertion in Frozen Mode (SMC_MODE.EXNW_MODE = 10) MCK A[23:0] FROZEN STATE 4 3 2 1 1 1 1 0 3 2 2 2 2 1 NWE 6 5 4 0 NCS D[7:0] NWAIT internally synchronized NWAIT signal Write cycle EXNW_MODE = 10 (Frozen) WRITE_MODE = 1 (NWE_controlled) NWE_PULSE = 5 NCS_WR_PULSE = 7 Figure 35-28. Read Access with NWAIT Assertion in Frozen Mode (SMC_MODE.
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SAM E70/S70/V70/V71 Family Static Memory Controller (SMC) If asserted, the SMC suspends the access as shown in Figure 35-29 and Figure 35-30. After deassertion, the access is completed: the hold step of the access is performed. This mode must be selected when the external device uses deassertion of the NWAIT signal to indicate its ability to complete the read or write operation.
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SAM E70/S70/V70/V71 Family Static Memory Controller (SMC) Figure 35-30. NWAIT Assertion in Read Access: Ready Mode (SMC_MODE.EXNW_MODE = 11) MCK A[23:0] Wait STATE 6 5 4 3 2 1 0 0 6 5 4 3 2 1 1 NCS NRD 0 NWAIT internally synchronized NWAIT signal Read cycle Assertion is ignored EXNW_MODE = 11(Ready mode) READ_MODE = 0 (NCS_controlled) Assertion is ignored NRD_PULSE = 7 NCS_RD_PULSE =7 35.13.
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SAM E70/S70/V70/V71 Family Static Memory Controller (SMC) Figure 35-31. NWAIT Latency MCK A[23:0] WAIT STATE 4 3 2 1 0 0 0 NRD minimal pulse length NWAIT intenally synchronized NWAIT signal NWAIT latency 2 cycle resynchronization Read cycle EXNW_MODE = 10 or 11 READ_MODE = 1 (NRD_controlled) NRD_PULSE = 5 35.
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SAM E70/S70/V70/V71 Family Static Memory Controller (SMC) Table 35-6. Read and Write Timing Parameters in Slow Clock Mode Read Parameters Duration (cycles) Write Parameters Duration (cycles) NRD_SETUP 1 NWE_SETUP 1 NRD_PULSE 1 NWE_PULSE 1 NCS_RD_SETUP 0 NCS_WR_SETUP 0 NCS_RD_PULSE 2 NCS_WR_PULSE 3 NRD_CYCLE 2 NWE_CYCLE 3 35.14.
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SAM E70/S70/V70/V71 Family Static Memory Controller (SMC) Figure 35-34. Recommended Procedure to Switch from Slow Clock Mode to Normal Mode or from Normal Mode to Slow Clock Mode Slow Clock Mode internal signal from PMC MCK A[23:0] NWE 1 1 1 3 2 2 NCS SLOW CLOCK MODE WRITE IDLE STATE NORMAL MODE WRITE Reload Conf guration Wait State 35.15 Asynchronous Page Mode The SMC supports asynchronous burst reads in Page mode, provided that the Page mode is enabled (SMC_MODE.PMEN =1).
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SAM E70/S70/V70/V71 Family Static Memory Controller (SMC) Figure 35-35. Page Mode Read Protocol (Address MSB and LSB are defined in Table 35-7) MCK A[MSB] A[LSB] NRD NCS tpa tsa tsa D[7:0] NRD_PULSE NCS_RD_PULSE NRD_PULSE The NRD and NCS signals are held low during all read transfers, whatever the programmed values of the setup and hold timings in the User Interface may be. Moreover, the NRD and NCS timings are identical.
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SAM E70/S70/V70/V71 Family Static Memory Controller (SMC) If the MSB of addresses are different, the SMC performs the access of a new page. In the same way, if the chip select is different from the previous access, a page break occurs. If two sequential accesses are made to the Page mode memory, but separated by an other internal or external peripheral access, a page break occurs on the second access because the chip select of the device was deasserted between both accesses. Figure 35-36.
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SAM E70/S70/V70/V71 Family Static Memory Controller (SMC) 35.16 Register Summary Offset Name 0x00 SMC_SETUP[0..3] 0x00 SMC_PULSE[0..3] Bit Pos. 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 NWE_SETUP[5:0] NCS_WR_SETUP[5:0] NRD_SETUP[5:0] NCS_RD_SETUP[5:0] NWE_PULSE[6:0] NCS_WR_PULSE[6:0] NRD_PULSE[6:0] NCS_RD_PULSE[6:0] NWE_CYCLE[7:0] NWE_CYCLE[ 8] 15:8 0x00 SMC_CYCLE[0..3] 23:16 NRD_CYCLE[7:0] NRD_CYCLE[ 24] 31:24 7:0 0x00 SMC_MODE[0..3] 0x04 ...
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SAM E70/S70/V70/V71 Family Static Memory Controller (SMC) 35.16.1.1 SMC Setup Register Name: Offset: Reset: Property: SMC_SETUP[0..3] 0x00 0 R/W This register can only be written if the WPEN bit is cleared in the “SMC Write Protection Mode Register” .
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SAM E70/S70/V70/V71 Family Static Memory Controller (SMC) 35.16.1.2 SMC Pulse Register Name: Offset: Reset: Property: SMC_PULSE[0..3] 0x00 0 R/W This register can only be written if the WPEN bit is cleared in the “SMC Write Protection Mode Register” .
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SAM E70/S70/V70/V71 Family Static Memory Controller (SMC) 35.16.1.3 SMC Cycle Register Name: Offset: Reset: Property: SMC_CYCLE[0..3] 0x00 0 R/W This register can only be written if the WPEN bit is cleared in the “SMC Write Protection Mode Register” .
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SAM E70/S70/V70/V71 Family Static Memory Controller (SMC) 35.16.1.4 SMC Mode Register Name: Offset: Reset: Property: SMC_MODE[0..3] 0x00 0 R/W This register can only be written if the WPEN bit is cleared in the “SMC Write Protection Mode Register” . The user must confirm the SMC configuration by writing any one of the SMC_MODE registers.
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SAM E70/S70/V70/V71 Family Static Memory Controller (SMC) Value 0 1 Name 8_BIT 16_BIT Description 8-bit Data Bus 16-bit Data Bus Bit 8 – BAT Byte Access Type This field is used only if DBW defines a 16-bit data bus. Value Name Description 0 BYTE_SELECT Byte select access type: - Write operation is controlled using NCS, NWE, NBS0, NBS1. 1 BYTE_WRITE - Read operation is controlled using NCS, NRD, NBS0, NBS1. Byte write access type: - Write operation is controlled using NCS, NWR0, NWR1.
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SAM E70/S70/V70/V71 Family Static Memory Controller (SMC) 35.16.1.5 SMC Off-Chip Memory Scrambling Register Name: Offset: Reset: Property: SMC_OCMS 0x80 0x00000000 Read/Write Note: This register can only be written if the WPEN bit is cleared in the SMC Write Protection Mode Register (35.16.1.8 SMC_WPMR).
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SAM E70/S70/V70/V71 Family Static Memory Controller (SMC) 35.16.1.6 SMC Off-Chip Memory Scrambling Key1 Register Name: Offset: Reset: Property: SMC_KEY1 0x84 0x00000000 Write-once Note: 1. ‘Write-once’ access indicates that the first write access after a system reset prevents any further modification of the value of this register.
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SAM E70/S70/V70/V71 Family Static Memory Controller (SMC) 35.16.1.7 SMC Off-Chip Memory Scrambling Key2 Register Name: Offset: Reset: Property: SMC_KEY2 0x88 0x00000000 Write-once Note: ‘Write-once’ access indicates that the first write access after a system reset prevents any further modification of the value of this register.
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SAM E70/S70/V70/V71 Family Static Memory Controller (SMC) 35.16.1.
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SAM E70/S70/V70/V71 Family Static Memory Controller (SMC) 35.16.1.
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SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) 36. DMA Controller (XDMAC) 36.1 Description The DMA Controller (XDMAC) is a AHB-protocol central direct memory access controller. It performs peripheral data transfer and memory move operations over one or two bus ports through the unidirectional communication channel. Each channel is fully programmable and provides both peripheral or memory-to-memory transfers. The channel features are configurable at implementation. 36.
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SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) 36.3 Block Diagram Figure 36-1. DMA Controller (XDMAC) Block Diagram Data FIFO DMA Read/Write Datapath DMA Channel Destination FSM Source FSM Request Arbiter Control and Data Steering Request Pool APB Interface Status Registers Configuration Registers Hardware Request Interface DMA Interrupt Dual Master AHB Interface AMBA AHB Layer 36.
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SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) ...........continued Peripheral Name Transfer Type HW Interface Number (XDMAC_CC.
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SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) ...........continued Peripheral Name Transfer Type HW Interface Number (XDMAC_CC.PERID) I2SC0 Receive Right 49 I2SC1 Transmit Right 50 I2SC1 Receive Right 51 36.5 Functional Description 36.5.1 Basic Definitions Source Peripheral: Slave device, memory mapped on the interconnection network, from where the XDMAC reads data. The source peripheral teams up with a destination peripheral to form a channel.
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SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) Figure 36-2. XDMAC Memory Transfer Hierarchy Master Transfer BLK0 μBLK0 MB0 MB(p-1) BLK1 μBLK(M-1) μBLK1 iMB BLK(N-1) Block Level Micro Block Level Memory Burst Level Figure 36-3. XDAMC Peripheral Transfer Hierarchy Master Transfer BLK0 μBLK0 CHK0 36.5.
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SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) 36.5.4 XDMAC Transfer Software Operation 36.5.4.1 Single Block Transfer With Single Microblock 1. 2. Read the XDMAC Global Channel Status Register (XDMAC_GS) to select a free channel. Clear the pending Interrupt Status bit(s) by reading the selected XDMAC Channel x Interrupt Status Register (XDMAC_CISx). 3. Write the XDMAC Channel x Source Address Register (XDMAC_CSAx) for channel x. 4.
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SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) This indicates that the linked list is disabled and striding is disabled. Enable the Block interrupt by writing a ‘1’ to XDMAC_CIEx.BIE, enable the Channel x Interrupt Enable bit by writing a ‘1’ to XDMAC_GIEx.IEx. 10. Enable channel x by writing a ‘1’ to the XDMAC_GE.ENx. XDMAC_GS.STx is set by hardware. 11. Once completed, the DMA channel sets XDMAC_CISx.BIS (End of Block Interrupt Status bit) and generates an interrupt. XDMAC_GS.
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SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) ...........
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SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) 36.6.2.
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SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) 36.7 XDMAC Maintenance Software Operations 36.7.1 Disabling a Channel A disable channel request occurs when a write operation is performed in the XDMAC_GD register. If the channel is source peripheral synchronized (bit XDMAC_CCx.TYPE is set and bit XDMAC_CCx.DSYNC is cleared), then pending bytes (bytes located in the FIFO) are written to memory and bit XDMAC_CISx.DIS is set.
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SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) • When XDMAC_CC.INITD is set to 0, XDMAC_CUBC.UBLEN and XDMAC_CNDA.NDA field values are unreliable when the descriptor is being updated. The following procedure applies to get the buffer descriptor identifier and the residual bytes: Read XDMAC_CNDAx.NDA(nda0) Read XDMAC_CCx.INITD(initd0) Read XDMAC_CCx.INITD(initd0) Read XDMAC_CUBCx.UBLEN(ublen) Read XDMAC_CCx.INITD(initd1) Read XDMA_CNDAx.NDA(nda1) If (nda0 == nda1 && initd0 == 1 && initd1 == 1).
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SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) 36.9 Register Summary Offset Name 0x00 XDMAC_GTYPE 0x04 XDMAC_GCFG 0x08 XDMAC_GWAC 0x0C XDMAC_GIE 0x10 XDMAC_GID 0x14 XDMAC_GIM 0x18 XDMAC_GIS 0x1C XDMAC_GE 0x20 XDMAC_GD 0x24 XDMAC_GS 0x28 XDMAC_GRS 0x2C XDMAC_GWS 0x30 XDMAC_GRWS 0x34 XDMAC_GRWR Bit Pos.
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SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) ...........continued Offset Name 0x38 XDMAC_GSWR 0x3C XDMAC_GSWS 0x40 XDMAC_GSWF 0x44 ... 0x4F Reserved 0x50 0x54 0x58 0x5C XDMAC_CIE0 XDMAC_CID0 XDMAC_CIM0 XDMAC_CIS0 0x60 XDMAC_CSA0 0x64 XDMAC_CDA0 0x68 0x6C 0x70 0x74 0x78 XDMAC_CNDA0 XDMAC_CNDC0 XDMAC_CUBC0 XDMAC_CBC0 XDMAC_CC0 Bit Pos.
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SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) ...........continued Offset Name 0x7C XDMAC_CDS_MSP 0 0x80 XDMAC_CSUS0 0x84 XDMAC_CDUS0 0x88 ... 0x8F Reserved 0x90 0x94 0x98 0x9C XDMAC_CIE1 XDMAC_CID1 XDMAC_CIM1 XDMAC_CIS1 0xA0 XDMAC_CSA1 0xA4 XDMAC_CDA1 0xA8 0xAC 0xB0 0xB4 0xB8 XDMAC_CNDA1 XDMAC_CNDC1 XDMAC_CUBC1 XDMAC_CBC1 XDMAC_CC1 Bit Pos.
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SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) ...........continued Offset Name 0xBC XDMAC_CDS_MSP 1 0xC0 XDMAC_CSUS1 0xC4 XDMAC_CDUS1 0xC8 ... 0xCF Reserved 0xD0 0xD4 0xD8 0xDC XDMAC_CIE2 XDMAC_CID2 XDMAC_CIM2 XDMAC_CIS2 0xE0 XDMAC_CSA2 0xE4 XDMAC_CDA2 0xE8 0xEC 0xF0 0xF4 0xF8 XDMAC_CNDA2 XDMAC_CNDC2 XDMAC_CUBC2 XDMAC_CBC2 XDMAC_CC2 Bit Pos.
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SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) ...........continued Offset Name 0xFC XDMAC_CDS_MSP 2 0x0100 XDMAC_CSUS2 0x0104 XDMAC_CDUS2 0x0108 ... 0x010F Reserved 0x0110 0x0114 0x0118 0x011C XDMAC_CIE3 XDMAC_CID3 XDMAC_CIM3 XDMAC_CIS3 0x0120 XDMAC_CSA3 0x0124 XDMAC_CDA3 0x0128 0x012C 0x0130 0x0134 0x0138 XDMAC_CNDA3 XDMAC_CNDC3 XDMAC_CUBC3 XDMAC_CBC3 XDMAC_CC3 Bit Pos.
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SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) ...........continued Offset Name 0x013C XDMAC_CDS_MSP 3 0x0140 XDMAC_CSUS3 0x0144 XDMAC_CDUS3 0x0148 ... 0x014F Reserved 0x0150 0x0154 0x0158 0x015C XDMAC_CIE4 XDMAC_CID4 XDMAC_CIM4 XDMAC_CIS4 0x0160 XDMAC_CSA4 0x0164 XDMAC_CDA4 0x0168 0x016C 0x0170 0x0174 0x0178 XDMAC_CNDA4 XDMAC_CNDC4 XDMAC_CUBC4 XDMAC_CBC4 XDMAC_CC4 Bit Pos.
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SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) ...........continued Offset Name 0x017C XDMAC_CDS_MSP 4 0x0180 XDMAC_CSUS4 0x0184 XDMAC_CDUS4 0x0188 ... 0x018F Reserved 0x0190 0x0194 0x0198 0x019C XDMAC_CIE5 XDMAC_CID5 XDMAC_CIM5 XDMAC_CIS5 0x01A0 XDMAC_CSA5 0x01A4 XDMAC_CDA5 0x01A8 0x01AC 0x01B0 0x01B4 0x01B8 XDMAC_CNDA5 XDMAC_CNDC5 XDMAC_CUBC5 XDMAC_CBC5 XDMAC_CC5 Bit Pos.
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SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) ...........continued Offset Name 0x01BC XDMAC_CDS_MSP 5 0x01C0 XDMAC_CSUS5 0x01C4 XDMAC_CDUS5 0x01C8 ... 0x01CF Reserved 0x01D0 0x01D4 0x01D8 0x01DC XDMAC_CIE6 XDMAC_CID6 XDMAC_CIM6 XDMAC_CIS6 0x01E0 XDMAC_CSA6 0x01E4 XDMAC_CDA6 0x01E8 0x01EC 0x01F0 0x01F4 0x01F8 XDMAC_CNDA6 XDMAC_CNDC6 XDMAC_CUBC6 XDMAC_CBC6 XDMAC_CC6 Bit Pos.
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SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) ...........continued Offset Name 0x01FC XDMAC_CDS_MSP 6 0x0200 XDMAC_CSUS6 0x0204 XDMAC_CDUS6 0x0208 ... 0x020F Reserved 0x0210 0x0214 0x0218 0x021C XDMAC_CIE7 XDMAC_CID7 XDMAC_CIM7 XDMAC_CIS7 0x0220 XDMAC_CSA7 0x0224 XDMAC_CDA7 0x0228 0x022C 0x0230 0x0234 0x0238 XDMAC_CNDA7 XDMAC_CNDC7 XDMAC_CUBC7 XDMAC_CBC7 XDMAC_CC7 Bit Pos.
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SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) ...........continued Offset Name 0x023C XDMAC_CDS_MSP 7 0x0240 XDMAC_CSUS7 0x0244 XDMAC_CDUS7 0x0248 ... 0x024F Reserved 0x0250 0x0254 0x0258 0x025C XDMAC_CIE8 XDMAC_CID8 XDMAC_CIM8 XDMAC_CIS8 0x0260 XDMAC_CSA8 0x0264 XDMAC_CDA8 0x0268 0x026C 0x0270 0x0274 0x0278 XDMAC_CNDA8 XDMAC_CNDC8 XDMAC_CUBC8 XDMAC_CBC8 XDMAC_CC8 Bit Pos.
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SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) ...........continued Offset Name 0x027C XDMAC_CDS_MSP 8 0x0280 XDMAC_CSUS8 0x0284 XDMAC_CDUS8 0x0288 ... 0x028F Reserved 0x0290 0x0294 0x0298 0x029C XDMAC_CIE9 XDMAC_CID9 XDMAC_CIM9 XDMAC_CIS9 0x02A0 XDMAC_CSA9 0x02A4 XDMAC_CDA9 0x02A8 0x02AC 0x02B0 0x02B4 0x02B8 XDMAC_CNDA9 XDMAC_CNDC9 XDMAC_CUBC9 XDMAC_CBC9 XDMAC_CC9 Bit Pos.
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SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) ...........continued Offset Name 0x02BC XDMAC_CDS_MSP 9 0x02C0 XDMAC_CSUS9 0x02C4 XDMAC_CDUS9 0x02C8 ... 0x02CF Reserved 0x02D0 0x02D4 0x02D8 0x02DC XDMAC_CIE10 XDMAC_CID10 XDMAC_CIM10 XDMAC_CIS10 0x02E0 XDMAC_CSA10 0x02E4 XDMAC_CDA10 0x02E8 0x02EC 0x02F0 0x02F4 0x02F8 XDMAC_CNDA10 XDMAC_CNDC10 XDMAC_CUBC10 XDMAC_CBC10 XDMAC_CC10 Bit Pos.
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SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) ...........continued Offset Name 0x02FC XDMAC_CDS_MSP 10 0x0300 XDMAC_CSUS10 0x0304 XDMAC_CDUS10 0x0308 ... 0x030F Reserved 0x0310 0x0314 0x0318 0x031C XDMAC_CIE11 XDMAC_CID11 XDMAC_CIM11 XDMAC_CIS11 0x0320 XDMAC_CSA11 0x0324 XDMAC_CDA11 0x0328 0x032C 0x0330 0x0334 0x0338 XDMAC_CNDA11 XDMAC_CNDC11 XDMAC_CUBC11 XDMAC_CBC11 XDMAC_CC11 Bit Pos.
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SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) ...........continued Offset Name 0x033C XDMAC_CDS_MSP 11 0x0340 XDMAC_CSUS11 0x0344 XDMAC_CDUS11 0x0348 ... 0x034F Reserved 0x0350 0x0354 0x0358 0x035C XDMAC_CIE12 XDMAC_CID12 XDMAC_CIM12 XDMAC_CIS12 0x0360 XDMAC_CSA12 0x0364 XDMAC_CDA12 0x0368 0x036C 0x0370 0x0374 0x0378 XDMAC_CNDA12 XDMAC_CNDC12 XDMAC_CUBC12 XDMAC_CBC12 XDMAC_CC12 Bit Pos.
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SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) ...........continued Offset Name 0x037C XDMAC_CDS_MSP 12 0x0380 XDMAC_CSUS12 0x0384 XDMAC_CDUS12 0x0388 ... 0x038F Reserved 0x0390 0x0394 0x0398 0x039C XDMAC_CIE13 XDMAC_CID13 XDMAC_CIM13 XDMAC_CIS13 0x03A0 XDMAC_CSA13 0x03A4 XDMAC_CDA13 0x03A8 0x03AC 0x03B0 0x03B4 0x03B8 XDMAC_CNDA13 XDMAC_CNDC13 XDMAC_CUBC13 XDMAC_CBC13 XDMAC_CC13 Bit Pos.
PAGE 481
SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) ...........continued Offset Name 0x03BC XDMAC_CDS_MSP 13 0x03C0 XDMAC_CSUS13 0x03C4 XDMAC_CDUS13 0x03C8 ... 0x03CF Reserved 0x03D0 0x03D4 0x03D8 0x03DC XDMAC_CIE14 XDMAC_CID14 XDMAC_CIM14 XDMAC_CIS14 0x03E0 XDMAC_CSA14 0x03E4 XDMAC_CDA14 0x03E8 0x03EC 0x03F0 0x03F4 0x03F8 XDMAC_CNDA14 XDMAC_CNDC14 XDMAC_CUBC14 XDMAC_CBC14 XDMAC_CC14 Bit Pos.
PAGE 482
SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) ...........continued Offset Name 0x03FC XDMAC_CDS_MSP 14 0x0400 XDMAC_CSUS14 0x0404 XDMAC_CDUS14 0x0408 ... 0x040F Reserved 0x0410 0x0414 0x0418 0x041C XDMAC_CIE15 XDMAC_CID15 XDMAC_CIM15 XDMAC_CIS15 0x0420 XDMAC_CSA15 0x0424 XDMAC_CDA15 0x0428 0x042C 0x0430 0x0434 0x0438 XDMAC_CNDA15 XDMAC_CNDC15 XDMAC_CUBC15 XDMAC_CBC15 XDMAC_CC15 Bit Pos.
PAGE 483
SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) ...........continued Offset Name 0x043C XDMAC_CDS_MSP 15 0x0440 XDMAC_CSUS15 0x0444 XDMAC_CDUS15 0x0448 ... 0x044F Reserved 0x0450 0x0454 0x0458 0x045C XDMAC_CIE16 XDMAC_CID16 XDMAC_CIM16 XDMAC_CIS16 0x0460 XDMAC_CSA16 0x0464 XDMAC_CDA16 0x0468 0x046C 0x0470 0x0474 0x0478 XDMAC_CNDA16 XDMAC_CNDC16 XDMAC_CUBC16 XDMAC_CBC16 XDMAC_CC16 Bit Pos.
PAGE 484
SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) ...........continued Offset Name 0x047C XDMAC_CDS_MSP 16 0x0480 XDMAC_CSUS16 0x0484 XDMAC_CDUS16 0x0488 ... 0x048F Reserved 0x0490 0x0494 0x0498 0x049C XDMAC_CIE17 XDMAC_CID17 XDMAC_CIM17 XDMAC_CIS17 0x04A0 XDMAC_CSA17 0x04A4 XDMAC_CDA17 0x04A8 0x04AC 0x04B0 0x04B4 0x04B8 XDMAC_CNDA17 XDMAC_CNDC17 XDMAC_CUBC17 XDMAC_CBC17 XDMAC_CC17 Bit Pos.
PAGE 485
SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) ...........continued Offset Name 0x04BC XDMAC_CDS_MSP 17 0x04C0 XDMAC_CSUS17 0x04C4 XDMAC_CDUS17 0x04C8 ... 0x04CF Reserved 0x04D0 0x04D4 0x04D8 0x04DC XDMAC_CIE18 XDMAC_CID18 XDMAC_CIM18 XDMAC_CIS18 0x04E0 XDMAC_CSA18 0x04E4 XDMAC_CDA18 0x04E8 0x04EC 0x04F0 0x04F4 0x04F8 XDMAC_CNDA18 XDMAC_CNDC18 XDMAC_CUBC18 XDMAC_CBC18 XDMAC_CC18 Bit Pos.
PAGE 486
SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) ...........continued Offset Name 0x04FC XDMAC_CDS_MSP 18 0x0500 XDMAC_CSUS18 0x0504 XDMAC_CDUS18 0x0508 ... 0x050F Reserved 0x0510 0x0514 0x0518 0x051C XDMAC_CIE19 XDMAC_CID19 XDMAC_CIM19 XDMAC_CIS19 0x0520 XDMAC_CSA19 0x0524 XDMAC_CDA19 0x0528 0x052C 0x0530 0x0534 0x0538 XDMAC_CNDA19 XDMAC_CNDC19 XDMAC_CUBC19 XDMAC_CBC19 XDMAC_CC19 Bit Pos.
PAGE 487
SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) ...........continued Offset Name 0x053C XDMAC_CDS_MSP 19 0x0540 XDMAC_CSUS19 0x0544 XDMAC_CDUS19 0x0548 ... 0x054F Reserved 0x0550 0x0554 0x0558 0x055C XDMAC_CIE20 XDMAC_CID20 XDMAC_CIM20 XDMAC_CIS20 0x0560 XDMAC_CSA20 0x0564 XDMAC_CDA20 0x0568 0x056C 0x0570 0x0574 0x0578 XDMAC_CNDA20 XDMAC_CNDC20 XDMAC_CUBC20 XDMAC_CBC20 XDMAC_CC20 Bit Pos.
PAGE 488
SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) ...........continued Offset Name 0x057C XDMAC_CDS_MSP 20 0x0580 XDMAC_CSUS20 0x0584 XDMAC_CDUS20 0x0588 ... 0x058F Reserved 0x0590 0x0594 0x0598 0x059C XDMAC_CIE21 XDMAC_CID21 XDMAC_CIM21 XDMAC_CIS21 0x05A0 XDMAC_CSA21 0x05A4 XDMAC_CDA21 0x05A8 0x05AC 0x05B0 0x05B4 0x05B8 XDMAC_CNDA21 XDMAC_CNDC21 XDMAC_CUBC21 XDMAC_CBC21 XDMAC_CC21 Bit Pos.
PAGE 489
SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) ...........continued Offset Name 0x05BC XDMAC_CDS_MSP 21 0x05C0 XDMAC_CSUS21 0x05C4 XDMAC_CDUS21 0x05C8 ... 0x05CF Reserved 0x05D0 0x05D4 0x05D8 0x05DC XDMAC_CIE22 XDMAC_CID22 XDMAC_CIM22 XDMAC_CIS22 0x05E0 XDMAC_CSA22 0x05E4 XDMAC_CDA22 0x05E8 0x05EC 0x05F0 0x05F4 0x05F8 XDMAC_CNDA22 XDMAC_CNDC22 XDMAC_CUBC22 XDMAC_CBC22 XDMAC_CC22 Bit Pos.
PAGE 490
SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) ...........continued Offset Name 0x05FC XDMAC_CDS_MSP 22 0x0600 XDMAC_CSUS22 0x0604 XDMAC_CDUS22 0x0608 ... 0x060F Reserved 0x0610 0x0614 0x0618 0x061C XDMAC_CIE23 XDMAC_CID23 XDMAC_CIM23 XDMAC_CIS23 0x0620 XDMAC_CSA23 0x0624 XDMAC_CDA23 0x0628 0x062C 0x0630 0x0634 0x0638 XDMAC_CNDA23 XDMAC_CNDC23 XDMAC_CUBC23 XDMAC_CBC23 XDMAC_CC23 Bit Pos.
PAGE 491
SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) ...........continued Offset Name 0x063C XDMAC_CDS_MSP 23 0x0640 XDMAC_CSUS23 0x0644 XDMAC_CDUS23 Bit Pos. 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 © 2019 Microchip Technology Inc.
PAGE 492
SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) 36.9.
PAGE 493
SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) 36.9.
PAGE 494
SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) 36.9.
PAGE 495
SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) 36.9.
PAGE 496
SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) 36.9.
PAGE 497
SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) 36.9.
PAGE 498
SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) 36.9.
PAGE 499
SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) 36.9.
PAGE 500
SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) 36.9.
PAGE 501
SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) 36.9.
PAGE 502
SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) 36.9.
PAGE 503
SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) 36.9.
PAGE 504
SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) 36.9.
PAGE 505
SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) 36.9.
PAGE 506
SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) 36.9.
PAGE 507
SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) 36.9.
PAGE 508
SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) 36.9.
PAGE 509
SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) 36.9.18 XDMAC Channel x Interrupt Enable Register [x=0..23] Name: Offset: Reset: Property: Bit XDMAC_CIE 0x50 + n*0x40 [n=0..
PAGE 510
SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) Bit 0 – BIE Value 0 1 End of Block Interrupt Enable Bit Description No effect. Enables end of block interrupt. © 2019 Microchip Technology Inc.
PAGE 511
SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) 36.9.19 XDMAC Channel x Interrupt Disable Register [x = 0..23] Name: Offset: Reset: Property: Bit XDMAC_CID 0x54 + n*0x40 [n=0..
PAGE 512
SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) Bit 0 – BID Value 0 1 End of Block Interrupt Disable Bit Description No effect. Disables end of block interrupt. © 2019 Microchip Technology Inc.
PAGE 513
SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) 36.9.20 XDMAC Channel x Interrupt Mask Register [x = 0..23] Name: Offset: Reset: Property: Bit XDMAC_CIM 0x58 + n*0x40 [n=0..
PAGE 514
SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) Bit 0 – BIM Value 0 1 End of Block Interrupt Mask Bit Description Block interrupt is masked. Block interrupt is activated. © 2019 Microchip Technology Inc.
PAGE 515
SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) 36.9.21 XDMAC Channel x Interrupt Status Register [x = 0..23] Name: Offset: Reset: Property: Bit XDMAC_CIS 0x5C + n*0x40 [n=0..
PAGE 516
SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) Value 1 Bit 0 – BIS Value 0 1 Description End of linked list condition has occurred since the last read of the Status register. End of Block Interrupt Status Bit Description End of block interrupt has not occurred. End of block interrupt has occurred since the last read of the Status register. © 2019 Microchip Technology Inc.
PAGE 517
SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) 36.9.22 XDMAC Channel x Source Address Register [x = 0..23] Name: Offset: Reset: Property: Bit 31 XDMAC_CSA 0x60 + n*0x40 [n=0..
PAGE 518
SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) 36.9.23 XDMAC Channel x Destination Address Register [x = 0..23] Name: Offset: Reset: Property: Bit 31 XDMAC_CDA 0x64 + n*0x40 [n=0..
PAGE 519
SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) 36.9.24 XDMAC Channel x Next Descriptor Address Register [x = 0..23] Name: Offset: Reset: Property: Bit 31 XDMAC_CNDA 0x68 + n*0x40 [n=0..
PAGE 520
SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) 36.9.25 XDMAC Channel x Next Descriptor Control Register [x = 0..23] Name: Offset: Reset: Property: Bit XDMAC_CNDC 0x6C + n*0x40 [n=0..
PAGE 521
SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) 36.9.26 XDMAC Channel x Microblock Control Register [x = 0..23] Name: Offset: Reset: Property: Bit XDMAC_CUBC 0x70 + n*0x40 [n=0..
PAGE 522
SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) 36.9.27 XDMAC Channel x Block Control Register [x = 0..23] Name: Offset: Reset: Property: Bit XDMAC_CBC 0x74 + n*0x40 [n=0..
PAGE 523
SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) 36.9.28 XDMAC Channel x Configuration Register [x = 0..23] Name: Offset: Reset: Property: Bit 31 30 29 28 R/W 0 R/W 0 23 WRIP R/W 0 22 RDIP R/W 0 15 Access Reset Bit Access Reset Bit Access Reset Bit Access Reset XDMAC_CC 0x78 + n*0x40 [n=0..
PAGE 524
SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) Value 1 2 3 Name INCREMENTED_AM UBS_AM UBS_DS_AM Description The addressing mode is incremented (the increment size is set to the data size). The microblock stride is added at the microblock boundary. The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. Bit 14 – DIF Channel x Destination Interface Identifier 0 (AHB_IF0): The data is written through system bus interface 0.
PAGE 525
SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) 36.9.29 XDMAC Channel x Data Stride Memory Set Pattern Register [x = 0..23] Name: Offset: Reset: Property: Bit Access Reset Bit Access Reset Bit Access Reset Bit Access Reset XDMAC_CDS_MSP 0x7C + n*0x40 [n=0..
PAGE 526
SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) 36.9.30 XDMAC Channel x Source Microblock Stride Register [x = 0..23] Name: Offset: Reset: Property: Bit XDMAC_CSUS 0x80 + n*0x40 [n=0..
PAGE 527
SAM E70/S70/V70/V71 Family DMA Controller (XDMAC) 36.9.31 XDMAC Channel x Destination Microblock Stride Register [x = 0..23] Name: Offset: Reset: Property: Bit XDMAC_CDUS 0x84 + n*0x40 [n=0..
PAGE 528
SAM E70/S70/V70/V71 Family Image Sensor Interface (ISI) 37. 37.1 Image Sensor Interface (ISI) Description The Image Sensor Interface (ISI) connects a CMOS-type image sensor to the processor and provides image capture in various formats. The ISI performs data conversion, if necessary, before the storage in memory through DMA. The ISI supports color CMOS image sensor and grayscale image sensors with a reduced set of functionalities.
PAGE 529
SAM E70/S70/V70/V71 Family Image Sensor Interface (ISI) 37.2 Embedded Characteristics • • • • • • • • • • • • • 37.3 ITU-R BT. 601/656 8-bit Mode External Interface Support Supports up to 12-bit Grayscale CMOS Sensors Support for ITU-R BT.
PAGE 530
SAM E70/S70/V70/V71 Family Image Sensor Interface (ISI) 37.5 Functional Description The Image Sensor Interface (ISI) supports direct connection to the ITU-R BT. 601/656 8-bit mode compliant sensors and up to 12-bit grayscale sensors. It receives the image data stream from the image sensor on the 12-bit data bus. This module receives up to 12 bits for data, the horizontal and vertical synchronizations and the pixel clock.
PAGE 531
SAM E70/S70/V70/V71 Family Image Sensor Interface (ISI) There are two timing reference signals, one at the beginning of each video data block SAV (0xFF000080) and one at the end of each video data block EAV (0xFF00009D). Only data sent between EAV and SAV is captured. Horizontal blanking and vertical blanking are ignored. Use of the SAV and EAV synchronization eliminates the ISI_VSYNC and ISI_HSYNC signals from the interface, thereby reducing the pin count.
PAGE 532
SAM E70/S70/V70/V71 Family Image Sensor Interface (ISI) Table 37-5.
PAGE 533
SAM E70/S70/V70/V71 Family Image Sensor Interface (ISI) Example: Input 1280 × 1024 Output = 640 × 480 Hratio = 1280/640 = 2 Vratio = 1024/480 = 2.1333 The decimation factor is 2 so 32/16. Figure 37-5. Resize Examples 1280 32/16 decimation 640 1024 480 1280 56/16 decimation 352 1024 288 37.5.4.2 Color Space Conversion This module converts YCrCb or YUV pixels to RGB color space. Clipping is performed to ensure that the samples value do not exceed the allowable range.
PAGE 534
SAM E70/S70/V70/V71 Family Image Sensor Interface (ISI) 37.5.4.3 Memory Interface 37.5.4.3.1 RGB Mode The preview datapath contains a data formatter that converts 8:8:8 pixel to RGB 5:6:5 format compliant with the 16bit format of the LCD controller. In general, when converting from a color channel with more bits to one with fewer bits, the formatter module discards the lower-order bits.
PAGE 535
SAM E70/S70/V70/V71 Family Image Sensor Interface (ISI) Table 37-10. Grayscale Memory Mapping Configuration for 12-bit Data (ISI_CFG2.GS_MODE = 1: one pixel per word) 31 30 29 28 27 26 25 24 22 21 20 19 18 17 16 – – – – Pixel 0 [11:4] 23 Pixel 0 [3:0] 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – – 37.5.4.3.3 8-bit Grayscale Mode For 8-bit Grayscale mode, ISI_DATA[7:0] on the 12-bit data bus is the physical interface to the ISI.
PAGE 536
SAM E70/S70/V70/V71 Family Image Sensor Interface (ISI) operation. This mode of operation improves flexibility of image buffer location and allows the user to allocate two or more frame buffers. The destination frame buffers are defined by a series of Frame Buffer Descriptors (FBD). Each FBD controls the transfer of one entire frame and then optionally loads a further FBD to switch the DMA operation at another frame buffer address. The FBD is defined by a series of three words.
PAGE 537
SAM E70/S70/V70/V71 Family Image Sensor Interface (ISI) Figure 37-6. Three Frame Buffers Application and Memory Mapping Codec Done Codec Request frame n-1 frame n frame n+1 frame n+2 frame n+3 frame n+4 Memory Space Frame Buffer 3 Frame Buffer 0 LCD Frame Buffer 1 ISI config space 4:2:2 Image Full ROI 37.5.5 Codec Path 37.5.5.1 Color Space Conversion Depending on user selection, this module can be bypassed so that input YCrCb stream is directly connected to the format converter module.
PAGE 538
SAM E70/S70/V70/V71 Family Image Sensor Interface (ISI) � = 0.257 ⋅ � + 0.504 ⋅ � + 0.098 ⋅ � + 16 �� = 0.439 ⋅ � − 0.368 ⋅ � − 0.071 ⋅ � + 128 �� = − 0.148 ⋅ � − 0.291 ⋅ � + 0.439 ⋅ � + 128 37.5.5.2 Memory Interface Dedicated FIFOs are used to support packed memory mapping. YCrCb pixel components are sent in a single 32-bit word in a contiguous space (packed). Data is stored in the order of natural scan lines. Planar mode is not supported. 37.5.5.
PAGE 539
SAM E70/S70/V70/V71 Family Image Sensor Interface (ISI) 37.6 Register Summary Note: Several parts of the ISI controller use the pixel clock provided by the image sensor (ISI_PCK). Thus the user must first program the image sensor to provide this clock (ISI_PCK) before programming the Image Sensor Controller.
PAGE 540
SAM E70/S70/V70/V71 Family Image Sensor Interface (ISI) ...........continued Offset Name 0x34 ISI_IMR 0x38 ISI_DMA_CHER 0x3C ISI_DMA_CHDR 0x40 ISI_DMA_CHSR 0x44 ISI_DMA_P_ADDR 0x48 ISI_DMA_P_CTRL 0x4C ISI_DMA_P_DSCR 0x50 ISI_DMA_C_ADDR 0x54 ISI_DMA_C_CTRL 0x58 ISI_DMA_C_DSCR 0x5C ... 0xE3 Reserved 0xE4 0xE8 ISI_WPMR ISI_WPSR Bit Pos.
PAGE 541
SAM E70/S70/V70/V71 Family Image Sensor Interface (ISI) 37.6.
PAGE 542
SAM E70/S70/V70/V71 Family Image Sensor Interface (ISI) Value 0 1 Description No CRC correction is performed on embedded synchronization. CRC correction is performed. If the correction is not possible, the current frame is discarded and the CRC_ERR bit is set in the ISI_SR. Bit 6 – EMB_SYNC Embedded Synchronization Value Description 0 Synchronization by HSYNC, VSYNC. 1 Synchronization by embedded synchronization sequence SAV/EAV.
PAGE 543
SAM E70/S70/V70/V71 Family Image Sensor Interface (ISI) 37.6.
PAGE 544
SAM E70/S70/V70/V71 Family Image Sensor Interface (ISI) Bits 29:28 – YCC_SWAP[1:0] YCrCb Format Swap Mode Defines the YCC image data. Value Name Description 0 DEFAULT Byte 0 Cb(i) Byte 1 Y(i) Byte 2 Cr(i) 1 MODE1 Byte 3 Y(i+1) Byte 0 Cr(i) Byte 1 Y(i) Byte 2 Cb(i) 2 MODE2 Byte 3 Y(i+1) Byte 0 Y(i) Byte 1 Cb(i) Byte 2 Y(i+1) 3 MODE3 Byte 3 Cr(i) Byte 0 Y(i) Byte 1 Cr(i) Byte 2 Y(i+1) Byte 3 Cb(i) Bits 26:16 – IM_HSIZE[10:0] Horizontal Size of the Image Sensor [0..
PAGE 545
SAM E70/S70/V70/V71 Family Image Sensor Interface (ISI) Bits 10:0 – IM_VSIZE[10:0] Vertical Size of the Image Sensor [0..2047] IM_VSIZE = Vertical size - 1 © 2019 Microchip Technology Inc.
PAGE 546
SAM E70/S70/V70/V71 Family Image Sensor Interface (ISI) 37.6.
PAGE 547
SAM E70/S70/V70/V71 Family Image Sensor Interface (ISI) 37.6.
PAGE 548
SAM E70/S70/V70/V71 Family Image Sensor Interface (ISI) 37.6.
PAGE 549
SAM E70/S70/V70/V71 Family Image Sensor Interface (ISI) 37.6.
PAGE 550
SAM E70/S70/V70/V71 Family Image Sensor Interface (ISI) 37.6.
PAGE 551
SAM E70/S70/V70/V71 Family Image Sensor Interface (ISI) 37.6.
PAGE 552
SAM E70/S70/V70/V71 Family Image Sensor Interface (ISI) 37.6.
PAGE 553
SAM E70/S70/V70/V71 Family Image Sensor Interface (ISI) 37.6.10 ISI Control Register Name: Offset: Reset: Property: Bit ISI_CR 0x24 – Write-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 ISI_CDC W – 7 6 5 4 3 2 ISI_SRST W – 1 ISI_DIS W – 0 ISI_EN W – Access Reset Bit Access Reset Bit Access Reset Bit Access Reset Bit 8 – ISI_CDC ISI Codec Request Write a one to this bit to enable the codec datapath and capture a full resolution frame.
PAGE 554
SAM E70/S70/V70/V71 Family Image Sensor Interface (ISI) 37.6.
PAGE 555
SAM E70/S70/V70/V71 Family Image Sensor Interface (ISI) Value 0 1 Description The clock domain synchronization process is terminated. This bit is set when the clock domain synchronization operation occurs. No modification of the channel status is allowed when this bit is set, to guarantee data integrity. Bit 17 – CXFR_DONE Codec DMA Transfer has Terminated (cleared on read) Value Description 0 Codec transfer done not detected. 1 Codec transfer done detected.
PAGE 556
SAM E70/S70/V70/V71 Family Image Sensor Interface (ISI) 37.6.
PAGE 557
SAM E70/S70/V70/V71 Family Image Sensor Interface (ISI) Value 1 Description Enables the corresponding interrupt. Bit 10 – VSYNC Vertical Synchronization Interrupt Enable Value Description 0 No effect. 1 Enables the corresponding interrupt. Bit 2 – SRST Software Reset Interrupt Enable Value Description 0 No effect. 1 Enables the corresponding interrupt. Bit 1 – DIS_DONE Disable Done Interrupt Enable Value Description 0 No effect. 1 Enables the corresponding interrupt. © 2019 Microchip Technology Inc.
PAGE 558
SAM E70/S70/V70/V71 Family Image Sensor Interface (ISI) 37.6.
PAGE 559
SAM E70/S70/V70/V71 Family Image Sensor Interface (ISI) Value 1 Description Disables the corresponding interrupt. Bit 10 – VSYNC Vertical Synchronization Interrupt Disable Value Description 0 No effect. 1 Disables the corresponding interrupt. Bit 2 – SRST Software Reset Interrupt Disable Value Description 0 No effect. 1 Disables the corresponding interrupt. Bit 1 – DIS_DONE Disable Done Interrupt Disable Value Description 0 No effect. 1 Disables the corresponding interrupt.
PAGE 560
SAM E70/S70/V70/V71 Family Image Sensor Interface (ISI) 37.6.
PAGE 561
SAM E70/S70/V70/V71 Family Image Sensor Interface (ISI) Value 1 Description The Preview DMA Transfer Completed interrupt is enabled. Bit 10 – VSYNC Vertical Synchronization Value Description 0 The Vertical Synchronization interrupt is disabled. 1 The Vertical Synchronization interrupt is enabled. Bit 2 – SRST Software Reset Completed Value Description 0 The Software Reset Completed interrupt is disabled. 1 The Software Reset Completed interrupt is enabled.
PAGE 562
SAM E70/S70/V70/V71 Family Image Sensor Interface (ISI) 37.6.15 DMA Channel Enable Register Name: Offset: Reset: Property: Bit ISI_DMA_CHER 0x38 – Write-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 C_CH_EN W – 0 P_CH_EN W – Access Reset Bit Access Reset Bit Access Reset Bit Access Reset Bit 1 – C_CH_EN Codec Channel Enable Write a one to this bit to enable the codec DMA channel.
PAGE 563
SAM E70/S70/V70/V71 Family Image Sensor Interface (ISI) 37.6.16 DMA Channel Disable Register Name: Offset: Reset: Property: Bit ISI_DMA_CHDR 0x3C – Write-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 C_CH_DIS W – 0 P_CH_DIS W – Access Reset Bit Access Reset Bit Access Reset Bit Access Reset Bit 1 – C_CH_DIS Codec Channel Disable Request Value Description 0 No effect. 1 Disables the channel.
PAGE 564
SAM E70/S70/V70/V71 Family Image Sensor Interface (ISI) 37.6.17 DMA Channel Status Register Name: Offset: Reset: Property: Bit ISI_DMA_CHSR 0x40 0x00000000 Read-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 C_CH_S R 0 0 P_CH_S R 0 Access Reset Bit Access Reset Bit Access Reset Bit Access Reset Bit 1 – C_CH_S Code DMA Channel Status Value Description 0 Indicates that the Codec DMA channel is disabled.
PAGE 565
SAM E70/S70/V70/V71 Family Image Sensor Interface (ISI) 37.6.
PAGE 566
SAM E70/S70/V70/V71 Family Image Sensor Interface (ISI) 37.6.19 DMA Preview Control Register Name: Offset: Reset: Property: Bit ISI_DMA_P_CTRL 0x48 0x00000000 Read/Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 P_DONE R/W 0 2 P_IEN R/W 0 1 P_WB R/W 0 0 P_FETCH R/W 0 Access Reset Bit Access Reset Bit Access Reset Bit Access Reset Bit 3 – P_DONE Preview Transfer Done This bit is only updated in the memory.
PAGE 567
SAM E70/S70/V70/V71 Family Image Sensor Interface (ISI) 37.6.
PAGE 568
SAM E70/S70/V70/V71 Family Image Sensor Interface (ISI) 37.6.
PAGE 569
SAM E70/S70/V70/V71 Family Image Sensor Interface (ISI) 37.6.22 DMA Codec Control Register Name: Offset: Reset: Property: Bit ISI_DMA_C_CTRL 0x54 0x00000000 Read/Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 C_DONE R/W 0 2 C_IEN R/W 0 1 C_WB R/W 0 0 C_FETCH R/W 0 Access Reset Bit Access Reset Bit Access Reset Bit Access Reset Bit 3 – C_DONE Codec Transfer Done This bit is only updated in the memory.
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SAM E70/S70/V70/V71 Family Image Sensor Interface (ISI) 37.6.
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SAM E70/S70/V70/V71 Family Image Sensor Interface (ISI) 37.6.
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SAM E70/S70/V70/V71 Family Image Sensor Interface (ISI) 37.6.
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SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38. GMAC - Ethernet MAC The description and registers of this peripheral are using the 'GMAC' designation although the device does not support Gigabit Ethernet functionality. 38.1 Description The Ethernet Media Access Controller (GMAC) module implements a 10/100 Mbps Ethernet MAC, compatible with the IEEE 802.3 standard. The GMAC can operate in either half or full duplex mode at all supported speeds. 38.
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SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.3 Block Diagram Figure 38-1. Block Diagram Status & Statistic Registers APB Register Interface MDIO Control Registers AHB AHB DMA Interface MAC Transmitter FIFO Interface Media Interface MAC Receiver Frame Filtering Packet Buffer Memories 38.
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SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC Note: 1. Input only. GTXCK must be provided with a 25 MHz / 50 MHz external crystal oscillator for MII / RMII interfaces, respectively. 38.5 Product Dependencies 38.5.1 I/O Lines The pins used for interfacing the GMAC may be multiplexed with PIO lines. The programmer must first program the PIO Controller to assign the pins to their peripheral function.
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SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC • The lowest 16 bits [15:0] of the timer count sub-nanoseconds. The 46 lower bits roll over when they have counted to 1s. The timer increments by a programmable period (to approximately 15.2fs resolution) with each MCK period and can also be adjusted in 1ns resolution (incremented or decremented) through APB register accesses. 38.6.
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SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC buffers are filled until the frame is complete and the final buffer descriptor status word contains the complete frame status. See the following table for details of the receive buffer descriptor list. Table 38-2. Receive Buffer Descriptor Entry Bit Function Word 0 31:2 Address of beginning of buffer 1 Wrap—marks last descriptor in receive buffer descriptor list. 0 Ownership—needs to be zero for the GMAC to write data to the receive buffer.
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SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC ...........continued Bit Function 23:22 This bit has a different meaning depending on whether RX checksum offloading is enabled. With RX checksum offloading disabled: (bit 24 clear in Network Configuration) Type ID register match. Encoded as follows: 00: Type ID register 1 match 01: Type ID register 2 match 10: Type ID register 3 match 11: Type ID register 4 match If more than one Type ID is matched only one is indicated with priority 4 down to 1.
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SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC Each receive AHB buffer start location is a word address. The start of the first AHB buffer in a frame can be offset by up to three Bytes, depending on the value written to bits 14 and 15 of the Network Configuration register (GMAC_NCFGR). If the start location of the AHB buffer is offset, the available length of the first AHB buffer is reduced by the corresponding number of Bytes.
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SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC In any packet buffer mode, writing a '1' to the Flush Next Package bit in the NCR register (GMAC_NCR.FNP) will force a packet from the external SRAM-based receive packet buffer to be flushed. This feature is only acted upon when the RX DMA is not currently writing packet data out to AHB, i.e., it is in an IDLE state. If the RX DMA is active, GMAC_NCR.FNP=1 is ignored. 38.6.3.
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SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC ...........continued Bit Function 22:20 Transmit IP/TCP/UDP checksum generation offload errors: 000: No Error. 001: The Packet was identified as a VLAN type, but the header was not fully complete, or had an error in it. 010: The Packet was identified as a SNAP type, but the header was not fully complete, or had an error in it. 011: The Packet was not of an IP type, or the IP packet was invalidly short, or the IP was not of type IPv4/ IPv6.
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SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC • • • A buffer descriptor with its ownership bit set is read. Bit 10, THALT, of the Network Control register is written. There is a transmit error such as too many retries or a transmit underrun. To set TXGO, write a '1' to GMAC_NCR.TSTART. Transmit halt does not take effect until any ongoing transmit finishes.
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SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC Figure 38-2. Data Paths with Packet Buffers Included TX GMII MAC Transmitter TX Packet Buffer DPSRAM TX Packet Buffer APB Register Interface TX DMA Status and Statistic Registers AHB AHB DMA RX DMA MDIO Control Interface RX Packet Buffer DPSRAM RX Packet Buffer RX GMII MAC Receiver Ethernet MAC Frame Filtering 38.6.3.
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SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC notification is received the frame is flushed from memory to make room for a new frame to be fetched from AHB system memory. In Partial Store and Forward mode, a trigger is sent across to the MAC transmitter as soon as sufficient packet data is available, which will then begin fetching the frame from the packet buffer memory.
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SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC ...........continued Queue Number Queue Size 2 512 bytes 1 512 bytes 0 (lowest priority) 2 KB In the transmit direction, higher priority queues are always serviced before lower priority queues, with Q0 as lowest priority and Q5 as highest priority. This strict priority scheme requires the user to ensure that high priority traffic is constrained so that lower priority traffic will have required bandwidth.
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SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC – An enable bit Compare C, COMPCE. This bit is associated with a Screening Type 2 Compare Word 0/1 register x, GMAC_ST2CW0/1. Each screener type has an enable bit, a match pattern and a queue number. If a received frame matches on an enabled screening register, then the frame will be tagged with the queue value in the associated screening register, and forwarded onto the DMA and subsequently into the external memory associated with that queue.
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SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC In half duplex mode, the transmitter checks carrier sense. If asserted, the transmitter waits for the signal to become inactive, and then starts transmission after the interframe gap of 96 bit times. If the collision signal is asserted during transmission, the transmitter will transmit a jam sequence of 32 bits taken from the data register and then retry transmission after the back off time has elapsed.
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SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC Each discarded frame is counted in the 10-bit length field error statistics register. Frames where the length field is greater than or equal to 0x0600 hex will not be checked. 38.6.
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SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC If the transmitter checksum engine is prevented from generating the relevant checksums, bits [22:20] of the transmitter DMA writeback status will be updated to identify the reason for the error. Note that the frame will still be transmitted but without the checksum substitution, as typically the reason that the substitution did not occur was that the protocol was not recognized. 38.6.
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SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC SA 00(see Note) SA (MSB) 00(see Note) Type ID (MSB) 43 Type ID (LSB) 21 Note: Contains the address of the transmitting device. The previous sequence shows the beginning of an Ethernet frame. Byte order of transmission is from top to bottom, as shown.
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SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.6.11 Disable Copy of Pause Frames Pause frames can be prevented from being written to memory by setting the disable copying of pause frames control bit 23 in the Network Configuration register. When set, pause frames are not copied to memory regardless of the Copy All Frames bit, whether a hash match is found, a type ID match is identified or if a destination address match is found. 38.6.12 VLAN Support The following table describes an Ethernet encoded 802.
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SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC • • The frame has an ARP operation field of 0x0001 (bytes 21 and 22) The least significant 16 bits of the frame's ARP target protocol address (bytes 41 and 42) match the value programmed in bits[15:0] of the Wake on LAN register The decoding of the ARP fields adjusts automatically if a VLAN tag is detected within the frame. The reserved value of 0x0000 for the Wake on LAN target address value will not cause an ARP request event, even if matched by the frame.
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SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 1588 version 2 introduces transparent clocks of which there are two kinds, peer-to-peer (P2P) and end-to-end (E2E). Transparent clocks measure the transit time of event messages through a bridge and amend a correction field within the message to allow for the transit time. P2P transparent clocks additionally correct for the delay in the receive path of the link using the information gathered from the peer delay frames.
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SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC ...........continued Frame Segment Value Source IP port (Octets 34–35) — Dest IP port (Octets 36–37) 013F Other stuff (Octets 38–42) — Version PTP (Octet 43) 01 Other stuff (Octets 44–73) — Control (Octet 74) 01 Other stuff (Octets 75–168) — For 1588 version 1 messages, sync and delay request frames are indicated by the GMAC if the frame type field indicates TCP/IP, UDP protocol is indicated, the destination IP address is 224.0.1.
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SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC ...........continued Frame Segment Value Type (Octets 12–13) 0800 IP stuff (Octets 14–22) — UDP (Octet 23) 11 IP stuff (Octets 24–29) — IP DA (Octets 30–33) E000006B Source IP port (Octets 34–35) — Dest IP port (Octets 36–37) 013F Other stuff (Octets 38–41) — Message type (Octet 42) 02 Version PTP (Octet 43) 02 Table 38-10.
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SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC ...........continued Frame Segment Value IP stuff (Octets 21–37) — IP DA (Octets 38–53) FF0200000000006B Source IP port (Octets 54–55) — Dest IP port (Octets 56–57) 013F Other stuff (Octets 58–61) — Message type (Octet 62) 03 Other stuff (Octets 63–93) — Version PTP (Octet 94) 02 For the multicast address 011B19000000 sync and delay request frames are recognized depending on the message type field, 00 for sync and 01 for delay request.
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SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC • • • The 48 upper bits [93:46] of the timer count seconds and are accessible in the GMAC 1588 Timer Seconds High Register” (GMAC_TSH) and GMAC 1588 Timer Seconds Low Register (GMAC_TSL). The 30 lower bits [45:16] of the timer count nanoseconds and are accessible in the GMAC 1588 Timer Nanoseconds Register (GMAC_TN). The lowest 16 bits [15:0] of the timer count sub-nanoseconds. The 46 lower bits roll over when they have counted to 1s.
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SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC The GMAC supports both hardware controlled pause of the transmitter, upon reception of a pause frame, and hardware generated pause frame transmission. 38.6.16.1 802.3 Pause Frame Reception Bit 13 of the Network Configuration register is the pause enable control for reception. If this bit is set, transmission will pause if a non zero pause quantum frame is received.
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SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.6.17 MAC PFC Priority-based Pause Frame Support Note: Refer to the 802.1Qbb standard for a full description of priority-based pause operation. The following table shows the start of a Priority-based Flow Control (PFC) pause frame. Table 38-15.
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SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC • • • • A priority enable vector taken from Transmit PFC Pause register 8 pause quantum registers Fill of 00 to take the frame to minimum frame length Valid FCS The pause quantum registers used in the generated frame will depend on the trigger source for the frame as follows: • • If bit 17 of the Network Control register is written with a one, then the priority enable vector of the priority-based pause frame will be set equal to the value stored in the Tran
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SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC IdleSlope is the rate of change of increasing credit when waiting to transmit and must be less than the value of the portTransmitRate. IdleSlope is the rate of change of credit when waiting to transmit and must be less than the value of the portTransmitRate. The max value of IdleSlope (or sendSlope) is (portTransmitRate / bits_per_MII_Clock). In case of 100 Mbps, maximum IdleSlope = (100 Mbps / 4) = 0x17D7840.
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SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.7 Programming Interface 38.7.1 Initialization 38.7.1.1 Configuration Initialization of the GMAC configuration (e.g., loop back mode, frequency ratios) must be done while the transmit and receive circuits are disabled. See the description of the Network Control register and Network Configuration register earlier in this document. To change loop back mode, the following sequence of operations must be followed: 1. 2. 3.
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SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 1. 2. 3. 4. 5. Allocate a number (N) of buffers of between 1 and 2047 bytes of data to be transmitted in system memory. Up to 128 buffers per frame are allowed. Allocate an area 8N bytes for the transmit buffer descriptor list in system memory and create N entries in this list. Mark all entries in this list as owned by GMAC, i.e., bit 31 of word 1 set to 0. Mark the last descriptor in the queue with the wrap bit (bit 30 in word 1 set to 1).
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SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 3. 4. 5. 6. 7. Set-up the transmit buffer list by writing buffer addresses to word zero of the transmit buffer descriptor entries and control and length to word one. Write data for transmission into the buffers pointed to by the descriptors. Write the address of the first buffer descriptor to transmit buffer descriptor queue pointer. Enable appropriate interrupts. Write to the transmit start bit (TSTART) in the Network Control register. 38.7.1.
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SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC Single Collision Frames Register Length Field Frame Errors Register Multiple Collision Frames Register Receive Symbol Errors Register Excessive Collisions Register Alignment Errors Register Late Collisions Register Receive Resource Errors Register Deferred Transmission Frames Register Receive Overrun Register Carrier Sense Errors Register IP Header Checksum Errors Register Octets Received Low Register TCP Checksum Errors Register Octets Received H
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SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8 Register Summary Offset Name 0x00 GMAC_NCR 0x04 GMAC_NCFGR 0x08 GMAC_NSR 0x0C GMAC_UR 0x10 GMAC_DCFGR 0x14 GMAC_TSR 0x18 GMAC_RBQB 0x1C GMAC_TBQB 0x20 GMAC_RSR 0x24 0x28 0x2C 0x30 0x34 GMAC_ISR GMAC_IER GMAC_IDR GMAC_IMR GMAC_MAN Bit Pos.
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SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC ...........continued Offset Name 0x38 GMAC_RPQ 0x3C GMAC_TPQ 0x40 GMAC_TPSF 0x44 GMAC_RPSF 0x48 GMAC_RJFML 0x4C ... 0x7F Reserved 0x80 GMAC_HRB 0x84 GMAC_HRT 0x88 GMAC_SAB1 0x8C GMAC_SAT1 0x90 GMAC_SAB2 0x94 GMAC_SAT2 0x98 GMAC_SAB3 0x9C GMAC_SAT3 0xA0 GMAC_SAB4 Bit Pos.
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SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC ...........continued Offset Name 0xA4 GMAC_SAT4 0xA8 0xAC 0xB0 0xB4 GMAC_TIDM1 GMAC_TIDM2 GMAC_TIDM3 GMAC_TIDM4 0xB8 GMAC_WOL 0xBC GMAC_IPGS 0xC0 0xC4 GMAC_SVLAN GMAC_TPFCP 0xC8 GMAC_SAMB1 0xCC GMAC_SAMT1 0xD0 ... 0xDB Reserved 0xDC GMAC_NSC 0xE0 GMAC_SCL 0xE4 GMAC_SCH Bit Pos.
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SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC ...........continued Offset Name 0xE8 GMAC_EFTSH 0xEC GMAC_EFRSH 0xF0 GMAC_PEFTSH 0xF4 GMAC_PEFRSH 0xF8 ... 0xFF Reserved 0x0100 GMAC_OTLO 0x0104 GMAC_OTHI 0x0108 GMAC_FT 0x010C GMAC_BCFT 0x0110 GMAC_MFT 0x0114 GMAC_PFT 0x0118 GMAC_BFT64 0x011C GMAC_TBFT127 0x0120 GMAC_TBFT255 0x0124 GMAC_TBFT511 Bit Pos.
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SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC ...........continued Offset Name 0x0128 GMAC_TBFT1023 0x012C GMAC_TBFT1518 0x0130 GMAC_GTBFT1518 0x0134 GMAC_TUR 0x0138 GMAC_SCF 0x013C GMAC_MCF 0x0140 GMAC_EC 0x0144 GMAC_LC 0x0148 GMAC_DTF 0x014C GMAC_CSE 0x0150 GMAC_ORLO 0x0154 GMAC_ORHI 0x0158 GMAC_FR 0x015C GMAC_BCFR Bit Pos.
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SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC ...........continued Offset Name 0x0160 GMAC_MFR 0x0164 GMAC_PFR 0x0168 GMAC_BFR64 0x016C GMAC_TBFR127 0x0170 GMAC_TBFR255 0x0174 GMAC_TBFR511 0x0178 GMAC_TBFR1023 0x017C GMAC_TBFR1518 0x0180 GMAC_TMXBFR 0x0184 GMAC_UFR 0x0188 GMAC_OFR 0x018C GMAC_JR 0x0190 GMAC_FCSE 0x0194 GMAC_LFFE Bit Pos.
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SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC ...........continued Offset Name 0x0198 GMAC_RSE 0x019C GMAC_AE 0x01A0 GMAC_RRE 0x01A4 GMAC_ROE 0x01A8 GMAC_IHCE 0x01AC GMAC_TCE 0x01B0 GMAC_UCE 0x01B4 ... 0x01BB Reserved 0x01BC GMAC_TISUBN 0x01C0 GMAC_TSH 0x01C4 ... 0x01CF Reserved 0x01D0 GMAC_TSL 0x01D4 GMAC_TN 0x01D8 0x01DC GMAC_TA GMAC_TI Bit Pos.
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SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC ...........continued Offset Name 0x01E0 GMAC_EFTSL 0x01E4 GMAC_EFTN 0x01E8 GMAC_EFRSL 0x01EC GMAC_EFRN 0x01F0 GMAC_PEFTSL 0x01F4 GMAC_PEFTN 0x01F8 GMAC_PEFRSL 0x01FC GMAC_PEFRN 0x0200 ...
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SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC ...........continued Offset Name 0x0404 GMAC_ISRPQ2 0x0408 GMAC_ISRPQ3 0x040C GMAC_ISRPQ4 0x0410 GMAC_ISRPQ5 0x0414 ... 0x043F Reserved 0x0440 0x0444 0x0448 0x044C GMAC_TBQBAPQ1 GMAC_TBQBAPQ2 GMAC_TBQBAPQ3 GMAC_TBQBAPQ4 0x0450 GMAC_TBQBAPQ5 0x0454 ... 0x047F Reserved 0x0480 GMAC_RBQBAPQ1 0x0484 GMAC_RBQBAPQ2 0x0488 GMAC_RBQBAPQ3 0x048C GMAC_RBQBAPQ4 Bit Pos.
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SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC ...........continued Offset Name Bit Pos. 0x0490 GMAC_RBQBAPQ5 7:0 15:8 23:16 31:24 0x0494 ... 0x049F Reserved 0x04A0 0x04A4 0x04A8 0x04AC GMAC_RBSRPQ1 GMAC_RBSRPQ2 GMAC_RBSRPQ3 GMAC_RBSRPQ4 0x04B0 GMAC_RBSRPQ5 0x04B4 ... 0x04BB Reserved 0x04BC GMAC_CBSCR 0x04C0 GMAC_CBSISQA 0x04C4 GMAC_CBSISQB 0x04C8 ...
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SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC ...........continued Offset Name Bit Pos. 0x050C GMAC_ST1RPQ3 7:0 15:8 23:16 31:24 0x0510 ... 0x053F 0x0540 0x0544 0x0548 0x054C 0x0550 0x0554 0x0558 0x055C 0x0560 ...
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SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC ...........continued Offset Name Bit Pos. GMAC_IERPQ5 7:0 15:8 23:16 31:24 TCOMP 0x0610 0x0614 ... 0x061F Reserved 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 TCOMP 0x0620 0x0624 0x0628 0x062C GMAC_IDRPQ1 GMAC_IDRPQ2 GMAC_IDRPQ3 GMAC_IDRPQ4 0x0630 GMAC_IDRPQ5 0x0634 ...
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SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC ...........continued Offset Name 0x06E4 GMAC_ST2ER1 0x06E8 GMAC_ST2ER2 0x06EC GMAC_ST2ER3 0x06F0 ... 0x06FF Reserved 0x0700 0x0704 0x0708 0x070C 0x0710 0x0714 0x0718 0x071C 0x0720 0x0724 0x0728 GMAC_ST2CW00 GMAC_ST2CW10 GMAC_ST2CW01 GMAC_ST2CW11 GMAC_ST2CW02 GMAC_ST2CW12 GMAC_ST2CW03 GMAC_ST2CW13 GMAC_ST2CW04 GMAC_ST2CW14 GMAC_ST2CW05 Bit Pos.
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SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC ...........continued Offset Name 0x072C GMAC_ST2CW15 0x0730 GMAC_ST2CW06 0x0734 GMAC_ST2CW16 0x0738 GMAC_ST2CW07 0x073C GMAC_ST2CW17 0x0740 GMAC_ST2CW08 0x0744 GMAC_ST2CW18 0x0748 GMAC_ST2CW09 0x074C GMAC_ST2CW19 0x0750 GMAC_ST2CW010 0x0754 GMAC_ST2CW110 0x0758 GMAC_ST2CW011 0x075C GMAC_ST2CW111 0x0760 GMAC_ST2CW012 Bit Pos.
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SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC ...........continued Offset Name 0x0764 GMAC_ST2CW112 0x0768 GMAC_ST2CW013 0x076C GMAC_ST2CW113 0x0770 GMAC_ST2CW014 0x0774 GMAC_ST2CW114 0x0778 GMAC_ST2CW015 0x077C GMAC_ST2CW115 0x0780 GMAC_ST2CW016 0x0784 GMAC_ST2CW116 0x0788 GMAC_ST2CW017 0x078C GMAC_ST2CW117 0x0790 GMAC_ST2CW018 0x0794 GMAC_ST2CW118 0x0798 GMAC_ST2CW019 Bit Pos.
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SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC ...........continued Offset Name 0x079C GMAC_ST2CW119 0x07A0 GMAC_ST2CW020 0x07A4 GMAC_ST2CW120 0x07A8 GMAC_ST2CW021 0x07AC GMAC_ST2CW121 0x07B0 GMAC_ST2CW022 0x07B4 GMAC_ST2CW122 0x07B8 GMAC_ST2CW023 0x07BC GMAC_ST2CW123 Bit Pos.
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SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
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SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC Bit 10 – THALT Transmit Halt Writing a '1' to this bit halts transmission as soon as any ongoing frame transmission ends. Writing a '0' to this bit has no effect. Bit 9 – TSTART Start Transmission Writing a '1' to this bit starts transmission. Writing a '0' to this bit has no effect. Bit 8 – BP Back Pressure In 10M or 100M half duplex mode, writing a '1' to this bit forces collisions on all received frames. Ignored in gigabit half duplex mode.
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SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC GRXCK and GTXCK may malfunction as the GMAC is switched into and out of internal loop back. It is important that receive and transmit circuits have already been disabled when making the switch into and out of internal loop back. Value Description 0 Loop back local is disabled. 1 Loop back local is enabled. © 2019 Microchip Technology Inc.
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SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
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SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC Bits 22:21 – DBW[1:0] Data Bus Width Should always be written to '0'. Value Name 0 DBW32 1 DBW64 Description 32-bit data bus width 64-bit data bus width Bits 20:18 – CLK[2:0] MDC Clock Division These bits must be set according to MCK speed, and determine the number MCK will be divided by to generate Management Data Clock (MDC). For conformance with the 802.3 specification, MDC must not exceed 2.5MHz.
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SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC Bit 4 – CAF Copy All Frames When writing a '1' to this bit, all valid frames will be accepted. Bit 3 – JFRAME Jumbo Frame Size Writing a '1' to this bit enables jumbo frames of up to 10240 bytes to be accepted. The default length is 10240 bytes. Bit 2 – DNVLAN Discard Non-VLAN Frames Writing a '1' to this bit allows only VLAN-tagged frames to pass to the address matching logic.
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SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.3 GMAC Network Status Register Name: Offset: Reset: Property: Bit GMAC_NSR 0x008 0x000001X0 Read-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 IDLE R 0 1 MDIO R 0 0 Access Reset Bit Access Reset Bit Access Reset Bit Access Reset Bit 2 – IDLE PHY Management Logic Idle The PHY management logic is idle (i.e., has completed).
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SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.4 GMAC User Register Name: Offset: Reset: Property: Bit GMAC_UR 0x00C 0x00000000 - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access Reset Bit Access Reset Bit Access Reset Bit Access Reset R/W 0 Bit 0 – Reduced MII Mode Value Description 0 RMII mode is selected 1 MII mode is selected © 2019 Microchip Technology Inc.
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SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
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SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC Bit 10 – TXPBMS Transmitter Packet Buffer Memory Size Select When written to zero, the amount of memory used for the transmit packet buffer is reduced by 50%. This reduces the amount of memory used by the GMAC. It is important to write this bit to '1' if the full configured physical memory is available. The value in parentheses represents the size that would result for the default maximum configured memory size of 4KBytes.
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SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.6 GMAC Transmit Status Register Name: Offset: Reset: Property: Bit GMAC_TSR 0x014 0x00000000 - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 HRESP R/W 0 7 6 5 TXCOMP R/W 0 4 TFC R/W 0 3 TXGO R/W 0 2 RLE R/W 0 1 COL R/W 0 0 UBR R/W 0 Access Reset Bit Access Reset Bit Access Reset Bit Access Reset Bit 8 – HRESP HRESP Not OK Set when the DMA block sees HRESP not OK.
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SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC This bit is cleared by writing a '1' to it. © 2019 Microchip Technology Inc.
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SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.7 GMAC Receive Buffer Queue Base Address Register Name: Offset: Reset: Property: GMAC_RBQB 0x018 0x00000000 Read/Write This register holds the start address of the receive buffer queue (receive buffers descriptor list). The receive buffer queue base address must be initialized before receive is enabled through bit 2 of the Network Control Register. Once reception is enabled, any write to the Receive Buffer Queue Base Address Register is ignored.
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SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.8 GMAC Transmit Buffer Queue Base Address Register Name: Offset: Reset: Property: GMAC_TBQB 0x01C 0x00000000 - This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The Transmit Buffer Queue Base Address Register must be initialized before transmit is started through bit 9 of the Network Control Register.
PAGE 636
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.9 GMAC Receive Status Register Name: Offset: Reset: Property: GMAC_RSR 0x020 0x00000000 - This register, when read, provides receive status details. Once read, individual bits may be cleared by writing a '1' to them. It is not possible to set a bit to '1' by writing to this register.
PAGE 637
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.10 GMAC Interrupt Status Register Name: Offset: Reset: Property: GMAC_ISR 0x024 0x00000000 Read-only This register indicates the source of the interrupt. An interrupt source must be enabled in the mask register first so the corresponding bits of this register will be set and the GMAC interrupt signal will be asserted in the system.
PAGE 638
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC Bit 22 – PDRQFR PDelay Request Frame Received Indicates a PTP pdelay_req frame has been received. Cleared on read. Bit 21 – SFT PTP Sync Frame Transmitted Indicates a PTP sync frame has been transmitted. Cleared on read. Bit 20 – DRQFT PTP Delay Request Frame Transmitted Indicates a PTP delay_req frame has been transmitted. Cleared on read. Bit 19 – SFR PTP Sync Frame Received Indicates a PTP sync frame has been received. Cleared on read.
PAGE 639
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC This interrupt is also set if a transmitter status write back has not completed when another status write back is attempted. This interrupt is also set when the transmit DMA has written the SOP data into the FIFO and either the AHB bus was not granted in time for further data, or because an AHB not OK response was returned, or because the used bit was read. Bit 3 – TXUBR TX Used Bit Read Set when a transmit buffer descriptor is read with its used bit set.
PAGE 640
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.11 GMAC Interrupt Enable Register Name: Offset: Reset: Property: GMAC_IER 0x028 – Write-only This register is write-only and will always return zero. The following values are valid for all listed bit names of this register: 0: No effect. 1: Enables the corresponding interrupt.
PAGE 641
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC Bit 18 – DRQFR PTP Delay Request Frame Received Bit 15 – EXINT External Interrupt Bit 14 – PFTR Pause Frame Transmitted Bit 13 – PTZ Pause Time Zero Bit 12 – PFNZ Pause Frame with Non-zero Pause Quantum Received Bit 11 – HRESP HRESP Not OK Bit 10 – ROVR Receive Overrun Bit 7 – TCOMP Transmit Complete Bit 6 – TFC Transmit Frame Corruption Due to AHB Error Bit 5 – RLEX Retry Limit Exceeded or Late Collision Bit 4 – TUR Transmit Underrun Bit 3 – TXUBR TX Used Bit
PAGE 642
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.12 GMAC Interrupt Disable Register Name: Offset: Reset: Property: GMAC_IDR 0x02C – Write-only This register is write-only and will always return zero. The following values are valid for all listed bit names of this register: 0: No effect. 1: Disables the corresponding interrupt.
PAGE 643
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC Bit 18 – DRQFR PTP Delay Request Frame Received Bit 15 – EXINT External Interrupt Bit 14 – PFTR Pause Frame Transmitted Bit 13 – PTZ Pause Time Zero Bit 12 – PFNZ Pause Frame with Non-zero Pause Quantum Received Bit 11 – HRESP HRESP Not OK Bit 10 – ROVR Receive Overrun Bit 7 – TCOMP Transmit Complete Bit 6 – TFC Transmit Frame Corruption Due to AHB Error Bit 5 – RLEX Retry Limit Exceeded or Late Collision Bit 4 – TUR Transmit Underrun Bit 3 – TXUBR TX Used Bit
PAGE 644
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.13 GMAC Interrupt Mask Register Name: Offset: Reset: Property: GMAC_IMR 0x030 0x07FFFFFF Read/Write This register is a read-only register indicating which interrupts are masked. All bits are set at Reset and can be reset individually by writing to the Interrupt Enable Register (GMAC_IER), or set individually by writing to the Interrupt Disable Register (GMAC_IDR).
PAGE 645
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC Bit 21 – SFT PTP Sync Frame Transmitted Bit 20 – DRQFT PTP Delay Request Frame Transmitted Bit 19 – SFR PTP Sync Frame Received Bit 18 – DRQFR PTP Delay Request Frame Received Bit 15 – EXINT External Interrupt Bit 14 – PFTR Pause Frame Transmitted Bit 13 – PTZ Pause Time Zero Bit 12 – PFNZ Pause Frame with Non-zero Pause Quantum Received Bit 11 – HRESP HRESP Not OK Bit 10 – ROVR Receive Overrun Bit 7 – TCOMP Transmit Complete Bit 6 – TFC Transmit Frame Corrupti
PAGE 646
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.14 GMAC PHY Maintenance Register Name: Offset: Reset: Property: GMAC_MAN 0x034 0x00000000 Read/Write This register is a shift register. Writing to it starts a shift operation which is signaled completed when bit 2 is set in the Network Status Register (GMAC_NSR). It takes about 2000 MCK cycles to complete, when MDC is set for MCK divide by 32 in the Network Configuration Register. An interrupt is generated upon completion.
PAGE 647
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC Bit Access Reset Bit Access Reset Bit 31 WZO R/W 0 30 CLTTO R/W 0 29 28 27 26 25 24 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 23 PHYA[23] R/W 0 22 21 19 R/W 0 R/W 0 20 REGA[4:0] R/W 0 18 17 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 R/W 0 R/W 0 R/W 0 R/W 0 3 2 1 0 R/W 0 R/W 0 R/W 0 R/W 0 OP[1:0] PHYA[4:1] 16 WTN[1:0] DATA[15:8] Access Reset Bit R/W 0 R/W 0 R/W 0 R/W 0 7 6 5 4 DATA[7:0] Access Reset R/W 0
PAGE 648
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 649
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 650
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 651
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 652
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 653
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.20 GMAC Hash Register Bottom Name: Offset: Reset: Property: GMAC_HRB 0x080 0x00000000 Read/Write The unicast hash enable (UNIHEN) and the multicast hash enable (MITIHEN) bits in the Network Configuration Register (GMAC_NCFGR) enable the reception of hash matched frames.
PAGE 654
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.21 GMAC Hash Register Top Name: Offset: Reset: Property: GMAC_HRT 0x084 0x00000000 Read/Write The Unicast Hash Enable (UNIHEN) and the Multicast Hash Enable (MITIHEN) bits in the Network Configuration Register (GMAC_NCFGR) enable the reception of hash matched frames.
PAGE 655
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.22 GMAC Specific Address n Bottom Register Name: Offset: Reset: Property: GMAC_SABx 0x88 + (x-1)*0x08 [x=1..4] 0x00000000 Read/Write The addresses stored in the Specific Address Registers are deactivated at reset or when their corresponding Specific Address Register Bottom is written. They are activated when Specific Address Register Top is written.
PAGE 656
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.23 GMAC Specific Address n Top Register Name: Offset: Reset: Property: GMAC_SATx 0x8C + (x-1)*0x08 [x=1..4] 0x00000000 Read/Write The addresses stored in the Specific Address Registers are deactivated at reset or when their corresponding Specific Address Register Bottom is written. They are activated when Specific Address Register Top is written.
PAGE 657
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.24 GMAC Type ID Match n Register Name: Offset: Reset: Property: Bit Access Reset Bit GMAC_TIDMx 0xA8 + (x-1)*0x04 [x=1..
PAGE 658
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 659
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 660
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 661
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 662
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 663
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 664
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 665
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 666
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 667
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 668
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 669
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 670
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 671
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.38 GMAC Octets Transmitted Low Register Name: Offset: Reset: Property: GMAC_OTLO 0x100 0x00000000 - When reading the Octets Transmitted and Octets Received Registers, bits [31:0] should be read prior to bits [47:32] to ensure reliable operation.
PAGE 672
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.39 GMAC Octets Transmitted High Register Name: Offset: Reset: Property: GMAC_OTHI 0x104 0x00000000 - When reading the Octets Transmitted and Octets Received Registers, bits [31:0] should be read prior to bits [47:32] to ensure reliable operation.
PAGE 673
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 674
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 675
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 676
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 677
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 678
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 679
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 680
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 681
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 682
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 683
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 684
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 685
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 686
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 687
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 688
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 689
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 690
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 691
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.58 GMAC Octets Received Low Register Name: Offset: Reset: Property: GMAC_ORLO 0x150 0x00000000 - When reading the Octets Transmitted and Octets Received Registers, bits [31:0] should be read prior to bits [47:32] to ensure reliable operation.
PAGE 692
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.59 GMAC Octets Received High Register Name: Offset: Reset: Property: GMAC_ORHI 0x154 0x00000000 - When reading the Octets Transmitted and Octets Received Registers, bits 31:0 should be read prior to bits 47:32 to ensure reliable operation.
PAGE 693
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 694
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 695
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 696
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 697
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 698
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 699
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 700
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 701
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 702
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 703
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 704
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 705
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 706
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 707
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 708
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 709
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 710
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 711
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 712
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 713
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 714
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 715
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 716
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 717
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 718
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 719
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 720
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 721
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 722
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 723
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 724
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 725
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 726
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 727
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 728
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 729
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 730
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 731
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 732
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 733
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.
PAGE 734
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.101 GMAC Interrupt Status Register Priority Queue x Name: Offset: Reset: Property: Bit GMAC_ISRPQx 0x0400 + (x-1)*0x04 [x=1..
PAGE 735
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.102 GMAC Transmit Buffer Queue Base Address Register Priority Queue x Name: Offset: Reset: Property: GMAC_TBQBAPQx 0x0440 + (x-1)*0x04 [x=1..5] 0x00000000 Read/Write These registers hold the start address of the transmit buffer queues (transmit buffers descriptor lists) for the additional queues and must be initialized to the address of valid descriptors, even if the priority queues are not used.
PAGE 736
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.103 GMAC Receive Buffer Queue Base Address Register Priority Queue x Name: Offset: Reset: Property: GMAC_RBQBAPQx 0x0480 + (x-1)*0x04 [x=1..5] 0x00000000 Read/Write These registers hold the start address of the receive buffer queues (receive buffers descriptor lists) for the additional queues used when priority queues are employed.
PAGE 737
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.104 GMAC Receive Buffer Size Register Priority Queue x Name: Offset: Reset: Property: Bit GMAC_RBSRPQx 0x04A0 + (x-1)*0x04 [x=1..
PAGE 738
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.105 GMAC Credit-Based Shaping Control Register Name: Offset: Reset: Property: Bit GMAC_CBSCR 0x4BC 0x00000000 Read/Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 QAE 0 QBE 0 0 Access Reset Bit Access Reset Bit Access Reset Bit Access Reset Bit 1 – QAE Value 0 1 Queue A CBS Enable Description Credit-based shaping on the second highest priority queue (queue A) is disabled.
PAGE 739
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.106 GMAC Credit-Based Shaping IdleSlope Register for Queue A Name: Offset: Reset: Property: GMAC_CBSISQA 0x4C0 0x00000000 Read/Write Credit-based shaping must be disabled in the GMAC_CBSCR before updating this register.
PAGE 740
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.107 GMAC Credit-Based Shaping IdleSlope Register for Queue B Name: Offset: Reset: Property: GMAC_CBSISQB 0x4C4 0x00000000 Read/Write Credit-based shaping must be disabled in the GMAC_CBSCR before updating this register.
PAGE 741
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.108 GMAC Screening Type 1 Register x Priority Queue Name: Offset: Reset: Property: GMAC_ST1RPQx 0x0500 + x*0x04 [x=0..3] 0x00000000 Read/Write Screening type 1 registers are used to allocate up to 6 priority queues to received frames based on certain IP or UDP fields of incoming frames.
PAGE 742
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.109 GMAC Screening Type 2 Register x Priority Queue Name: Offset: Reset: Property: GMAC_ST2RPQx 0x0540 + x*0x04 [x=0..7] 0x00000000 Read/Write Screening type 2 registers are used to allocate up to 6 priority queues to received frames based on the VLAN priority field of received Ethernet frames.
PAGE 743
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC Bits 17:13 – COMPA[4:0] Index of Screening Type 2 Compare Word 0/Word 1 register x COMPA is a pointer to the compare registers GMAC_ST2CW0x and GMAC_ST2CW1x. When COMPAE=1, the compare is true if the data at the frame offset ANDed with the value MASKVAL is equal to the value of COMPVAL ANDed with the value of MASKVAL.
PAGE 744
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.110 GMAC Interrupt Enable Register Priority Queue x Name: Offset: Reset: Property: GMAC_IERPQx 0x0600 + (x-1)*0x04 [x=1..5] – Write-only The following values are valid for all listed bit names of this register: 0: No effect. 1: Enables the corresponding interrupt.
PAGE 745
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.111 GMAC Interrupt Disable Register Priority Queue x Name: Offset: Reset: Property: GMAC_IDRPQx 0x0620 + (x-1)*0x04 [x=1..5] – Write-only The following values are valid for all listed bit names of this register: 0: No effect. 1: Disables the corresponding interrupt.
PAGE 746
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.112 GMAC Interrupt Mask Register Priority Queue x Name: Offset: Reset: Property: GMAC_IMRPQx 0x0640 + (x-1)*0x04 [x=1..5] 0x00000000 Read/Write A read of this register returns the value of the receive complete interrupt mask. A write to this register directly affects the state of the corresponding bit in the Interrupt Status Register, causing an interrupt to be generated if a '1' is written.
PAGE 747
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.113 GMAC Screening Type 2 EtherType Register x Name: Offset: Reset: Property: Bit GMAC_ST2ERx 0x06E0 + x*0x04 [x=0..
PAGE 748
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.114 GMAC Screening Type 2 Compare Word 0 Register x Name: Offset: Reset: Property: GMAC_ST2CW0x 0x0700 + x*0x08 [x=0..
PAGE 749
SAM E70/S70/V70/V71 Family GMAC - Ethernet MAC 38.8.115 GMAC Screening Type 2 Compare Word 1 Register x Name: Offset: Reset: Property: Bit GMAC_ST2CW1x 0x0704 + x*0x08 [x=0..
PAGE 750
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39. USB High-Speed Interface (USBHS) 39.1 Description The USB High-Speed Interface (USBHS) complies with the Universal Serial Bus (USB) 2.0 specification in all speeds. Each pipe/endpoint can be configured in one of several USB transfer types. It can be associated with one, two or three banks of a DPRAM used to store the current data payload.
PAGE 751
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.3 Block Diagram The USBHS provides a hardware device to interface a USB link to a data flow stored in a dual-port RAM (DPRAM). In normal operation (SPDCONF = 0), the UTMI transceiver requires the UTMI PLL (480 MHz). In case of full-speed or low-speed only, for a lower consumption (SPDCONF = 1), the UTMI transceiver only requires 48 MHz. Figure 39-1.
PAGE 752
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.4.2 Clocks The clock for the USBHS bus interface is generated by the Power Management Controller. This clock can be enabled or disabled in the Power Management Controller. It is recommended to disable the USBHS before disabling the clock, to avoid freezing the USBHS in an undefined state. Before enabling the USB clock in the Power Management Controller, the USBHS must be enabled (by writing a one to the USBHS_CTRL.
PAGE 753
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) Figure 39-2. General States Macro off: USBHS_CTRL.USBE = 0 Clock stopped: USBHS_CTRL.FRZCLK = 1 USBHS_CTRL.USBE = 0 Reset HW RESET USBHS_CTRL.USBE = 1 USBHS_CTRL.UIMOD = 1 USBHS_CTRL.USBE = 0 USBHS_CTRL.USBE = 1 USBHS_CTRL.UIMOD = 0 USBHS_CTRL_USBE = 0 Device Host After a hardware reset, the USBHS is in Reset state. In this state: • • • • • The USBHS is disabled.
PAGE 754
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) Figure 39-3. Interrupt System & = Logical AND USBHS_DEVEPTISRx.TXINI USBHS_DEVEPTIMRx.TXINE USBHS_SR.RDERRI USBHS_DEVEPTISRx.RXOUTI USB General Interrupt USBHS_CTRL.RDERRE USBHS_DEVEPTIMRx.RXOUTE USBHS_DEVEPTISRx.RXSTPI USBHS_DEVEPTIMRx.RXSTPE USBHS_DEVEPTISRx.UNDERFI USBHS_DEVEPTIMRx.UNDERFE USBHS_DEVEPTISRx.NAKOUTI USBHS_DEVEPTISRx.HBISOINERRI USBHS_DEVEPTIMRx.NAKOUTE USBHS_DEVEPTIMRx.HBISOINERRE USBHS_DEVEPTISRx.NAKINI USBHS_DEVEPTIMRx.
PAGE 755
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) • USBHS_CTRL.FRZCLK, USBHS_CTRL.USBE and USBHS_DEVCTRL.LS bits Moreover, when USBHS_CTRL.FRZCLK = 1, only the asynchronous interrupt sources can trigger the USB interrupt: • • Wakeup Interrupt (USBHS_DEVISR.WAKEUP) Host Wakeup Interrupt (USBHS_HSTISR.HWUPI) 39.5.1.
PAGE 756
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) Figure 39-4. Allocation and Reorganization of the DPRAM Free Memory Free Memory Free Memory Free Memory PEP5 PEP5 PEP5 PEP5 PEP4 PEP4 PEP4 Lost Memory PEP3 PEP3 (ALLOC stays at 1) PEP4 PEP2 PEP2 PEP2 PEP2 PEP1 PEP1 PEP1 PEP1 PEP0 PEP0 PEP0 PEP0 Conflict PEP4 Device: USBHS_DEVEPT.EPENx = 1 USBHS_DEVEPTCFGx.ALLOC = 1 Device: USBHS_DEVEPT.EPEN3 = 0 Device: USBHS_DEVEPTCFG3.ALLOC = 0 Device: USBHS_DEVEPT.
PAGE 757
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) Figure 39-5. Pad Behavior | = Logical OR & = Logical AND Idle USBHS_CTRL.USBE = 1 & USBHS_DEVCTRL.DETACH = 0 & Suspend USBHS_CTRL.USBE = 0 | USBHS_DEVCTRL.DETACH = 1 | Suspend • • Active In Idle state, the pad is put in Low-power mode, i.e., the differential receiver of the USB pad is off, and internal pull-downs with a strong value (15 K) are set in HSDP/D and HSDM/DM to avoid floating lines. In Active state, the pad is working.
PAGE 758
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) Figure 39-7. Device Mode Main States | = Logical OR & = Logical AND USBHS_CTRL.USBE = 0 | USBHS_CTRL.UIMOD = 0 USBHS_CTRL.USBE = 0 | USBHS_CTRL.UIMOD = 0 Reset Idle USBHS_CTRL.USBE = 1 and USBHS_CTRL.UIMOD = 1 HW USBHS_HSTCTRL.RESET After a hardware reset, the USBHS Device mode is in Reset state. In this state: • • • • the USBHS clock is stopped to minimize power consumption (USBHS_CTRL.
PAGE 759
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) The endpoint reset may be associated with a clear of the data toggle sequence as an answer to the CLEAR_FEATURE USB request. This can be achieved by writing a one to the Reset Data Toggle Set bit (RSTDTS) in the Device Endpoint x Control Set register (this sets the Reset Data Toggle bit USBHS_DEVEPTIMRx.RSTDT). In the end, the user has to write a zero to the USBHS_DEVEPT.EPRSTx bit to complete the reset operation and to start using the FIFO. 39.5.
PAGE 760
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.5.2.7 Suspend and Wakeup When an idle USB bus state has been detected for 3 ms, the controller sets the Suspend (USBHS_DEVISR.SUSP) interrupt bit. The user may then write a one to the USBHS_CTRL.FRZCLK bit to reduce power consumption. To recover from the Suspend mode, the user should wait for the Wakeup (USBHS_DEVISR.WAKEUP) interrupt bit, which is set when a non-idle event is detected, then write a zero to USBHS_CTRL.FRZCLK.
PAGE 761
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.5.2.11 Management of Control Endpoints Overview A SETUP request is always ACKed. When a new SETUP packet is received, the USBHS_DEVEPTISRx.RXSTPI is set; the Received OUT Data Interrupt (USBHS_DEVEPTISRx.RXOUTI) bit is not. The FIFO Control (USBHS_DEVEPTIMRx.FIFOCON) bit and the Read/Write Allowed (USBHS_DEVEPTISRx.RWALL) bit are irrelevant for control endpoints. The user never uses them on these endpoints.
PAGE 762
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) The OUT retry is always ACKed. This reception sets USBHS_DEVEPTISRx.RXOUTI and USBHS_DEVEPTISRx.TXINI. Handle this with the following software algorithm: set TXINI wait for RXOUTI OR TXINI if RXOUTI, then clear bit and return if TXINI, then continue Once the OUT status stage has been received, the USBHS waits for a SETUP request. The SETUP request has priority over any other request and has to be ACKed.
PAGE 763
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) Detailed Description The data is written as follows: • • • • When the bank is empty, USBHS_DEVEPTISRx.TXINI and USBHS_DEVEPTIMRx.FIFOCON are set, which triggers a PEP_x interrupt if USBHS_DEVEPTIMRx.TXINE = 1. The user acknowledges the interrupt by clearing USBHS_DEVEPTISRx.TXINI.
PAGE 764
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) The USBHS_DEVEPTISRx.RWALL bit is set when the current bank is not empty, i.e., when the software can read further data from the FIFO. Figure 39-14. Example of an OUT Endpoint with one Data Bank OUT DATA (bank 0) NAK ACK DATA (bank 0) OUT ACK HW HW USBHS_DEVEPTISRx.RXOUTI SW SW read data from CPU BANK 0 USBHS_DEVEPTIMRx.FIFOCON read data from CPU BANK 0 SW Figure 39-15.
PAGE 765
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) • • • An underflow cannot occur during the OUT stage on a CPU action, since the user may only read if the bank is not empty (USBHS_DEVEPTISRx.RXOUTI = 1 or USBHS_DEVEPTISRx.RWALL = 1). An underflow can also occur during the OUT stage if the host sends a packet while the bank is already full. Typically, the CPU is not fast enough. The packet is lost.
PAGE 766
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) • • • • • • End of Reset (USBHS_DEVISR.EORST) Wakeup (USBHS_DEVISR.WAKEUP) End of Resume (USBHS_DEVISR.EORSM) Upstream Resume (USBHS_DEVISR.UPRSM) Endpoint x (USBHS_DEVISR.PEP_x) DMA Channel x (USBHS_DEVISR.DMA_x) The exception device global interrupts are: • • Start of Frame (USBHS_DEVISR.SOF) with a frame number CRC error (USBHS_DEVFNUM.FNCERR = 1) Micro Start of Frame (USBHS_DEVFNUM.FNCERR.
PAGE 767
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.5.3 USB Host Operation 39.5.3.1 Description of Pipes For the USBHS in Host mode, the term “pipe” is used instead of “endpoint” (used in Device mode). A host pipe corresponds to a device endpoint, as described in Figure 39-16 (from the USB Specification). Figure 39-16. USB Communication Flow In Host mode, the USBHS associates a pipe to a device endpoint, considering the device configuration descriptors. 39.5.3.
PAGE 768
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.5.3.4 USB Reset The USBHS sends a USB bus reset when the user writes a one to the Send USB Reset bit in the Host General Control register (USBHS_HSTCTRL.RESET). The USB Reset Sent Interrupt bit in the Host Global Interrupt Status register (USBHS_HSTISR.RSTI) is set when the USB reset has been sent. In this case, all pipes are disabled and de-allocated.
PAGE 769
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) The USBHS_HSTPIPISRx.CFGOK bit is only set if the configured size and number of banks are correct as compared to their maximal allowed values for the pipe (see the Description of USB Pipes/Endpoints table) and to the maximal FIFO size (i.e., the DPRAM size). See "DPRAM Management" for additional information. Once the pipe is correctly configured (USBHS_HSTPIPISRx.CFGOK = 1), only the USBHS_HSTPIPCFGx.PTOKEN and USBHS_HSTPIPCFGx.
PAGE 770
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) The generation of IN requests starts when the pipe is unfrozen (the Pipe Freeze (USBHS_HSTPIPIMRx.PFREEZE) field in USBHS_HSTPIPIMRx is zero). The Received IN Data Interrupt (USBHS_HSTPIPISRx.RXINI) bit is set at the same time as the FIFO Control (USBHS_HSTPIPIMRx.FIFOCON) bit when the current bank is full. This triggers a PEP_x interrupt if the Received IN Data Interrupt Enable (USBHS_HSTPIPIMRx.RXINE) bit is one. USBHS_HSTPIPISRx.
PAGE 771
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) The USBHS_HSTPIPISRx.RWALL bit is set when the current bank is not full, i.e., when the software can write further data into the FIFO. Note: 1. If the user decides to switch to the Suspend state (by writing a zero to the USBHS_HSTCTRL.SOFE bit) while a bank is ready to be sent, the USBHS automatically exits this state and the bank is sent. 2.
PAGE 772
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) There are two kinds of host interrupts: processing, i.e., their generation is part of the normal processing, and exception, i.e., errors (not related to CPU exceptions). Global Interrupts The processing host global interrupts are: • • • • • • • • • Device Connection (USBHS_HSTISR.DCONNI) Device Disconnection (USBHS_HSTISR.DDISCI) USB Reset Sent (USBHS_HSTISR.RSTI) Downstream Resume Sent (USBHS_HSTISR.RSMEDI) Upstream Resume Received (USBHS_HSTISR.
PAGE 773
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) (USBHS_HSTPIPCFGx.PSIZE / USBHS_DEVEPTCFGx.EPSIZE) and the Buffer Byte Length (USBHS_HSTDMACONTROLx.BUFF_LENGTH / USBHS_DEVDMACONTROLx.BUFF_LENGTH) fields. The USBHS average throughput can reach nearly 480 Mbps. Its average access latency decreases as burst length increases due to the zero wait-state side effect of unchanged pipe/endpoint. Word access allows reducing the AHB bandwidth required for the USB by four, as compared to native byte access.
PAGE 774
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6 Register Summary Offset Name 0x00 USBHS_DEVCTRL 0x04 0x08 0x0C 0x10 0x14 0x18 USBHS_DEVISR USBHS_DEVICR USBHS_DEVIFR USBHS_DEVIMR USBHS_DEVIDR USBHS_DEVIER 0x1C USBHS_DEVEPT 0x20 USBHS_DEVFNUM 0x24 ... 0xFF Reserved 0x0100 USBHS_DEVEPTC FG0 0x0104 USBHS_DEVEPTC FG1 0x0108 USBHS_DEVEPTC FG2 0x010C USBHS_DEVEPTC FG3 Bit Pos.
PAGE 775
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) ...........continued Offset Name 0x0110 USBHS_DEVEPTC FG4 0x0114 USBHS_DEVEPTC FG5 0x0118 USBHS_DEVEPTC FG6 0x011C USBHS_DEVEPTC FG7 0x0120 USBHS_DEVEPTC FG8 0x0124 USBHS_DEVEPTC FG9 0x0128 ... 0x012F Reserved Bit Pos.
PAGE 776
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) ...........continued Offset Name Bit Pos.
PAGE 777
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) ...........continued Offset Name Bit Pos.
PAGE 778
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) ...........continued Offset Name 0x0168 USBHS_DEVEPTIC R2 (ISOENPT) 0x016C USBHS_DEVEPTIC R3 0x016C USBHS_DEVEPTIC R3 (ISOENPT) 0x0170 USBHS_DEVEPTIC R4 0x0170 USBHS_DEVEPTIC R4 (ISOENPT) 0x0174 USBHS_DEVEPTIC R5 0x0174 USBHS_DEVEPTIC R5 (ISOENPT) 0x0178 USBHS_DEVEPTIC R6 0x0178 USBHS_DEVEPTIC R6 (ISOENPT) 0x017C USBHS_DEVEPTIC R7 0x017C USBHS_DEVEPTIC R7 (ISOENPT) Bit Pos.
PAGE 779
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) ...........continued Offset Name 0x0180 USBHS_DEVEPTIC R8 0x0180 USBHS_DEVEPTIC R8 (ISOENPT) 0x0184 USBHS_DEVEPTIC R9 0x0184 USBHS_DEVEPTIC R9 (ISOENPT) 0x0188 ... 0x018F Reserved Bit Pos.
PAGE 780
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) ...........continued Offset Name 0x019C USBHS_DEVEPTIF R3 (ISOENPT) 0x01A0 USBHS_DEVEPTIF R4 0x01A0 USBHS_DEVEPTIF R4 (ISOENPT) 0x01A4 USBHS_DEVEPTIF R5 0x01A4 USBHS_DEVEPTIF R5 (ISOENPT) 0x01A8 USBHS_DEVEPTIF R6 0x01A8 USBHS_DEVEPTIF R6 (ISOENPT) 0x01AC USBHS_DEVEPTIF R7 0x01AC USBHS_DEVEPTIF R7 (ISOENPT) 0x01B0 USBHS_DEVEPTIF R8 0x01B0 USBHS_DEVEPTIF R8 (ISOENPT) Bit Pos.
PAGE 781
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) ...........continued Offset Name 0x01B4 USBHS_DEVEPTIF R9 0x01B4 USBHS_DEVEPTIF R9 (ISOENPT) 0x01B8 ... 0x01BF Reserved Bit Pos.
PAGE 782
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) ...........continued Offset Name 0x01D0 USBHS_DEVEPTIM R4 Bit Pos.
PAGE 783
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) ...........continued Offset Name 0x01E4 USBHS_DEVEPTIM R9 Bit Pos. 7:0 15:8 23:16 31:24 7:0 0x01E4 USBHS_DEVEPTIM R9 (ISOENPT) SHORTPACK ETE SHORTPACK ETE 15:8 STALLEDE OVERFE NAKINE FIFOCON KILLBK NBUSYBKE CRCERRE OVERFE FIFOCON KILLBK NAKOUTE RXSTPE RXOUTE TXINE STALLRQ RSTDT NYETDIS EPDISHDMA UNDERFE RXOUTE TXINE DATAXE MDATAE HBISOFLUSH HBISOINERR E E ERRORTRAN SE RSTDT NBUSYBKE 23:16 31:24 0x01E8 ...
PAGE 784
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) ...........continued Offset 0x01FC Name USBHS_DEVEPTIE R3 (ISOENPT) Bit Pos.
PAGE 785
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) ...........continued Offset Name Bit Pos.
PAGE 786
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) ...........continued Offset Name Bit Pos.
PAGE 787
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) ...........continued Offset 0x0238 Name USBHS_DEVEPTID R6 (ISOENPT) Bit Pos.
PAGE 788
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) ...........continued Offset Name Bit Pos.
PAGE 789
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) ...........continued Offset Name 0x0340 USBHS_DEVDMAN XTDSC5 0x0344 USBHS_DEVDMAA DDRESS5 0x0348 USBHS_DEVDMAC ONTROL5 0x034C USBHS_DEVDMAS TATUS5 0x0350 USBHS_DEVDMAN XTDSC6 0x0354 USBHS_DEVDMAA DDRESS6 0x0358 USBHS_DEVDMAC ONTROL6 0x035C USBHS_DEVDMAS TATUS6 0x0360 USBHS_DEVDMAN XTDSC7 0x0364 USBHS_DEVDMAA DDRESS7 0x0368 USBHS_DEVDMAC ONTROL7 0x036C USBHS_DEVDMAS TATUS7 0x0370 ...
PAGE 790
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) ...........continued Offset Name 0x0408 USBHS_HSTICR 0x040C 0x0410 0x0414 0x0418 USBHS_HSTIFR USBHS_HSTIMR USBHS_HSTIDR USBHS_HSTIER 0x041C USBHS_HSTPIP 0x0420 USBHS_HSTFNUM 0x0424 USBHS_HSTADDR 1 0x0428 USBHS_HSTADDR 2 0x042C USBHS_HSTADDR 3 0x0430 ... 0x04FF Reserved 0x0500 USBHS_HSTPIPCF G0 0x0500 USBHS_HSTPIPCF G0 (HSBOHSCP) 0x0504 USBHS_HSTPIPCF G1 0x0504 USBHS_HSTPIPCF G1 (HSBOHSCP) Bit Pos.
PAGE 791
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) ...........
PAGE 792
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) ...........continued Offset Name 0x0524 USBHS_HSTPIPCF G9 0x0524 USBHS_HSTPIPCF G9 (HSBOHSCP) 0x0528 ... 0x052F Reserved Bit Pos.
PAGE 793
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) ...........continued Offset Name 0x053C USBHS_HSTPIPIS R3 Bit Pos.
PAGE 794
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) ...........continued Offset Name 0x0548 USBHS_HSTPIPIS R6 (ISOPIPES) Bit Pos.
PAGE 795
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) ...........continued Offset Name 0x0560 USBHS_HSTPIPIC R0 (INTPIPES) 0x0560 USBHS_HSTPIPIC R0 (ISOPIPES) 0x0564 USBHS_HSTPIPIC R1 0x0564 USBHS_HSTPIPIC R1 (INTPIPES) 0x0564 USBHS_HSTPIPIC R1 (ISOPIPES) 0x0568 USBHS_HSTPIPIC R2 0x0568 USBHS_HSTPIPIC R2 (INTPIPES) 0x0568 USBHS_HSTPIPIC R2 (ISOPIPES) 0x056C USBHS_HSTPIPIC R3 0x056C USBHS_HSTPIPIC R3 (INTPIPES) 0x056C USBHS_HSTPIPIC R3 (ISOPIPES) Bit Pos.
PAGE 796
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) ...........continued Offset Name 0x0570 USBHS_HSTPIPIC R4 0x0570 USBHS_HSTPIPIC R4 (INTPIPES) 0x0570 USBHS_HSTPIPIC R4 (ISOPIPES) 0x0574 USBHS_HSTPIPIC R5 0x0574 USBHS_HSTPIPIC R5 (INTPIPES) 0x0574 USBHS_HSTPIPIC R5 (ISOPIPES) 0x0578 USBHS_HSTPIPIC R6 0x0578 USBHS_HSTPIPIC R6 (INTPIPES) 0x0578 USBHS_HSTPIPIC R6 (ISOPIPES) 0x057C USBHS_HSTPIPIC R7 0x057C USBHS_HSTPIPIC R7 (INTPIPES) Bit Pos.
PAGE 797
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) ...........continued Offset Name 0x057C USBHS_HSTPIPIC R7 (ISOPIPES) 0x0580 USBHS_HSTPIPIC R8 0x0580 USBHS_HSTPIPIC R8 (INTPIPES) 0x0580 USBHS_HSTPIPIC R8 (ISOPIPES) 0x0584 USBHS_HSTPIPIC R9 0x0584 USBHS_HSTPIPIC R9 (INTPIPES) 0x0584 USBHS_HSTPIPIC R9 (ISOPIPES) 0x0588 ... 0x058F Reserved Bit Pos.
PAGE 798
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) ...........
PAGE 799
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) ...........continued Offset Name 0x05AC USBHS_HSTPIPIF R7 (INTPIPES) 0x05AC USBHS_HSTPIPIF R7 (ISOPIPES) 0x05B0 USBHS_HSTPIPIF R8 (INTPIPES) 0x05B0 USBHS_HSTPIPIF R8 (ISOPIPES) 0x05B4 USBHS_HSTPIPIF R9 (INTPIPES) 0x05B4 USBHS_HSTPIPIF R9 (ISOPIPES) 0x05B8 ... 0x05BF Reserved Bit Pos.
PAGE 800
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) ...........continued Offset Name 0x05C4 USBHS_HSTPIPIM R1 (ISOPIPES) Bit Pos.
PAGE 801
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) ...........continued Offset Name 0x05D4 USBHS_HSTPIPIM R5 (INTPIPES) Bit Pos.
PAGE 802
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) ...........continued Offset Name 0x05E4 USBHS_HSTPIPIM R9 Bit Pos. 7:0 15:8 23:16 31:24 7:0 0x05E4 USBHS_HSTPIPIM R9 (INTPIPES) 15:8 23:16 31:24 7:0 0x05E4 0x05E8 ...
PAGE 803
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) ...........continued Offset Name 0x05F8 USBHS_HSTPIPIE R2 (ISOPIPES) Bit Pos.
PAGE 804
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) ...........continued Offset Name 0x0608 USBHS_HSTPIPIE R6 (INTPIPES) Bit Pos. 7:0 15:8 23:16 31:24 7:0 0x0608 USBHS_HSTPIPIE R6 (ISOPIPES) 0x060C 0x060C 0x060C 0x0610 0x0610 0x0610 0x0614 0x0614 0x0614 0x0618 ...
PAGE 805
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) ...........continued Offset Name 0x0620 USBHS_HSTPIPID R0 Bit Pos.
PAGE 806
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) ...........continued Offset Name 0x062C USBHS_HSTPIPID R3 (ISOPIPES) Bit Pos.
PAGE 807
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) ...........continued Offset Name 0x063C USBHS_HSTPIPID R7 (INTPIPES) Bit Pos.
PAGE 808
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) ...........continued Offset Name 0x0660 USBHS_HSTPIPIN RQ4 0x0664 USBHS_HSTPIPIN RQ5 0x0668 USBHS_HSTPIPIN RQ6 0x066C USBHS_HSTPIPIN RQ7 0x0670 USBHS_HSTPIPIN RQ8 0x0674 USBHS_HSTPIPIN RQ9 0x0678 ...
PAGE 809
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) ...........continued Offset Name 0x06A0 USBHS_HSTPIPER R8 0x06A4 USBHS_HSTPIPER R9 0x06A8 ...
PAGE 810
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) ...........
PAGE 811
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) ...........continued Offset Name Bit Pos. USBHS_HSTDMAC ONTROLx 7:0 15:8 23:16 31:24 BURST_LCK DESC_LD_IT END_BUFFIT END_TR_IT 0x0768 0x076C 7:0 15:8 23:16 31:24 DESC_LDST END_BF_ST END_TR_ST USBHS_HSTDMAS TATUSx 0x0770 ...
PAGE 812
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6.1 General Control Register Name: Offset: Reset: Property: Bit 31 USBHS_CTRL 0x0800 0x03004000 Read/Write 30 29 28 27 26 Access Reset Bit 25 UIMOD 24 UID 1 1 23 22 21 20 19 18 17 16 15 USBE 14 FRZCLK 13 12 11 10 9 8 VBUSHWC Access Reset 0 1 Bit 7 6 Access Reset Bit 0 5 Access Reset 4 RDERRE 3 2 1 0 0 Bit 25 – UIMOD USBHS Mode 0 (HOST): The module is in USB Host mode.
PAGE 813
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) Value 0 1 0 1 Description The hardware control over the VBOF output pin is enabled. The USBHS resets the VBOF output pin when a VBUS problem occurs. The hardware control over the VBOF output pin is disabled. The hardware control over the PIO line is enabled. The USBHS resets the PIO output pin when a VBUS problem occurs. The hardware control over the PIO line is disabled.
PAGE 814
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6.2 General Status Register Name: Offset: Reset: Property: Bit USBHS_SR 0x0804 0x00000400 Read-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 CLKUSABLE 13 12 11 10 9 8 0 0 0 6 5 4 RDERRI 3 2 1 0 Access Reset Bit Access Reset Bit Access Reset Bit 7 Access Reset SPEED[1:0] 0 Bit 14 – CLKUSABLE UTMI Clock Usable Value Description 0 Cleared when the UTMI 30 MHz is not usable.
PAGE 815
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6.3 General Status Clear Register Name: Offset: Property: USBHS_SCR 0x0808 Write-only This register always reads as zero. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 RDERRIC 3 2 1 0 Access Reset Bit Access Reset Bit Access Reset Bit Access Reset Bit 4 – RDERRIC Remote Device Connection Error Interrupt Clear Value Description 0 No effect.
PAGE 816
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6.4 General Status Set Register Name: Offset: Property: USBHS_SFR 0x080C Write-only This register always reads as zero. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 VBUSRQS 8 7 6 5 4 RDERRIS 3 2 1 0 Access Reset Bit Access Reset Bit Access Reset Bit Access Reset Bit 9 – VBUSRQS VBUS Request Set Must be set to ‘1’. Value Description 0 No effect. 1 Sets the VBUSRQ bit in USBHS_SR.
PAGE 817
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6.
PAGE 818
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) Bits 11:10 – SPDCONF[1:0] Mode Configuration This field contains the peripheral speed: Value Name Description 0 NORMAL The peripheral starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the host is high-speed-capable. 1 LOW_POWER For a better consumption, if high speed is not needed. 2 HIGH_SPEED Forced high speed. 3 FORCED_FS The peripheral remains in Full-speed mode whatever the host speed capability.
PAGE 819
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6.
PAGE 820
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) Value 1 Description Set when the USBHS is reactivated by a filtered non-idle signal from the lines (not by an upstream resume). This triggers an interrupt if USBHS_DEVIMR.WAKEUPE = 1. Bit 3 – EORST End of Reset Interrupt Value Description 0 Cleared when the USBHS_DEVICR.EORSTC bit is written to one to acknowledge the interrupt. 1 Set when a USB “End of Reset” has been detected. This triggers a USB interrupt if USBHS_DEVIMR.EORSTE = 1.
PAGE 821
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6.7 Device Global Interrupt Clear Register Name: Offset: Property: USBHS_DEVICR 0x0008 Write-only This register always reads as zero. The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Clears the corresponding bit in USBHS_DEVISR.
PAGE 822
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6.8 Device Global Interrupt Set Register Name: Offset: Property: USBHS_DEVIFR 0x000C Write-only This register always reads as zero. The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Sets the corresponding bit in USBHS_DEVISR.
PAGE 823
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6.9 Device Global Interrupt Mask Register Name: Offset: Reset: Property: USBHS_DEVIMR 0x0010 0x00000000 Read-only The following configuration values are valid for all listed bit names of this register: 0: The corresponding interrupt is not enabled. 1: The corresponding interrupt is enabled.
PAGE 824
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6.10 Device Global Interrupt Disable Register Name: Offset: Property: USBHS_DEVIDR 0x0014 Write-only This register always reads as zero. The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Clears the corresponding bit in USBHS_DEVIMR.
PAGE 825
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6.11 Device Global Interrupt Enable Register Name: Offset: Property: USBHS_DEVIER 0x0018 Write-only This register always reads as zero. The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Sets the corresponding bit in USBHS_DEVIMR.
PAGE 826
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6.
PAGE 827
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6.
PAGE 828
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6.14 Device Endpoint x Configuration Register Name: Offset: Reset: Property: Bit USBHS_DEVEPTCFGx 0x0100 + x*0x04 [x=0..
PAGE 829
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 0 (OUT): The endpoint direction is OUT. 1 (IN): The endpoint direction is IN (nor for control endpoints). Bits 6:4 – EPSIZE[2:0] Endpoint Size This field should be written to select the size of each endpoint bank: This field is cleared upon receiving a USB reset (except for endpoint 0).
PAGE 830
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6.15 Device Endpoint Interrupt Status Register (Control, Bulk, Interrupt Endpoints) Name: Offset: Reset: Property: USBHS_DEVEPTISRx 0x0130 + x*0x04 [x=0..9] 0 Read/Write This register view is relevant only if EPTYPE = 0x0, 0x2, or 0x3 in the ”Device Endpoint x Configuration Register”.
PAGE 831
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) This bit is cleared otherwise. This bit should not be used for control endpoints. Bits 15:14 – CURRBK[1:0] Current Bank This bit is set for non-control endpoints, to indicate the current bank: This field may be updated one clock cycle after the RWALL bit changes, so the user should not poll this field as an interrupt bit.
PAGE 832
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) Bit 5 – OVERFI Overflow Interrupt For all endpoint types, an overflow can occur during the OUT stage if the host attempts to write into a bank that is too small for the packet. The packet is acknowledged and the USBHS_DEVEPTISRx.RXOUTI bit is set as if no overflow had occurred. The bank is filled with all the first bytes of the packet that fit in. Value Description 0 Cleared when the OVERFIC bit is written to one. This acknowledges the interrupt.
PAGE 833
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6.16 Device Endpoint Interrupt Status Register (Isochronous Endpoints) Name: Offset: Reset: Property: USBHS_DEVEPTISRx (ISOENPT) 0x0130 + x*0x04 [x=0..9] 0 Read/Write This register view is relevant only if EPTYPE = 0x1 in the ”Device Endpoint x Configuration Register”.
PAGE 834
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) Value 0 1 2 3 Name BANK0 BANK1 BANK2 Reserved Description Current bank is bank0 Current bank is bank1 Current bank is bank2 Bits 13:12 – NBUSYBK[1:0] Number of Busy Banks This field is set to indicate the number of busy banks: For IN endpoints, it indicates the number of banks filled by the user and ready for IN transfer. When all banks are free, this triggers a PEP_x interrupt if NBUSYBKE = 1.
PAGE 835
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) Bit 6 – CRCERRI CRC Error Interrupt Value Description 0 Cleared when CRCERRIC = 1. This acknowledges the interrupt. 1 Set to signal that a CRC error has been detected in an isochronous OUT endpoint. The OUT packet is stored in the bank as if no CRC error had occurred. This triggers a PEP_x interrupt if CRCERRE = 1. Bit 5 – OVERFI Overflow Interrupt Value Description 0 Cleared when OVERFIC = 1. This acknowledges the interrupt.
PAGE 836
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) For IN endpoints: 0: Cleared when TXINIC = 1. This acknowledges the interrupt, which has no effect on the endpoint FIFO. USBHS_DEVEPTISRx.TXINI shall always be cleared before clearing USBHS_DEVEPTIMRx.FIFOCON. 1: Set at the same time as USBHS_DEVEPTIMRx.FIFOCON when the current bank is free. This triggers a PEP_x interrupt if TXINE = 1. The user writes into the FIFO and clears the USBHS_DEVEPTIMRx.FIFOCON bit to allow the USBHS to send the data.
PAGE 837
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6.17 Device Endpoint Interrupt Clear Register (Control, Bulk, Interrupt Endpoints) Name: Offset: Reset: Property: USBHS_DEVEPTICRx 0x0160 + x*0x04 [x=0..9] 0 Read/Write This register view is relevant only if EPTYPE = 0x0, 0x2, or 0x3 in the ”Device Endpoint x Configuration Register”. For additional information, see ”Device Endpoint x Status Register (Control, Bulk, Interrupt Endpoints)”. This register always reads as zero.
PAGE 838
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6.18 Device Endpoint Interrupt Clear Register (Isochronous Endpoints) Name: Offset: Reset: Property: USBHS_DEVEPTICRx (ISOENPT) 0x0160 + x*0x04 [x=0..9] 0 Read/Write This register view is relevant only if EPTYPE = 0x1 in ”Device Endpoint x Configuration Register”. For additional information, see ”Device Endpoint x Status Register (Isochronous Endpoints)”. This register always reads as zero.
PAGE 839
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6.19 Device Endpoint Interrupt Set Register (Control, Bulk, Interrupt Endpoints) Name: Offset: Reset: Property: USBHS_DEVEPTIFRx 0x0190 + x*0x04 [x=0..9] 0 Read/Write This register view is relevant only if EPTYPE = 0x0, 0x2, or 0x3 in ”Device Endpoint x Configuration Register”. For additional information, see ”Device Endpoint x Status Register (Control, Bulk, Interrupt Endpoints)”.This register always reads as zero.
PAGE 840
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6.20 Device Endpoint Interrupt Set Register (Isochronous Endpoints) Name: Offset: Reset: Property: USBHS_DEVEPTIFRx (ISOENPT) 0x0190 + x*0x04 [x=0..9] 0 Read/Write This register view is relevant only if EPTYPE = 0x1 in ”Device Endpoint x Configuration Register”. For additional information, see ”Device Endpoint x Status Register (Isochronous Endpoints)”.
PAGE 841
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6.21 Device Endpoint Interrupt Mask Register (Control, Bulk, Interrupt Endpoints) Name: Offset: Reset: Property: USBHS_DEVEPTIMRx 0x01C0 + x*0x04 [x=0..9] 0 Read/Write This register view is relevant only if EPTYPE = 0x0, 0x2, or 0x3 in ”Device Endpoint x Configuration Register”.
PAGE 842
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) In Ping-pong mode, if the interrupt is associated to a new system-bank packet (e.g. Bank1) and the current DMA transfer is running on the previous packet (Bank0), then the previous-packet DMA transfer completes normally, but the new-packet DMA transfer does not start (not requested). If the interrupt is not associated to a new system-bank packet (USBHS_DEVEPTISRx.NAKINI, NAKOUTI, etc.
PAGE 843
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) Value 0 1 Description Cleared when USBHS_DEVEPTIDRx.STALLEDEC = 1. This disables the STALLed interrupt (USBHS_DEVEPTISRx.STALLEDI). Set when USBHS_DEVEPTIERx.STALLEDES = 1. This enables the STALLed interrupt (USBHS_DEVEPTISRx.STALLEDI). Bit 5 – OVERFE Overflow Interrupt Value Description 0 Cleared when USBHS_DEVEPTIDRx.OVERFEC = 1. This disables the Overflow interrupt (USBHS_DEVEPTISRx.OVERFI). 1 Set when USBHS_DEVEPTIERx.OVERFES = 1.
PAGE 844
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6.22 Device Endpoint Interrupt Mask Register (Isochronous Endpoints) Name: Offset: Reset: Property: USBHS_DEVEPTIMRx (ISOENPT) 0x01C0 + x*0x04 [x=0..9] 0 Read/Write This register view is relevant only if EPTYPE = 0x1 in ”Device Endpoint x Configuration Register”.
PAGE 845
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 0: Cleared (by writing a one to the USBHS_DEVEPTIDRx.FIFOCONC bit) to send the FIFO data and to switch to the next bank. 1: Set when the current bank is free, at the same time as USBHS_DEVEPTISRx.TXINI. For OUT endpoints: 0: Cleared (by writing a one to the USBHS_DEVEPTIDRx.FIFOCONC bit) to free the current bank and to switch to the next bank. 1: Set when the current bank is full, at the same time as USBHS_DEVEPTISRx.RXOUTI.
PAGE 846
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) Value 0 1 Description Cleared when USBHS_DEVEPTIDRx.SHORTPACKETEC = 1. This disables the Short Packet interrupt (USBHS_DEVEPTISRx.SHORTPACKET). Set when USBHS_DEVEPTIERx.SHORTPACKETES = 1. This enables the Short Packet interrupt (USBHS_DEVEPTISRx.SHORTPACKET). Bit 6 – CRCERRE CRC Error Interrupt Value Description 0 Cleared when USBHS_DEVEPTIDRx.CRCERREC = 1. This disables the CRC Error interrupt (USBHS_DEVEPTISRx.CRCERRI).
PAGE 847
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6.23 Device Endpoint Interrupt Disable Register (Control, Bulk, Interrupt Endpoints) Name: Offset: Reset: Property: USBHS_DEVEPTIDRx 0x0220 + x*0x04 [x=0..9] 0 Read/Write This register view is relevant only if EPTYPE = 0x0, 0x2, or 0x3 in ”Device Endpoint x Configuration Register”. For additional information, see ”Device Endpoint x Mask Register (Control, Bulk, Interrupt Endpoints)”. This register always reads as zero.
PAGE 848
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) Bit 2 – RXSTPEC Received SETUP Interrupt Clear Bit 1 – RXOUTEC Received OUT Data Interrupt Clear Bit 0 – TXINEC Transmitted IN Interrupt Clear © 2019 Microchip Technology Inc.
PAGE 849
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6.24 Device Endpoint Interrupt Disable Register (Isochronous Endpoints) Name: Offset: Reset: Property: USBHS_DEVEPTIDRx (ISOENPT) 0x0220 + x*0x04 [x=0..9] 0 Read/Write This register view is relevant only if EPTYPE = 0x1 in ”Device Endpoint x Configuration Register”. For additional information, see ”Device Endpoint x Mask Register (Isochronous Endpoints)”. This register always reads as zero.
PAGE 850
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) Bit 4 – HBISOFLUSHEC High Bandwidth Isochronous IN Flush Interrupt Clear Bit 3 – HBISOINERREC High Bandwidth Isochronous IN Error Interrupt Clear Bit 2 – UNDERFEC Underflow Interrupt Clear Bit 1 – RXOUTEC Received OUT Data Interrupt Clear Bit 0 – TXINEC Transmitted IN Interrupt Clear © 2019 Microchip Technology Inc.
PAGE 851
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6.25 Device Endpoint Interrupt Enable Register (Control, Bulk, Interrupt Endpoints) Name: Offset: Reset: Property: USBHS_DEVEPTIERx 0x01F0 + x*0x04 [x=0..9] 0 Read/Write This register view is relevant only if EPTYPE = 0x0, 0x2, or 0x3 in ”Device Endpoint x Configuration Register”. For additional information, see ”Device Endpoint x Mask Register (Control, Bulk, Interrupt Endpoints)”. This register always reads as zero.
PAGE 852
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) Bit 4 – NAKINES NAKed IN Interrupt Enable Bit 3 – NAKOUTES NAKed OUT Interrupt Enable Bit 2 – RXSTPES Received SETUP Interrupt Enable Bit 1 – RXOUTES Received OUT Data Interrupt Enable Bit 0 – TXINES Transmitted IN Data Interrupt Enable © 2019 Microchip Technology Inc.
PAGE 853
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6.26 Device Endpoint Interrupt Enable Register (Isochronous Endpoints) Name: Offset: Reset: Property: USBHS_DEVEPTIERx (ISOENPT) 0x01F0 + x*0x04 [x=0..9] 0 Read/Write This register view is relevant only if EPTYPE = 0x1 in ”Device Endpoint x Configuration Register”. For additional information, see ”Device Endpoint x Mask Register (Isochronous Endpoints)”. This register always reads as zero.
PAGE 854
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) Bit 6 – CRCERRES CRC Error Interrupt Enable Bit 5 – OVERFES Overflow Interrupt Enable Bit 4 – HBISOFLUSHES High Bandwidth Isochronous IN Flush Interrupt Enable Bit 3 – HBISOINERRES High Bandwidth Isochronous IN Error Interrupt Enable Bit 2 – UNDERFES Underflow Interrupt Enable Bit 1 – RXOUTES Received OUT Data Interrupt Enable Bit 0 – TXINES Transmitted IN Data Interrupt Enable © 2019 Microchip Technology Inc.
PAGE 855
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6.27 Device DMA Channel x Next Descriptor Address Register Name: Offset: Reset: Property: USBHS_DEVDMANXTDSCx 0x0300 + (x-1)*0x10 [x=1..
PAGE 856
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6.28 Device DMA Channel x Address Register Name: Offset: Reset: Property: USBHS_DEVDMAADDRESSx 0x0304 + (x-1)*0x10 [x=1..
PAGE 857
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6.29 Device DMA Channel x Control Register Name: Offset: Reset: Property: USBHS_DEVDMACONTROLx 0x0308 + (x-1)*0x10 [x=1..
PAGE 858
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) Value 0 1 Description USBHS device-initiated buffer transfer completion does not trigger any interrupt at USBHS_DEVDMASTATUSx.END_TR_ST rising. An interrupt is sent after the buffer transfer is complete, if the USBHS device has ended the buffer transfer.
PAGE 859
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) Value 1 Description The USBHS_DEVDMASTATUS.CHANN_ENB bit is set, thus enabling the DMA channel data transfer. Then, any pending request starts the transfer. This may be used to start or resume any requested transfer. © 2019 Microchip Technology Inc.
PAGE 860
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6.30 Device DMA Channel x Status Register Name: Offset: Reset: Property: USBHS_DEVDMASTATUSx 0x030C + (x-1)*0x10 [x=1..
PAGE 861
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) Bit 1 – CHANN_ACT Channel Active Status When a packet transfer is ended, this bit is automatically reset. When a packet transfer cannot be completed due to an END_BF_ST, this flag stays set during the next channel descriptor load (if any) and potentially until completion of a USBHS packet transfer, if allowed by the new descriptor. Value Description 0 The DMA channel is no longer trying to source the packet data.
PAGE 862
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6.31 Host General Control Register Name: Offset: Reset: Property: Bit USBHS_HSTCTRL 0x0400 0x00000000 Read/Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 SPDCONF[1:0] 11 10 RESUME 9 RESET 8 SOFE 0 0 0 2 1 0 Access Reset Bit Access Reset Bit Access Reset Bit 7 6 0 0 5 4 3 Access Reset Bits 13:12 – SPDCONF[1:0] Mode Configuration This field contains the host speed capability:.
PAGE 863
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) Value 1 Description Generates SOF on the USB bus in Full- or High-speed mode and sends “keep alive” signals in Lowspeed mode. © 2019 Microchip Technology Inc.
PAGE 864
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6.
PAGE 865
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) Bit 3 – RSMEDI Downstream Resume Sent Interrupt Value Description 0 Cleared when USBHS_HSTICR.RSMEDIC = 1. 1 Set when a Downstream Resume has been sent to the device. Bit 2 – RSTI Value 0 1 USB Reset Sent Interrupt Description Cleared when USBHS_HSTICR.RSTIC = 1. Set when a USB Reset has been sent to the device. Bit 1 – DDISCI Device Disconnection Interrupt Value Description 0 Cleared when USBHS_HSTICR.DDISCIC = 1.
PAGE 866
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6.33 Host Global Interrupt Clear Register Name: Offset: Property: USBHS_HSTICR 0x0408 Write-only This register always reads as zero. The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Clears the corresponding bit in USBHS_HSTISR.
PAGE 867
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6.34 Host Global Interrupt Set Register Name: Offset: Property: USBHS_HSTIFR 0x040C Write-only This register always reads as zero. The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Sets the corresponding bit in USBHS_HSTISR, which may be useful for test or debug purposes.
PAGE 868
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6.
PAGE 869
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) Value 0 1 Description Cleared when USBHS_HSTIDR.RXRSMIEC= 1. This disables the Downstream Resume interrupt (USBHS_HSTISR.RXRSMI). Set when USBHS_HSTIER.RXRSMIES = 1. This enables the Upstream Resume Received interrupt (USBHS_HSTISR.RXRSMI). Bit 3 – RSMEDIE Downstream Resume Sent Interrupt Enable Value Description 0 Cleared when USBHS_HSTIDR.RSMEDIEC = 1. This disables the Downstream Resume interrupt (USBHS_HSTISR.RSMEDI). 1 Set when USBHS_HSTIER.
PAGE 870
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6.36 Host Global Interrupt Disable Register Name: Offset: Property: USBHS_HSTIDR 0x0414 Write-only This register always reads as zero. The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Clears the corresponding bit in USBHS_HSTIMR.
PAGE 871
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6.37 Host Global Interrupt Enable Register Name: Offset: Property: USBHS_HSTIER 0x0418 Write-only This register always reads as zero. The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Sets the corresponding bit in USBHS_HSTISR.
PAGE 872
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6.
PAGE 873
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6.
PAGE 874
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6.
PAGE 875
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6.
PAGE 876
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6.
PAGE 877
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6.43 Host Pipe x Configuration Register Name: Offset: Reset: Property: USBHS_HSTPIPCFGx 0x0500 + x*0x04 [x=0..9] 0 Read/Write For High-speed Bulk-out Pipe, see ”Host Pipe x Configuration Register (High-speed Bulk-out or High-speed Control Pipe)”.
PAGE 878
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) Value 0 1 2 3 Name SETUP IN OUT Reserved Bits 6:4 – PSIZE[2:0] Pipe Size This field contains the size of each pipe bank. This field is cleared upon sending a USB reset.
PAGE 879
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6.44 Host Pipe x Configuration Register (High-speed Bulk-out or High-speed Control Pipe) Name: Offset: Reset: Property: USBHS_HSTPIPCFGx (HSBOHSCP) 0x0500 + x*0x04 [x=0..9] 0 Read/Write This configuration is relevant only if PTYPE = 0x0 or 0x2 in ”Host Pipe x Configuration Register”.
PAGE 880
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) Value 0 1 2 3 Name CTRL Reserved BLK Reserved Description Control Bulk Bit 10 – AUTOSW Automatic Switch This bit is cleared upon sending a USB reset. Value Description 0 The automatic bank switching is disabled. 1 The automatic bank switching is enabled. Bits 9:8 – PTOKEN[1:0] Pipe Token This field contains the pipe token. Value Name 0 SETUP 1 IN 2 OUT 3 Reserved Bits 6:4 – PSIZE[2:0] Pipe Size This field contains the size of each pipe bank.
PAGE 881
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6.45 Host Pipe x Status Register (Control, Bulk Pipes) Name: Offset: Reset: Property: USBHS_HSTPIPISRx 0x0530 + x*0x04 [x=0..9] 0 Read/Write This register view is relevant only if PTYPE = 0x0 or 0x2 in ”Host Pipe x Configuration Register”.
PAGE 882
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) Value 0 1 2 3 Name BANK0 BANK1 BANK2 Reserved Description Current bank is bank0 Current bank is bank1 Current bank is bank2 Bits 13:12 – NBUSYBK[1:0] Number of Busy Banks This field indicates the number of busy banks. For an OUT pipe, this field indicates the number of busy banks, filled by the user, ready for OUT transfer. When all banks are busy, this triggers a PEP_x interrupt if USBHS_HSTPIPIMRx.NBUSYBKE = 1.
PAGE 883
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) Value 1 Description Set when an error occurs on the current bank of the pipe. This triggers an interrupt if the USBHS_HSTPIPIMR.PERRE bit is set. Refer to the USBHS_HSTPIPERRx register to determine the source of the error. Bit 2 – TXSTPI Transmitted SETUP Interrupt Value Description 0 Cleared when USBHS_HSTPIPICR.TXSTPIC = 1. 1 Set, for control pipes, when the current SETUP bank is free and can be filled.
PAGE 884
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6.46 Host Pipe x Status Register (Interrupt Pipes) Name: Offset: Reset: Property: USBHS_HSTPIPISRx (INTPIPES) 0x0530 + x*0x04 [x=0..9] 0 Read/Write This register view is relevant only if PTYPE = 0x3 in ”Host Pipe x Configuration Register”.
PAGE 885
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) Value 0 1 2 3 Name BANK0 BANK1 BANK2 Reserved Description Current bank is bank0 Current bank is bank1 Current bank is bank2 Bits 13:12 – NBUSYBK[1:0] Number of Busy Banks This field indicates the number of busy banks. For an OUT pipe, this field indicates the number of busy banks, filled by the user, ready for an OUT transfer. When all banks are busy, this triggers a PEP_x interrupt if USBHS_HSTPIPIMRx.NBUSYBKE = 1.
PAGE 886
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) Value 1 Description Set when an error occurs on the current bank of the pipe. This triggers an interrupt if the USBHS_HSTPIPIMR.PERRE bit is set. Refer to the USBHS_HSTPIPERRx register to determine the source of the error. Bit 2 – UNDERFI Underflow Interrupt This bit is set, for an isochronous and interrupt IN/OUT pipe, when an error flow occurs. This triggers an interrupt if UNDERFIE = 1.
PAGE 887
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6.47 Host Pipe x Status Register (Isochronous Pipes) Name: Offset: Reset: Property: USBHS_HSTPIPISRx (ISOPIPES) 0x0530 + x*0x04 [x=0..9] 0 Read/Write This register view is relevant only if PTYPE = 0x1 in ”Host Pipe x Configuration Register”.
PAGE 888
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) Value 0 1 2 3 Name BANK0 BANK1 BANK2 Reserved Description Current bank is bank0 Current bank is bank1 Current bank is bank2 Bits 13:12 – NBUSYBK[1:0] Number of Busy Banks This field indicates the number of busy banks. For an OUT pipe, this field indicates the number of busy banks, filled by the user, ready for an OUT transfer. When all banks are busy, this triggers a PEP_x interrupt if USBHS_HSTPIPIMRx.NBUSYBKE = 1.
PAGE 889
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) Value 1 Description Set when an error occurs on the current bank of the pipe. This triggers an interrupt if the USBHS_HSTPIPIMR.PERRE bit is set. Refer to the USBHS_HSTPIPERRx register to determine the source of the error. Bit 2 – UNDERFI Underflow Interrupt This bit is set, for an isochronous and interrupt IN/OUT pipe, when an error flow occurs. This triggers an interrupt if the UNDERFIE bit = 1.
PAGE 890
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6.48 Host Pipe x Clear Register (Control, Bulk Pipes) Name: Offset: Reset: Property: USBHS_HSTPIPICRx 0x0560 + x*0x04 [x=0..9] 0 Read/Write This register view is relevant only if PTYPE = 0x0 or 0x2 in ”Host Pipe x Configuration Register”. For additional information, see ”Host Pipe x Status Register (Control, Bulk Pipes)”. This register always reads as zero.
PAGE 891
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6.49 Host Pipe x Clear Register (Interrupt Pipes) Name: Offset: Reset: Property: USBHS_HSTPIPICRx (INTPIPES) 0x0560 + x*0x04 [x=0..9] 0 Read/Write This register view is relevant only if PTYPE = 0x3 in ”Host Pipe x Configuration Register”. For additional information, see ”Host Pipe x Status Register (Interrupt Pipes)”. This register always reads as zero.
PAGE 892
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6.50 Host Pipe x Clear Register (Isochronous Pipes) Name: Offset: Reset: Property: USBHS_HSTPIPICRx (ISOPIPES) 0x0560 + x*0x04 [x=0..9] 0 Read/Write This register view is relevant only if PTYPE = 0x1 in ”Host Pipe x Configuration Register”. For additional information, see ”Host Pipe x Status Register (Isochronous Pipes)”. This register always reads as zero.
PAGE 893
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6.51 Host Pipe x Set Register (Control, Bulk Pipes) Name: Offset: Reset: Property: USBHS_HSTPIPIFRx 0x0590 0 Read/Write This register view is relevant only if PTYPE = 0x0 or 0x2 in ”Host Pipe x Configuration Register”. For additional information, see ”Host Pipe x Status Register (Control, Bulk Pipes)”. This register always reads as zero. The following configuration values are valid for all listed bit names of this register: 0: No effect.
PAGE 894
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6.52 Host Pipe x Set Register (Interrupt Pipes) Name: Offset: Reset: Property: USBHS_HSTPIPIFRx (INTPIPES) 0x0590 + x*0x04 [x=0..9] 0 Read/Write This register view is relevant only if PTYPE = 0x3 in ”Host Pipe x Configuration Register”. For additional information, see ”Host Pipe x Status Register (Interrupt Pipes)”. This register always reads as zero.
PAGE 895
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6.53 Host Pipe x Set Register (Isochronous Pipes) Name: Offset: Reset: Property: USBHS_HSTPIPIFRx (ISOPIPES) 0x0590 + x*0x04 [x=0..9] 0 Read/Write This register view is relevant only if PTYPE = 0x1 in ”Host Pipe x Configuration Register”. For additional information, see ”Host Pipe x Status Register (Isochronous Pipes)”. This register always reads as zero.
PAGE 896
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6.54 Host Pipe x Mask Register (Control, Bulk Pipes) Name: Offset: Reset: Property: USBHS_HSTPIPIMRx 0x05C0 + x*0x04 [x=0..9] 0 Read/Write This register view is relevant only if PTYPE = 0x0 or 0x2 in ”Host Pipe x Configuration Register”.
PAGE 897
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 0: Cleared when USBHS_HSTPIPIDR.FIFOCONC = 1. This sends the FIFO data and switches the bank. 1: Set when the current bank is free, at the same time as USBHS_HSTPIPISR.TXOUTI or TXSTPI. For an IN pipe: 0: Cleared when USBHS_HSTPIPIDR.FIFOCONC = 1. This frees the current bank and switches to the next bank. 1: Set when a new IN message is stored in the current bank, at the same time as USBHS_HSTPIPISR.RXINI.
PAGE 898
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) Bit 1 – TXOUTE Transmitted OUT Data Interrupt Enable Value Description 0 Cleared when USBHS_HSTPIPIDR.TXOUTEC = 1. This disables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.TXOUTE). 1 Set when USBHS_HSTPIPIER.TXOUTES = 1. This enables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.TXOUTE). Bit 0 – RXINE Received IN Data Interrupt Enable Value Description 0 Cleared when USBHS_HSTPIPIDR.RXINEC = 1.
PAGE 899
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6.55 Host Pipe x Mask Register (Interrupt Pipes) Name: Offset: Reset: Property: USBHS_HSTPIPIMRx (INTPIPES) 0x05C0 + x*0x04 [x=0..9] 0 Read/Write This register view is relevant only if PTYPE = 0x3 in ”Host Pipe x Configuration Register”.
PAGE 900
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 0: Cleared when USBHS_HSTPIPIDR.FIFOCONC = 1. This sends the FIFO data and switches the bank. 1: Set when the current bank is free, at the same time as USBHS_HSTPIPISR.TXOUTI or TXSTPI. For IN pipes: 0: Cleared when USBHS_HSTPIPIDR.FIFOCONC = 1. This frees the current bank and switches to the next bank. 1: Set when a new IN message is stored in the current bank, at the same time as USBHS_HSTPIPISR.RXINI.
PAGE 901
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) Bit 1 – TXOUTE Transmitted OUT Data Interrupt Enable Value Description 0 Cleared when USBHS_HSTPIPIDR.TXOUTEC = 1. This disables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.TXOUTE). 1 Set when USBHS_HSTPIPIER.TXOUTES = 1. This enables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.TXOUTE). Bit 0 – RXINE Received IN Data Interrupt Enable Value Description 0 Cleared when USBHS_HSTPIPIDR.RXINEC = 1.
PAGE 902
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6.56 Host Pipe x Mask Register (Isochronous Pipes) Name: Offset: Reset: Property: USBHS_HSTPIPIMRx (ISOPIPES) 0x05C0 + x*0x04 [x=0..9] 0 Read/Write This register view is relevant only if PTYPE = 0x1 in ”Host Pipe x Configuration Register”.
PAGE 903
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 0: Cleared when USBHS_HSTPIPIDR.FIFOCONC = 1. This sends the FIFO data and switches the bank. 1: Set when the current bank is free, at the same time as USBHS_HSTPIPISR.TXOUTI or TXSTPI. For IN pipes: 0: Cleared when USBHS_HSTPIPIDR.FIFOCONC = 1. This frees the current bank and switches to the next bank. 1: Set when a new IN message is stored in the current bank, at the same time as USBHS_HSTPIPISR.RXINI.
PAGE 904
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) Bit 1 – TXOUTE Transmitted OUT Data Interrupt Enable Value Description 0 Cleared when USBHS_HSTPIPIDR.TXOUTEC = 1. This disables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.TXOUTE). 1 Set when USBHS_HSTPIPIER.TXOUTES = 1. This enables the Transmitted IN Data interrupt (USBHS_HSTPIPIMR.TXOUTE). Bit 0 – RXINE Received IN Data Interrupt Enable Value Description 0 Cleared when USBHS_HSTPIPIDR.RXINEC = 1.
PAGE 905
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6.57 Host Pipe x Disable Register (Control, Bulk Pipes) Name: Offset: Reset: Property: USBHS_HSTPIPIDRx 0x0620 + x*0x04 [x=0..9] 0 Read/Write This register view is relevant only if PTYPE = 0x0 or 0x2 in ”Host Pipe x Configuration Register”. For additional information, see ”Host Pipe x Mask Register (Control, Bulk Pipes)”. This register always reads as zero.
PAGE 906
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) Bit 1 – TXOUTEC Transmitted OUT Data Interrupt Disable Bit 0 – RXINEC Received IN Data Interrupt Disable © 2019 Microchip Technology Inc.
PAGE 907
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6.58 Host Pipe x Disable Register (Interrupt Pipes) Name: Offset: Reset: Property: USBHS_HSTPIPIDRx (INTPIPES) 0x0620 + x*0x04 [x=0..9] 0 Read/Write This register view is relevant only if PTYPE = 0x3 in ”Host Pipe x Configuration Register”. For additional information, see ”Host Pipe x Mask Register (Interrupt Pipes)”. This register always reads as zero.
PAGE 908
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) Bit 1 – TXOUTEC Transmitted OUT Data Interrupt Disable Bit 0 – RXINEC Received IN Data Interrupt Disable © 2019 Microchip Technology Inc.
PAGE 909
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6.59 Host Pipe x Disable Register (Isochronous Pipes) Name: Offset: Reset: Property: USBHS_HSTPIPIDRx (ISOPIPES) 0x0620 + x*0x04 [x=0..9] 0 Read/Write This register view is relevant only if PTYPE = 0x1 in ”Host Pipe x Configuration Register”. For additional information, see ”Host Pipe x Mask Register (Isochronous Pipes)”. This register always reads as zero.
PAGE 910
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) Bit 1 – TXOUTEC Transmitted OUT Data Interrupt Disable Bit 0 – RXINEC Received IN Data Interrupt Disable © 2019 Microchip Technology Inc.
PAGE 911
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6.60 Host Pipe x Enable Register (Control, Bulk Pipes) Name: Offset: Reset: Property: USBHS_HSTPIPIERx 0x05F0 + x*0x04 [x=0..9] 0 Read/Write This register view is relevant only if PTYPE = 0x0 or 0x2 in ”Host Pipe x Configuration Register”. For additional information, see ”Host Pipe x Mask Register (Control, Bulk Pipes)”. This register always reads as zero.
PAGE 912
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) Bit 1 – TXOUTES Transmitted OUT Data Interrupt Enable Bit 0 – RXINES Received IN Data Interrupt Enable © 2019 Microchip Technology Inc.
PAGE 913
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6.61 Host Pipe x Enable Register (Interrupt Pipes) Name: Offset: Reset: Property: USBHS_HSTPIPIERx (INTPIPES) 0x05F0 + x*0x04 [x=0..9] 0 Read/Write This register view is relevant only if PTYPE = 0x3 in ”Host Pipe x Configuration Register”. For additional information, see ”Host Pipe x Mask Register (Interrupt Pipes)”. This register always reads as zero.
PAGE 914
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) Bit 1 – TXOUTES Transmitted OUT Data Interrupt Enable Bit 0 – RXINES Received IN Data Interrupt Enable © 2019 Microchip Technology Inc.
PAGE 915
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6.62 Host Pipe x Enable Register (Isochronous Pipes) Name: Offset: Reset: Property: USBHS_HSTPIPIERx (ISOPIPES) 0x05F0 + x*0x04 [x=0..9] 0 Read/Write This register view is relevant only if PTYPE = 0x1 in ”Host Pipe x Configuration Register”. For additional information, see ”Host Pipe x Mask Register (Isochronous Pipes)”. This register always reads as zero.
PAGE 916
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) Bit 1 – TXOUTES Transmitted OUT Data Interrupt Enable Bit 0 – RXINES Received IN Data Interrupt Enable © 2019 Microchip Technology Inc.
PAGE 917
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6.63 Host Pipe x IN Request Register Name: Offset: Reset: Property: Bit USBHS_HSTPIPINRQx 0x0650 + x*0x04 [x=0..
PAGE 918
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6.64 Host Pipe x Error Register Name: Offset: Reset: Property: USBHS_HSTPIPERRx 0x0680 + x*0x04 [x=0..9] 0 Read/Write Writing a zero in a bit/field in this register clears the bit/field. Writing a one has no effect.
PAGE 919
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) Value 0 1 Description No Data Toggle error occurred since last clear of this bit. This bit is automatically set when a Data Toggle error has been detected. © 2019 Microchip Technology Inc.
PAGE 920
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6.65 Host DMA Channel x Next Descriptor Address Register Name: Offset: Reset: Property: USBHS_HSTDMANXTDSCx 0x0700 + (x-1)*0x10 [x=1..
PAGE 921
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6.66 Host DMA Channel x Address Register Name: Offset: Reset: Property: USBHS_HSTDMAADDRESSx 0x0704 + x*0x10 [x=0..
PAGE 922
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6.67 Host DMA Channel x Control Register Name: Offset: Reset: Property: USBHS_HSTDMACONTROLx 0x0708 + x*0x10 [x=0..
PAGE 923
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) Value 0 1 Description Completion of a USBHS device-initiated buffer transfer does not trigger any interrupt at USBHS_HSTDMASTATUSx.END_TR_ST rising. An interrupt is sent after the buffer transfer is complete, if the USBHS device has ended the buffer transfer.
PAGE 924
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) 39.6.68 Host DMA Channel x Status Register Name: Offset: Reset: Property: USBHS_HSTDMASTATUSx 0x070C + x*0x10 [x=0..
PAGE 925
SAM E70/S70/V70/V71 Family USB High-Speed Interface (USBHS) Bit 1 – CHANN_ACT Channel Active Status When a packet transfer is ended, this bit is automatically reset. When a packet transfer cannot be completed due to an END_BF_ST, this flag stays set during the next channel descriptor load (if any) and potentially until completion of a USBHS packet transfer, if allowed by the new descriptor. Value Description 0 The DMA channel is no longer trying to source the packet data.
PAGE 926
SAM E70/S70/V70/V71 Family High-Speed Multimedia Card Interface (HSMCI) 40. 40.1 High-Speed Multimedia Card Interface (HSMCI) Description The High Speed Multimedia Card Interface (HSMCI) supports the MultiMedia Card (MMC) Specification V4.3, the SD Memory Card Specification V2.0, the SDIO V2.0 specification and CE-ATA V1.1.
PAGE 927
SAM E70/S70/V70/V71 Family High-Speed Multimedia Card Interface (HSMCI) 40.3 Block Diagram Figure 40-1. Block Diagram (4-bit configuration) APB Bridge DMAC APB MCCK(1) MCCDA(1) PMC MCK MCDA0(1) HSMCI Interface PIO MCDA1(1) MCDA2(1) MCDA3(1) Interrupt Control HSMCI Interrupt Note: 1. When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to HSMCIx_CDA, MCDAy to HSMCIx_DAy. 40.4 Application Block Diagram Figure 40-2.
PAGE 928
SAM E70/S70/V70/V71 Family High-Speed Multimedia Card Interface (HSMCI) 40.5 Pin Name List Table 40-1. I/O Lines Description for 4-bit Configuration Pin Name(1) Pin Description Type(2) Comments MCCDA Command/response I/O/PP/OD CMD of an MMC or SDCard/SDIO MCCK Clock O CLK of an MMC or SD Card/SDIO MCDA0–MCDA3 Data 0..3 of Slot A I/O/PP DAT[0..3] of an MMC DAT[0..3] of an SD Card/SDIO Note: 1.
PAGE 929
SAM E70/S70/V70/V71 Family High-Speed Multimedia Card Interface (HSMCI) ...........continued Pin Number Name Type(1) Description HSMCI Pin Name(2) (Slot z) 4 VDD S Supply voltage VDD 5 CLK O Clock MCCK 6 VSS2 S Supply voltage ground VSS 7 DAT[0] I/O/PP Data 0 MCDz0 8 DAT[1] I/O/PP Data 1 MCDz1 9 DAT[2] I/O/PP Data 2 MCDz2 Note: 1. I: Input, O: Output, PP: Push/Pull, OD: Open Drain, S: Supply 2.
PAGE 930
SAM E70/S70/V70/V71 Family High-Speed Multimedia Card Interface (HSMCI) ...........continued Pin Number Name Type(1) Description HSMCI Pin Name(2) (Slot z) 6 VSS2 S Supply voltage ground VSS 7 DAT[0] I/O/PP Data line Bit 0 MCDz0 8 DAT[1] I/O/PP Data line Bit 1 or Interrupt MCDz1 9 DAT[2] I/O/PP Data line Bit 2 MCDz2 Note: 1. I: input, O: output, PP: Push Pull, OD: Open Drain. 2.
PAGE 931
SAM E70/S70/V70/V71 Family High-Speed Multimedia Card Interface (HSMCI) • Block-oriented commands—These commands send a data block succeeded by CRC bits. Both read and write operations allow either single or multiple block transmission. A multiple block transmission is terminated when a stop command follows on the CMD line similarly to the sequential read or when a multiple block transmission has a predefined block count (see “Data Transfer Operation”).
PAGE 932
SAM E70/S70/V70/V71 Family High-Speed Multimedia Card Interface (HSMCI) While the card maintains a busy indication (at the end of a STOP_TRANSMISSION command CMD12, for example), a new command shall not be sent. The NOTBUSY flag in the Status Register (HSMCI_SR) is asserted when the card releases the busy indication. If the command requires a response, it can be read in the HSMCI Response Register (HSMCI_RSPR). The response size can be from 48 bits up to 136 bits depending on the command.
PAGE 933
SAM E70/S70/V70/V71 Family High-Speed Multimedia Card Interface (HSMCI) Figure 40-7.
PAGE 934
SAM E70/S70/V70/V71 Family High-Speed Multimedia Card Interface (HSMCI) 40.8.2 Data Transfer Operation The High Speed MultiMedia Card allows several read/write operations (single block, multiple blocks, stream, etc.). These kinds of transfer can be selected setting the Transfer Type (TRTYP) field in the HSMCI Command Register (HSMCI_CMDR). In all cases, the block length (BLKLEN field) must be defined either in the HSMCI Mode Register (HSMCI_MR) or in the HSMCI Block Register (HSMCI_BLKR).
PAGE 935
SAM E70/S70/V70/V71 Family High-Speed Multimedia Card Interface (HSMCI) Figure 40-8.
PAGE 936
SAM E70/S70/V70/V71 Family High-Speed Multimedia Card Interface (HSMCI) The flowchart, Write Functional Flow Diagram, shows how to write a single block with or without use of DMA facilities. Polling or interrupt method can be used to wait for the end of write according to the contents of the HSMCI Interrupt Mask Register (HSMCI_IMR). Figure 40-9.
PAGE 937
SAM E70/S70/V70/V71 Family High-Speed Multimedia Card Interface (HSMCI) Figure 40-10.
PAGE 938
SAM E70/S70/V70/V71 Family High-Speed Multimedia Card Interface (HSMCI) 3. 4. 5. 6. Program the block length in the HSMCI Configuration Register with block_length value. Configure the fields of the HSMCI_MR as follows: a. Program FBYTE to one when the transfer is not multiple of 4, zero otherwise. Issue a WRITE_SINGLE_BLOCK command writing HSMCI_ARGR then HSMCI_CMDR. Program the DMA Controller. a. Read the Channel Status Register to choose an available (disabled) channel. b.
PAGE 939
SAM E70/S70/V70/V71 Family High-Speed Multimedia Card Interface (HSMCI) 40.9 SD/SDIO Card Operation The High Speed MultiMedia Card Interface allows processing of SD Memory (Secure Digital Memory Card) and SDIO (SD Input Output) Card commands. SD/SDIO cards are based on the MultiMedia Card (MMC) format, but are physically slightly thicker and feature higher data transfer rates, a lock switch on the side to prevent accidental overwriting and security features.
PAGE 940
SAM E70/S70/V70/V71 Family High-Speed Multimedia Card Interface (HSMCI) 40.10.1 Executing an ATA Polling Command 1. 2. 3. 4. Issue READ_DMA_EXT with RW_MULTIPLE_REGISTER (CMD60) for 8 KB of DATA. Read the ATA status register until DRQ is set. Issue RW_MULTIPLE_BLOCK (CMD61) to transfer DATA. Read the ATA status register until DRQ && BSY are configured to 0. 40.10.2 Executing an ATA Interrupt Command 1. 2. 3.
PAGE 941
SAM E70/S70/V70/V71 Family High-Speed Multimedia Card Interface (HSMCI) 3. 4. 5. 6. Issue the Boot Operation Request command by writing to the HSMCI_CMDR with SPCMD field set to BOOTREQ, TRDIR set to READ and TRCMD set to “start data transfer”. The BOOT_ACK field located in the HSMCI_CMDR must be set to one, if the BOOT_ACK field of the MMC device located in the Extended CSD register is set to one. Host processor can copy boot data sequentially as soon as the RXRDY flag is asserted.
PAGE 942
SAM E70/S70/V70/V71 Family High-Speed Multimedia Card Interface (HSMCI) Figure 40-12. XFRDONE During a Write Access CMD line HSMCI write CMD Card response CMDRDY flag The CMDRDY flag is released 8 tbit after the end of the card response. D0 is tied by the card D0 is released D0 1st Block Last Block 1st Block Last Block Data bus - D0 NOTBUSY flag XFRDONE flag 40.
PAGE 943
SAM E70/S70/V70/V71 Family High-Speed Multimedia Card Interface (HSMCI) 40.14 Register Summary Offset Name 0x00 HSMCI_CR 0x00 HSMCI_FIFOx [x=0..255] 0x04 HSMCI_MR 0x08 HSMCI_DTOR 0x0C HSMCI_SDCR 0x10 HSMCI_ARGR 0x14 HSMCI_CMDR 0x18 HSMCI_BLKR 0x1C HSMCI_CSTOR 0x20 HSMCI_RSPR 0x24 ... 0x2F Reserved 0x30 HSMCI_RDR 0x34 HSMCI_TDR 0x38 ... 0x3F Reserved Bit Pos.
PAGE 944
SAM E70/S70/V70/V71 Family High-Speed Multimedia Card Interface (HSMCI) ...........continued Offset Name 0x40 HSMCI_SR 0x44 HSMCI_IER 0x48 HSMCI_IDR 0x4C HSMCI_IMR 0x50 HSMCI_DMA 0x54 HSMCI_CFG 0x58 ... 0xE3 Reserved 0xE4 0xE8 HSMCI_WPMR HSMCI_WPSR Bit Pos.
PAGE 945
SAM E70/S70/V70/V71 Family High-Speed Multimedia Card Interface (HSMCI) 40.14.1 HSMCI Control Register Name: Offset: Property: Bit HSMCI_CR 0x00 Write-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 SWRST 6 5 4 3 PWSDIS 2 PWSEN 1 MCIDIS 0 MCIEN Access Reset Bit Access Reset Bit Access Reset Bit Access Reset Bit 7 – SWRST Software Reset Value Description 0 No effect. 1 Resets the HSMCI.
PAGE 946
SAM E70/S70/V70/V71 Family High-Speed Multimedia Card Interface (HSMCI) 40.14.2 HSMCI Mode Register Name: Offset: Reset: Property: HSMCI_MR 0x04 0x0 Read/Write This register can only be written if the WPEN bit is cleared in the HSMCI Write Protection Mode Register.
PAGE 947
SAM E70/S70/V70/V71 Family High-Speed Multimedia Card Interface (HSMCI) Bit 11 – RDPROOF Read Proof Enable Enabling Read Proof allows to stop the HSMCI Clock during read access if the internal FIFO is full. This will guarantee data integrity, not bandwidth. Value Description 0 Disables Read Proof. 1 Enables Read Proof. Bits 10:8 – PWSDIV[2:0] Power Saving Divider High Speed MultiMedia Card Interface clock is divided by 2(PWSDIV) + 1 when entering Power Saving Mode.
PAGE 948
SAM E70/S70/V70/V71 Family High-Speed Multimedia Card Interface (HSMCI) 40.14.3 HSMCI Data Timeout Register Name: Offset: Reset: Property: HSMCI_DTOR 0x08 0x0 Read/Write This register can only be written if the WPEN bit is cleared in the HSMCI Write Protection Mode Register.
PAGE 949
SAM E70/S70/V70/V71 Family High-Speed Multimedia Card Interface (HSMCI) 40.14.4 HSMCI SDCard/SDIO Register Name: Offset: Reset: Property: HSMCI_SDCR 0x0C 0x0 Read/Write This register can only be written if the WPEN bit is cleared in the HSMCI Write Protection Mode Register.
PAGE 950
SAM E70/S70/V70/V71 Family High-Speed Multimedia Card Interface (HSMCI) 40.14.
PAGE 951
SAM E70/S70/V70/V71 Family High-Speed Multimedia Card Interface (HSMCI) 40.14.6 HSMCI Command Register Name: Offset: Property: HSMCI_CMDR 0x14 Write-only This register is write-protected while CMDRDY is 0 in HSMCI_SR. If an Interrupt command is sent, this register is only writable by an interrupt response (field SPCMD). This means that the current command execution cannot be interrupted or modified.
PAGE 952
SAM E70/S70/V70/V71 Family High-Speed Multimedia Card Interface (HSMCI) Bit 18 – TRDIR Transfer Direction 0 (WRITE): Write. 1 (READ): Read. Bits 17:16 – TRCMD[1:0] Transfer Command Value Name 0 NO_DATA 1 START_DATA 2 STOP_DATA 3 Reserved Description No data transfer Start data transfer Stop data transfer Reserved Bit 12 – MAXLAT Max Latency for Command to Response 0 (5): 5-cycle max latency. 1 (64): 64-cycle max latency. Bit 11 – OPDCMD Open Drain Command 0 (PUSHPULL): Push pull command.
PAGE 953
SAM E70/S70/V70/V71 Family High-Speed Multimedia Card Interface (HSMCI) 40.14.
PAGE 954
SAM E70/S70/V70/V71 Family High-Speed Multimedia Card Interface (HSMCI) 40.14.8 HSMCI Completion Signal Timeout Register Name: Offset: Reset: Property: HSMCI_CSTOR 0x1C 0x0 Read/Write This register can only be written if the WPEN bit is cleared in the HSMCI Write Protection Mode Register.
PAGE 955
SAM E70/S70/V70/V71 Family High-Speed Multimedia Card Interface (HSMCI) 40.14.9 HSMCI Response Register Name: Offset: Reset: Property: HSMCI_RSPR 0x20 0x0 Read-only Note: 1. The response register can be read by N accesses at the same HSMCI_RSPR or at consecutive addresses (0x20 to 0x2C). N depends on the size of the response.
PAGE 956
SAM E70/S70/V70/V71 Family High-Speed Multimedia Card Interface (HSMCI) 40.14.
PAGE 957
SAM E70/S70/V70/V71 Family High-Speed Multimedia Card Interface (HSMCI) 40.14.11 HSMCI Transmit Data Register Name: Offset: Property: Bit 31 HSMCI_TDR 0x34 Write-only 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 DATA[31:24] Access Reset Bit 23 22 21 20 DATA[23:16] Access Reset Bit 15 14 13 12 DATA[15:8] Access Reset Bit 7 6 5 4 DATA[7:0] Access Reset Bits 31:0 – DATA[31:0] Data to Write © 2019 Microchip Technology Inc.
PAGE 958
SAM E70/S70/V70/V71 Family High-Speed Multimedia Card Interface (HSMCI) 40.14.
PAGE 959
SAM E70/S70/V70/V71 Family High-Speed Multimedia Card Interface (HSMCI) Value 1 Description Command Register is ready to operate and the data bus is in the idle state. Bit 26 – FIFOEMPTY FIFO empty flag Value Description 0 FIFO contains at least one byte. 1 FIFO is empty. Bit 24 – BLKOVRE DMA Block Overrun Error (cleared on read) Value Description 0 No error. 1 A new block of data is received and the DMA controller has not started to move the current pending block, a block overrun is raised.
PAGE 960
SAM E70/S70/V70/V71 Family High-Speed Multimedia Card Interface (HSMCI) Value 0 1 Description No completion signal received since last status read operation. The device has issued a command completion signal on the command line. Bit 12 – SDIOWAIT SDIO Read Wait Operation Status Value Description 0 Normal Bus operation. 1 The data bus has entered IO wait state. Bit 8 – SDIOIRQA SDIO Interrupt for Slot A (cleared on read) Value Description 0 No interrupt detected on SDIO Slot A.
PAGE 961
SAM E70/S70/V70/V71 Family High-Speed Multimedia Card Interface (HSMCI) Value 0 1 Description A command is in progress. The last command has been sent. © 2019 Microchip Technology Inc.
PAGE 962
SAM E70/S70/V70/V71 Family High-Speed Multimedia Card Interface (HSMCI) 40.14.13 HSMCI Interrupt Enable Register Name: Offset: Property: HSMCI_IER 0x44 Write-only The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Enables the corresponding interrupt.
PAGE 963
SAM E70/S70/V70/V71 Family High-Speed Multimedia Card Interface (HSMCI) Bit 17 – RDIRE Response Direction Error Interrupt Enable Bit 16 – RINDE Response Index Error Interrupt Enable Bit 13 – CSRCV Completion Signal Received Interrupt Enable Bit 12 – SDIOWAIT SDIO Read Wait Operation Status Interrupt Enable Bit 8 – SDIOIRQA SDIO Interrupt for Slot A Interrupt Enable Bit 5 – NOTBUSY Data Not Busy Interrupt Enable Bit 4 – DTIP Data Transfer in Progress Interrupt Enable Bit 3 – BLKE Data Block Ended Interrupt E
PAGE 964
SAM E70/S70/V70/V71 Family High-Speed Multimedia Card Interface (HSMCI) 40.14.14 HSMCI Interrupt Disable Register Name: Offset: Property: HSMCI_IDR 0x48 Write-only The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Disables the corresponding interrupt.
PAGE 965
SAM E70/S70/V70/V71 Family High-Speed Multimedia Card Interface (HSMCI) Bit 17 – RDIRE Response Direction Error Interrupt Disable Bit 16 – RINDE Response Index Error Interrupt Disable Bit 13 – CSRCV Completion Signal received interrupt Disable Bit 12 – SDIOWAIT SDIO Read Wait Operation Status Interrupt Disable Bit 8 – SDIOIRQA SDIO Interrupt for Slot A Interrupt Disable Bit 5 – NOTBUSY Data Not Busy Interrupt Disable Bit 4 – DTIP Data Transfer in Progress Interrupt Disable Bit 3 – BLKE Data Block Ended Inte
PAGE 966
SAM E70/S70/V70/V71 Family High-Speed Multimedia Card Interface (HSMCI) 40.14.15 HSMCI Interrupt Mask Register Name: Offset: Reset: Property: HSMCI_IMR 0x4C 0x0 Read-only The following configuration values are valid for all listed bit names of this register: 0: The corresponding interrupt is not enabled. 1: The corresponding interrupt is enabled.
PAGE 967
SAM E70/S70/V70/V71 Family High-Speed Multimedia Card Interface (HSMCI) Bit 18 – RCRCE Response CRC Error Interrupt Mask Bit 17 – RDIRE Response Direction Error Interrupt Mask Bit 16 – RINDE Response Index Error Interrupt Mask Bit 13 – CSRCV Completion Signal Received Interrupt Mask Bit 12 – SDIOWAIT SDIO Read Wait Operation Status Interrupt Mask Bit 8 – SDIOIRQA SDIO Interrupt for Slot A Interrupt Mask Bit 5 – NOTBUSY Data Not Busy Interrupt Mask Bit 4 – DTIP Data Transfer in Progress Interrupt Mask Bit 3
PAGE 968
SAM E70/S70/V70/V71 Family High-Speed Multimedia Card Interface (HSMCI) 40.14.16 HSMCI DMA Configuration Register Name: Offset: Reset: Property: HSMCI_DMA 0x50 0x0 Read/Write This register can only be written if the WPEN bit is cleared in the HSMCI Write Protection Mode Register.
PAGE 969
SAM E70/S70/V70/V71 Family High-Speed Multimedia Card Interface (HSMCI) 40.14.17 HSMCI Configuration Register Name: Offset: Reset: Property: HSMCI_CFG 0x54 0x0 Read/Write This register can only be written if the WPEN bit is cleared in the HSMCI Write Protection Mode Register.
PAGE 970
SAM E70/S70/V70/V71 Family High-Speed Multimedia Card Interface (HSMCI) 40.14.
PAGE 971
SAM E70/S70/V70/V71 Family High-Speed Multimedia Card Interface (HSMCI) 40.14.
PAGE 972
SAM E70/S70/V70/V71 Family High-Speed Multimedia Card Interface (HSMCI) 40.14.20 HSMCI FIFOx Memory Aperture Name: Offset: Reset: Property: Bit 31 HSMCI_FIFOx [x=0..
PAGE 973
SAM E70/S70/V70/V71 Family Serial Peripheral Interface (SPI) 41. Serial Peripheral Interface (SPI) 41.1 Description The Serial Peripheral Interface (SPI) circuit is a synchronous serial data link that provides communication with external devices in Master or Slave mode. It also enables communication between processors if an external processor is connected to the system. The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to other SPIs.
PAGE 974
SAM E70/S70/V70/V71 Family Serial Peripheral Interface (SPI) 41.3 Block Diagram Figure 41-1. Block Diagram Bus clock PMC 41.4 Peripheral clock AHB Matrix DMA Peripheral bridge Trigger events SPI Application Block Diagram Figure 41-2. Application Block Diagram: Single Master/Multiple Slave Implementation SPI Master SPCK SPCK MISO MISO MOSI MOSI NPCS0 NSS SPCK NPCS1 NPCS2 Slave 0 MISO NC Slave 1 MOSI NPCS3 NSS SPCK MISO Slave 2 MOSI NSS © 2019 Microchip Technology Inc.
PAGE 975
SAM E70/S70/V70/V71 Family Serial Peripheral Interface (SPI) 41.5 Signal Description Table 41-1. Signal Description Pin Name 41.6 41.6.
PAGE 976
SAM E70/S70/V70/V71 Family Serial Peripheral Interface (SPI) 41.7.2 Data Transfer Four combinations of polarity and phase are available for data transfers. The clock polarity is programmed with the CPOL bit in the SPI Chip Select registers (SPI_CSRx). The clock phase is programmed with the NCPHA bit. These two parameters determine the edges of the clock signal on which data is driven and sampled.
PAGE 977
SAM E70/S70/V70/V71 Family Serial Peripheral Interface (SPI) Figure 41-4. SPI Transfer Format (NCPHA = 0, 8 bits per transfer) 1 SPCK cycle (for reference) 2 3 4 5 7 6 8 SPCK (CPOL = 0) SPCK (CPOL = 1) MOSI (from master) MISO (from slave) * MSB 6 5 4 3 2 1 MSB 6 5 4 3 2 1 LSB LSB NSS (to slave) * Not defined. 41.7.3 Master Mode Operations When configured in Master mode, the SPI operates on the clock generated by the internal programmable baud rate generator.
PAGE 978
SAM E70/S70/V70/V71 Family Serial Peripheral Interface (SPI) Figure 41-5. TDRE and TXEMPTY Flag Behavior Write SPI_CR.SPIEN =1 Write SPI_TDR TDRE Write SPI_TDR Write SPI_TDR automatic set TDR loaded in shifter automatic set TDR loaded in shifter automatic set TDR loaded in shifter TXEMPTY Transfer Transfer DLYBCT Transfer DLYBCT DLYBCT The transfer of received data from the internal shift register to SPI_RDR is indicated by the Receive Data Register Full (RDRF) bit in SPI_SR.
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SAM E70/S70/V70/V71 Family Serial Peripheral Interface (SPI) 41.7.3.1 Master Mode Block Diagram Figure 41-6. Master Mode Block Diagram SPI_CSRx SCBR Baud Rate Generator Peripheral clock SPCK SPI Clock SPI_CSRx BITS NCPHA CPOL LSB MISO SPI_RDR RDRF OVRES RD MSB Shift Register MOSI SPI_TDR TD TDRE SPI_CSRx SPI_RDR CSAAT PCS PS NPCSx PCSDEC SPI_MR PCS 0 Current Peripheral SPI_TDR PCS NPCS0 1 MSTR MODF NPCS0 MODFDIS © 2019 Microchip Technology Inc.
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SAM E70/S70/V70/V71 Family Serial Peripheral Interface (SPI) 41.7.3.2 Master Mode Flow Diagram Figure 41-7.
PAGE 981
SAM E70/S70/V70/V71 Family Serial Peripheral Interface (SPI) The figure below shows the behavior of Transmit Data Register Empty (TDRE), Receive Data Register (RDRF) and Transmission Register Empty (TXEMPTY) status flags within SPI_SR during an 8-bit data transfer in Fixed mode without the DMA involved. Figure 41-8.
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SAM E70/S70/V70/V71 Family Serial Peripheral Interface (SPI) Figure 41-9. Programmable Delays Chip Select 1 Chip Select 2 SPCK DLYBCS DLYBS DLYBCT DLYBCT Related Links 58. Electrical Characteristics for SAM V70/V71 41.7.3.5 Peripheral Selection The serial peripherals are selected through the assertion of the NPCS0 to NPCS3 signals. By default, all NPCS signals are high before and after each transfer. • • Fixed Peripheral Select Mode: SPI exchanges data with only one peripheral.
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SAM E70/S70/V70/V71 Family Serial Peripheral Interface (SPI) 41.7.3.7 Peripheral Chip Select Decoding The user can program the SPI to operate with up to 15 slave peripherals by decoding the four chip select lines, NPCS0 to NPCS3 with an external decoder/demultiplexer (see figure below). This can be enabled by setting SPI_MR.PCSDEC. When operating without decoding, the SPI makes sure that in any case only one chip select line is activated, i.e., one NPCS line driven low at a time.
PAGE 984
SAM E70/S70/V70/V71 Family Serial Peripheral Interface (SPI) remains active. To deassert the chip select line at the end of the transfer, the Last Transfer (LASTXFER) bit in SPI_CR must be set after writing the last data to transmit into SPI_TDR. 41.7.3.9 Peripheral Deselection with DMA DMA provides faster reloads of SPI_TDR compared to software. However, depending on the system activity, it is not guaranteed that SPI_TDR is written with the next data before the end of the current transfer.
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SAM E70/S70/V70/V71 Family Serial Peripheral Interface (SPI) Figure 41-11. Peripheral Deselection CSAAT = 0 and CSNAAT = 0 TDRE CSAAT = 1 and CSNAAT= 0 / 1 DLYBCT NPCS[0..n] DLYBCT A A A A DLYBCS A DLYBCS PCS = A PCS = A Write SPI_TDR TDRE DLYBCT DLYBCT A NPCS[0..n] A A A DLYBCS A DLYBCS PCS=A PCS = A Write SPI_TDR TDRE DLYBCT DLYBCT NPCS[0..
PAGE 986
SAM E70/S70/V70/V71 Family Serial Peripheral Interface (SPI) are processed following a phase and a polarity defined respectively by the NCPHA and CPOL bits in SPI_CSR0. Note that the fields BITS, CPOL and NCPHA of the other chip select registers (SPI_CSR1...SPI_CSR3) have no effect when the SPI is programmed in Slave mode. The bits are shifted out on the MISO line and sampled on the MOSI line. Note: For more information on SPI_CSRx.BITS, see the note in section SPI Chip Select Register.
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SAM E70/S70/V70/V71 Family Serial Peripheral Interface (SPI) • SPI Control Register The following registers are write-protected when WPITEN is set in SPI_WPMR: • • SPI Interrupt Enable Register SPI Interrupt Disable Register © 2019 Microchip Technology Inc.
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SAM E70/S70/V70/V71 Family Serial Peripheral Interface (SPI) 41.8 Register Summary Offset Name 0x00 SPI_CR 0x04 0x08 0x0C 0x10 SPI_MR SPI_RDR SPI_TDR SPI_SR 0x14 SPI_IER 0x18 SPI_IDR 0x1C SPI_IMR 0x20 ... 0x2F Reserved 0x30 0x34 0x38 SPI_CSR0 SPI_CSR1 SPI_CSR2 0x3C SPI_CSR3 0x40 ... 0xE3 Reserved Bit Pos.
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SAM E70/S70/V70/V71 Family Serial Peripheral Interface (SPI) ...........continued Offset Name 0xE4 SPI_WPMR 0xE8 SPI_WPSR Bit Pos. 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 © 2019 Microchip Technology Inc.
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SAM E70/S70/V70/V71 Family Serial Peripheral Interface (SPI) 41.8.1 SPI Control Register Name: Offset: Reset: Property: SPI_CR 0x00 – Write-only This register can only be written if the WPCREN bit is cleared in the SPI Write Protection Mode Register.
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SAM E70/S70/V70/V71 Family Serial Peripheral Interface (SPI) Value 0 1 Description No effect. Enables the SPI to transfer and receive data. © 2019 Microchip Technology Inc.
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SAM E70/S70/V70/V71 Family Serial Peripheral Interface (SPI) 41.8.2 SPI Mode Register Name: Offset: Reset: Property: SPI_MR 0x04 0x0 Read/Write This register can only be written if the WPEN bit is cleared in theSPI Write Protection Mode Register .
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SAM E70/S70/V70/V71 Family Serial Peripheral Interface (SPI) Value 0 1 Description No Effect. In Master mode, a transfer can be initiated regardless of SPI_RDR state. In Master mode, a transfer can start only if SPI_RDR is empty, i.e., does not contain any unread data. This mode prevents overrun error in reception.
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SAM E70/S70/V70/V71 Family Serial Peripheral Interface (SPI) 41.8.
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SAM E70/S70/V70/V71 Family Serial Peripheral Interface (SPI) 41.8.
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SAM E70/S70/V70/V71 Family Serial Peripheral Interface (SPI) 41.8.5 SPI Status Register Name: Offset: Reset: Property: Bit SPI_SR 0x10 0x00000000 Read-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SPIENS R 0 15 14 13 12 SFERR R 0 11 10 UNDES R 0 9 TXEMPTY R 0 8 NSSR R 0 7 6 5 4 3 OVRES R 0 2 MODF R 0 1 TDRE R 0 0 RDRF R 0 Access Reset Bit Access Reset Bit Access Reset Bit Access Reset Bit 16 – SPIENS SPI Enable Status Value Description 0 SPI is disabled.
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SAM E70/S70/V70/V71 Family Serial Peripheral Interface (SPI) Bit 3 – OVRES Overrun Error Status (cleared on read) An overrun occurs when SPI_RDR is loaded at least twice from the internal shift register since the last read of SPI_RDR. Value Description 0 No overrun has been detected since the last read of SPI_SR. 1 An overrun has occurred since the last read of SPI_SR. Bit 2 – MODF Mode Fault Error (cleared on read) Value Description 0 No mode fault has been detected since the last read of SPI_SR.
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SAM E70/S70/V70/V71 Family Serial Peripheral Interface (SPI) 41.8.6 SPI Interrupt Enable Register Name: Offset: Reset: Property: SPI_IER 0x14 – Write-only This register can only be written if the WPITEN bit is cleared in the SPI Write Protection Mode Register. The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Enables the corresponding interrupt.
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SAM E70/S70/V70/V71 Family Serial Peripheral Interface (SPI) 41.8.7 SPI Interrupt Disable Register Name: Offset: Reset: Property: SPI_IDR 0x18 – Write-only This register can only be written if the WPITEN bit is cleared in the SPI Write Protection Mode Register. The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Disables the corresponding interrupt.
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SAM E70/S70/V70/V71 Family Serial Peripheral Interface (SPI) 41.8.8 SPI Interrupt Mask Register Name: Offset: Reset: Property: SPI_IMR 0x1C 0x0 Read-only The following configuration values are valid for all listed bit names of this register: 0: The corresponding interrupt is not enabled. 1: The corresponding interrupt is enabled.
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SAM E70/S70/V70/V71 Family Serial Peripheral Interface (SPI) 41.8.9 SPI Chip Select Register Name: Offset: Reset: Property: SPI_CSRx 0x30 + x*0x04 [x=0..3] 0 R/W This register can only be written if the WPEN bit is cleared in the SPI Write Protection Mode Register. SPI_CSRx must be written even if the user wants to use the default reset values. The BITS field is not updated with the translated value unless the register is written.
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SAM E70/S70/V70/V71 Family Serial Peripheral Interface (SPI) Bits 7:4 – BITS[3:0] Bits Per Transfer (See Note under the register table in SPI Chip Select Register.) The BITS field determines the number of data bits transferred. Reserved values should not be used.
PAGE 1003
SAM E70/S70/V70/V71 Family Serial Peripheral Interface (SPI) 41.8.10 SPI Write Protection Mode Register Name: Offset: Reset: Property: SPI_WPMR 0xE4 0x0 Read/Write See section Register Write Protection for the list of registers that can be write-protected.
PAGE 1004
SAM E70/S70/V70/V71 Family Serial Peripheral Interface (SPI) 41.8.
PAGE 1005
SAM E70/S70/V70/V71 Family Quad Serial Peripheral Interface (QSPI) 42. Quad Serial Peripheral Interface (QSPI) 42.1 Description The Quad Serial Peripheral Interface (QSPI) is a synchronous serial data link that provides communication with external devices in Master mode. The QSPI can be used in SPI mode to interface to serial peripherals such as ADCs, DACs, LCD controllers, CAN controllers and sensors, or in Serial Memory mode to interface to serial Flash memories.
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SAM E70/S70/V70/V71 Family Quad Serial Peripheral Interface (QSPI) 42.3 Block Diagram Figure 42-1. Block Diagram PMC peripheral clock QSPI QSCK MOSI/QIO0 Peripheral Bridge APB MISO/QIO1 CPU PIO AHB MATRIX QIO2 QIO3 QCS DMA Interrupt Control QSPI Interrupt 42.4 Signal Description Table 42-1.
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SAM E70/S70/V70/V71 Family Quad Serial Peripheral Interface (QSPI) 42.5.3 Interrupt Sources The QSPI has an interrupt line connected to the Interrupt Controller. Handling the QSPI interrupt requires programming the interrupt controller before configuring the QSPI. 42.5.4 Direct Memory Access Controller (DMA) The QSPI can be used in conjunction with the Direct Memory Access Controller (DMA) in order to reduce processor overhead.
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SAM E70/S70/V70/V71 Family Quad Serial Peripheral Interface (QSPI) Figure 42-2. QSPI Transfer Format (QSPI_SCR.CPHA = 0, 8 bits per transfer) 1 QSCK cycle (for reference) 2 3 4 6 5 7 8 QSCK (CPOL = 0) QSCK (CPOL = 1) MOSI (from master) MSB MISO (from slave) MSB 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB * QCS (to slave) * Not defined, but normally MSB of previous character received. Figure 42-3. QSPI Transfer Format (QSPI_SCR.
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SAM E70/S70/V70/V71 Family Quad Serial Peripheral Interface (QSPI) These delays allow the QSPI to be adapted to the interfaced peripherals and their speed and bus release time. Figure 42-4. Programmable Delays QCS QSCK DLYCS 42.6.4 DLYBS DLYBCT DLYBCT QSPI SPI Mode In SPI mode, the QSPI acts as a standard SPI Master. To activate this mode, QSPI_MR.SMM must be written to ‘0’ in QSPI_MR. 42.6.4.
PAGE 1010
SAM E70/S70/V70/V71 Family Quad Serial Peripheral Interface (QSPI) 42.6.4.2 SPI Mode Block Diagram Figure 42-5. SPI Mode Block Diagram QSPI_SCR SCBR peripheral clock Baud Rate Generator QSCK Serial Clock QSPI_SCR QSPI_RDR RDRF OVRES RD CPHA CPOL LSB MSB Shift Register MISO QSPI_MR NBBITS MOSI QSPI_TDR TD Chip Select Controller TDRE QCS QSPI_MR CSMODE © 2019 Microchip Technology Inc.
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SAM E70/S70/V70/V71 Family Quad Serial Peripheral Interface (QSPI) 42.6.4.3 SPI Mode Flow Diagram Figure 42-6.
PAGE 1012
SAM E70/S70/V70/V71 Family Quad Serial Peripheral Interface (QSPI) Figure 42-7. Status Register Flags Behavior 1 2 3 4 6 5 7 8 QSCK QCS MOSI (from master) MSB 6 5 4 3 2 1 LSB TDRE QSPI_RDR read Write in QSPI_TDR RDRF MISO (from slave) MSB 6 5 4 3 2 1 LSB TXEMPTY shift register empty 42.6.4.
PAGE 1013
SAM E70/S70/V70/V71 Family Quad Serial Peripheral Interface (QSPI) 42.6.5 QSPI Serial Memory Mode In Serial Memory mode, the QSPI acts as a serial Flash memory controller. The QSPI can be used to read data from the serial Flash memory allowing the CPU to execute code from it (XIP execute in place). The QSPI can also be used to control the serial Flash memory (Program, Erase, Lock, etc.) by sending specific commands. In this mode, the QSPI is compatible with single-bit SPI, Dual SPI and Quad SPI protocols.
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SAM E70/S70/V70/V71 Family Quad Serial Peripheral Interface (QSPI) • • • • • • • • • WIDTH field—used to configure which data lanes are used to send the instruction code, the address, the option code and to transfer the data. It is possible to use two unidirectional data lanes (MISO-MOSI Single-bit SPI), two bidirectional data lanes (QIO0-QIO1 Dual SPI) or four bidirectional data lanes (QIO0–QIO3 Quad SPI). INSTEN bit—used to enable the send of an instruction code.
PAGE 1015
SAM E70/S70/V70/V71 Family Quad Serial Peripheral Interface (QSPI) Figure 42-9.
PAGE 1016
SAM E70/S70/V70/V71 Family Quad Serial Peripheral Interface (QSPI) 42.6.5.3 Read Memory Transfer The user can access the data of the serial memory by sending an instruction with QSPI_IFR.DATAEN = 1 and QSPI_IFR.TFRTYP = 1. In this mode, the QSPI is able to read data at random address into the serial Flash memory, allowing the CPU to execute code directly from it (XIP execute-in-place). In order to fetch data, the user must first configure the instruction frame by writing the QSPI_IFR.
PAGE 1017
SAM E70/S70/V70/V71 Family Quad Serial Peripheral Interface (QSPI) • Wait for QSPI_SR.INSTRE to rise. Figure 42-11. Instruction Transmission Waveform 1 Write QSPI_IFR QCS QSCK MOSI / QIO0 Instruction C7h QSPI_SR.INSTRE Example 2: Instruction in Quad SPI, without address, without option, without data. Command: POWER DOWN (B9h) • • • Write 0x0000_00B9 in QSPI_ICR. Write 0x0000_0016 in QSPI_IFR. Wait for QSPI_SR.INSTRE to rise. Figure 42-12.
PAGE 1018
SAM E70/S70/V70/V71 Family Quad Serial Peripheral Interface (QSPI) Figure 42-13. Instruction Transmission Waveform 3 Write QSPI_IAR Write QSPI_IFR QCS QSCK A23 A22 A21 A20 MOSI / QIO0 A3 A2 A1 A0 Address Instruction 20h QSPI_SR.INSTRE Example 4: Instruction in Single-bit SPI, without address, without option, with data write in Single-bit SPI. Command: SET BURST (77h) • • • • • • Write 0x0000_0077 in QSPI_ICR. Write 0x0000_2090 in QSPI_IFR. Read QSPI_IFR (dummy read) to synchronize system bus accesses.
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SAM E70/S70/V70/V71 Family Quad Serial Peripheral Interface (QSPI) Figure 42-15. Instruction Transmission Waveform 5 Write QSPI_IFR QCS QSCK A22 A20 A18 A16 A14 A12 A10 A8 A6 A4 A2 A0 D6 D4 D2 D0 QIO0 D6 D4 D2 D0 A23 A21 A19 A17 A15 A13 A11 A9 A7 A5 A3 A1 D7 D5 D3 D1 QIO1 Instruction 02h D7 D5 D3 D1 Data Address QSPI_SR.INSTRE Write AHB Set QSPI_CR.LASTXFR Example 6: Instruction in Single-bit SPI, with address in Single-bit SPI, without option, with data read in Quad SPI, with eight dummy cycles.
PAGE 1020
SAM E70/S70/V70/V71 Family Quad Serial Peripheral Interface (QSPI) Figure 42-17.
PAGE 1021
SAM E70/S70/V70/V71 Family Quad Serial Peripheral Interface (QSPI) Figure 42-19. Instruction Transmission Waveform 9 Write QSPI_IFR QCS QSCK QIO0 D4 D0 D4 D0 QIO1 D5 D1 D5 D1 QIO2 D6 D2 D6 D2 D7 D3 QIO3 Instruction 05h D7 D3 Data Read AHB Set QSPI_CR.LASTXFR Example 10: Instruction in Quad SPI, without address, without option, with data read in Quad SPI, without dummy cycles, without fetch, read launched through APB interface.
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SAM E70/S70/V70/V71 Family Quad Serial Peripheral Interface (QSPI) The scrambling/unscrambling function can be enabled by writing a ‘1’ to the SCREN bit in the QSPI Scrambling Mode Register (QSPI_SMR). The scrambling and unscrambling are performed on-the-fly without impacting the throughput. The scrambling method depends on the user-configurable user scrambling key (field USRK) in the QSPI Scrambling Key Register (QSPI_SKR). QSPI_SKR is only accessible in Write mode. If QSPI_SMR.
PAGE 1023
SAM E70/S70/V70/V71 Family Quad Serial Peripheral Interface (QSPI) 42.7 Register Summary Offset Name 0x00 QSPI_CR 0x04 QSPI_MR 0x08 QSPI_RDR 0x0C QSPI_TDR 0x10 QSPI_SR 0x14 QSPI_IER 0x18 QSPI_IDR 0x1C QSPI_IMR 0x20 QSPI_SCR 0x24 ... 0x2F Reserved 0x30 QSPI_IAR 0x34 QSPI_ICR 0x38 0x3C ... 0x3F QSPI_IFR Bit Pos.
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SAM E70/S70/V70/V71 Family Quad Serial Peripheral Interface (QSPI) ...........continued Offset Name 0x40 QSPI_SMR 0x44 QSPI_SKR 0x48 ... 0xE3 Reserved 0xE4 0xE8 QSPI_WPMR QSPI_WPSR Bit Pos. 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 © 2019 Microchip Technology Inc.
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SAM E70/S70/V70/V71 Family Quad Serial Peripheral Interface (QSPI) 42.7.1 QSPI Control Register Name: Offset: Reset: Property: Bit QSPI_CR 0x00 – Write-only 31 30 29 28 27 26 25 24 LASTXFER W – 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 SWRST W – 6 5 4 3 2 1 QSPIDIS W – 0 QSPIEN W – Access Reset Bit Access Reset Bit Access Reset Bit Access Reset Bit 24 – LASTXFER Last Transfer Value Description 0 No effect.
PAGE 1026
SAM E70/S70/V70/V71 Family Quad Serial Peripheral Interface (QSPI) 42.7.2 QSPI Mode Register Name: Offset: Reset: Property: QSPI_MR 0x04 0x00000000 Read/Write This register can only be written if bit WPEN is cleared in the QSPI Write Protection Mode Register.
PAGE 1027
SAM E70/S70/V70/V71 Family Quad Serial Peripheral Interface (QSPI) Value 1 2 Name LASTXFER Description The chip select is deasserted when the bit LASTXFER is written to ‘1’ and the character written in QSPI_TDR.TD has been transferred. SYSTEMATICALLY The chip select is deasserted systematically after each transfer. Bit 2 – WDRBT Wait Data Read Before Transfer 0 (DISABLED): No effect. In SPI mode, a transfer can be initiated whatever the state of the QSPI_RDR is.
PAGE 1028
SAM E70/S70/V70/V71 Family Quad Serial Peripheral Interface (QSPI) 42.7.
PAGE 1029
SAM E70/S70/V70/V71 Family Quad Serial Peripheral Interface (QSPI) 42.7.
PAGE 1030
SAM E70/S70/V70/V71 Family Quad Serial Peripheral Interface (QSPI) 42.7.5 QSPI Status Register Name: Offset: Reset: Property: Bit QSPI_SR 0x10 0x00000000 Read-only 31 30 29 28 27 26 25 24 QSPIENS R 0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 INSTRE R 0 9 CSS R 0 8 CSR R 0 7 6 5 4 3 OVRES R 0 2 TXEMPTY R 0 1 TDRE R 0 0 RDRF R 0 Access Reset Bit Access Reset Bit Access Reset Bit Access Reset Bit 24 – QSPIENS QSPI Enable Status Value Description 0 QSPI is disabled.
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SAM E70/S70/V70/V71 Family Quad Serial Peripheral Interface (QSPI) Value 1 Description QSPI_TDR and the internal shifter are empty. If a transfer delay has been defined, TXEMPTY is set after the completion of such delay. Bit 1 – TDRE Transmit Data Register Empty (cleared by writing QSPI_TDR) TDRE equals zero when the QSPI is disabled or at reset. The QSPI enable command sets this bit to one. Value Description 0 Data has been written to QSPI_TDR and not yet transferred to the serializer.
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SAM E70/S70/V70/V71 Family Quad Serial Peripheral Interface (QSPI) 42.7.6 QSPI Interrupt Enable Register Name: Offset: Reset: Property: QSPI_IER 0x14 – Write-only The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Enables the corresponding interrupt.
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SAM E70/S70/V70/V71 Family Quad Serial Peripheral Interface (QSPI) 42.7.7 QSPI Interrupt Disable Register Name: Offset: Reset: Property: QSPI_IDR 0x18 – Write-only The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Disables the corresponding interrupt.
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SAM E70/S70/V70/V71 Family Quad Serial Peripheral Interface (QSPI) 42.7.8 QSPI Interrupt Mask Register Name: Offset: Reset: Property: QSPI_IMR 0x1C 0x00000000 Read-only The following configuration values are valid for all listed bit names of this register: 0: The corresponding interrupt is not enabled. 1: The corresponding interrupt is enabled.
PAGE 1035
SAM E70/S70/V70/V71 Family Quad Serial Peripheral Interface (QSPI) 42.7.9 QSPI Serial Clock Register Name: Offset: Reset: Property: QSPI_SCR 0x20 0x00000000 Read/Write This register can only be written if bit WPEN is cleared in the QSPI Write Protection Mode Register.
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SAM E70/S70/V70/V71 Family Quad Serial Peripheral Interface (QSPI) 42.7.
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SAM E70/S70/V70/V71 Family Quad Serial Peripheral Interface (QSPI) 42.7.
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SAM E70/S70/V70/V71 Family Quad Serial Peripheral Interface (QSPI) 42.7.
PAGE 1039
SAM E70/S70/V70/V71 Family Quad Serial Peripheral Interface (QSPI) Value 0 Name TRSFR_READTRSFR_REGISTER Description Read transfer from the serial memory. Scrambling is not performed. 1 Read at random location (fetch) in the serial Flash memory is not possible.Read/Write transfer from the serial memory. Scrambling is not performed. Read at random location (fetch) in the serial Flash memory is not possible. TRSFR_READ_MEMORYTRSFR_MEMORY Read data transfer from the serial memory.
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SAM E70/S70/V70/V71 Family Quad Serial Peripheral Interface (QSPI) Bits 2:0 – WIDTH[2:0] Width of Instruction Code, Address, Option Code and Data Value Name Description 0 SINGLE_BIT_SPI Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI 1 DUAL_OUTPUT Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI 2 QUAD_OUTPUT Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI 3 DUAL_IO Instruction: Single-bit SPI / Address-Option: Du
PAGE 1041
SAM E70/S70/V70/V71 Family Quad Serial Peripheral Interface (QSPI) 42.7.13 QSPI Scrambling Mode Register Name: Offset: Reset: Property: QSPI_SMR 0x40 0x00000000 Read/Write This register can only be written if bit WPEN is cleared in the QSPI Write Protection Mode Register.
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SAM E70/S70/V70/V71 Family Quad Serial Peripheral Interface (QSPI) 42.7.14 QSPI Scrambling Key Register Name: Offset: Reset: Property: QSPI_SKR 0x44 – Write-only This register can only be written if bit WPEN is cleared in the QSPI Write Protection Mode Register.
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SAM E70/S70/V70/V71 Family Quad Serial Peripheral Interface (QSPI) 42.7.
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SAM E70/S70/V70/V71 Family Quad Serial Peripheral Interface (QSPI) 42.7.
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SAM E70/S70/V70/V71 Family Two-wire Interface (TWIHS) 43. Two-wire Interface (TWIHS) 43.1 Description The Two-wire Interface (TWIHS) interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds of up to 400 kbit/s in Fast mode and up to 3.4 Mbit/s in High-speed slave mode only, based on a byte-oriented transfer format.
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SAM E70/S70/V70/V71 Family Two-wire Interface (TWIHS) • • Connection to DMA Controller (DMA) Channel Capabilities Optimizes Data Transfers Register Write Protection Note: See TWI Compatibility with I2C Standard for details on compatibility with I²C Standard. 43.3 List of Abbreviations Table 43-2. Abbreviations 43.
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SAM E70/S70/V70/V71 Family Two-wire Interface (TWIHS) 43.5 43.5.1 Product Dependencies I/O Lines Both TWD and TWCK are bidirectional lines, connected to a positive supply voltage via a current source or pullup resistor. When the bus is free, both lines are high. The output stages of devices connected to the bus must have an open-drain or open-collector to perform the wired-AND function. TWD and TWCK pins may be multiplexed with PIO lines.
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SAM E70/S70/V70/V71 Family Two-wire Interface (TWIHS) • • • • • Master Receiver mode (Standard and Fast modes only) Multimaster Transmitter mode (Standard and Fast modes only) Multimaster Receiver mode (Standard and Fast modes only) Slave Transmitter mode (Standard, Fast and High-speed modes) Slave Receiver mode (Standard, Fast and High-speed modes) These modes are described in the following sections. 43.6.3 Master Mode 43.6.3.
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SAM E70/S70/V70/V71 Family Two-wire Interface (TWIHS) Figure 43-4. Master Write with One Data Byte STOP Command sent (write in TWIHS_CR) TWD S DADR W A DATA A P TXCOMP TXRDY Write THR (DATA) Figure 43-5. Master Write with Multiple Data Bytes STOP command performed (by writing in TWIHS_CR) S TWD DADR W A DATA n A DATA n+1 A DATA n+2 A P TWCK TXCOMP TXRDY Write THR (Data n) Write THR (Data n+1) Write THR (Data n+2) Last data sent Figure 43-6.
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SAM E70/S70/V70/V71 Family Two-wire Interface (TWIHS) data line (HIGH), enabling the slave to pull it down in order to generate the acknowledge. The master polls the data line during this clock pulse and sets TWIHS_SR.NACK if the slave does not acknowledge the byte. If an acknowledge is received, the master is then ready to receive data from the slave.
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SAM E70/S70/V70/V71 Family Two-wire Interface (TWIHS) Figure 43-9. Master Read Clock Stretching with Multiple Data Bytes STOP command performed (by writing in TWIHS_CR) Clock Streching TWD S DADR W A DATA n A DATA n+1 A DATA n+2 A P TWCK TXCOMP RXRDY Read RHR (Data n) Read RHR (Data n+1) Read RHR (Data n+2) RXRDY is used as receive ready for the DMA receive channel. 43.6.3.
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SAM E70/S70/V70/V71 Family Two-wire Interface (TWIHS) Figure 43-10. Master Write with One-, Two- or Three-Byte Internal Address and One Data Byte Three-byte internal address S TWD DADR W A IADR(23:16) A IADR(15:8) A IADR(7:0) A W A IADR(15:8) A IADR(7:0) A DATA A W A IADR(7:0) A DATA A DATA A P Two-byte internal address S TWD DADR P One-byte internal address S TWD DADR P Figure 43-11.
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SAM E70/S70/V70/V71 Family Two-wire Interface (TWIHS) 43.6.3.8.1 Data Transmit with the DMA in Master Mode The DMA transfer size must be defined with the buffer size minus 1. The remaining character must be managed without DMA to ensure that the exact number of bytes are transmitted regardless of system bus latency conditions during the end of the buffer transfer period. 1. 2. 3. 4. 5. 6. 7. 8. 9. Initialize the DMA (channels, memory pointers, size - 1, etc.
PAGE 1054
SAM E70/S70/V70/V71 Family Two-wire Interface (TWIHS) In Master Receiver mode, the slave calculates a PEC value and transmits it to the master after all data bytes have been transmitted. Upon reception of this PEC byte, the master compares it to the PEC value it has computed itself. If the values match, the data was received correctly. If the PEC values differ, data was corrupted, and TWIHS_SR.PECERR is set.
PAGE 1055
SAM E70/S70/V70/V71 Family Two-wire Interface (TWIHS) Figure 43-14.
PAGE 1056
SAM E70/S70/V70/V71 Family Two-wire Interface (TWIHS) Figure 43-15.
PAGE 1057
SAM E70/S70/V70/V71 Family Two-wire Interface (TWIHS) Figure 43-16.
PAGE 1058
SAM E70/S70/V70/V71 Family Two-wire Interface (TWIHS) Figure 43-17.
PAGE 1059
SAM E70/S70/V70/V71 Family Two-wire Interface (TWIHS) Figure 43-18.
PAGE 1060
SAM E70/S70/V70/V71 Family Two-wire Interface (TWIHS) Figure 43-19.
PAGE 1061
SAM E70/S70/V70/V71 Family Two-wire Interface (TWIHS) Figure 43-20.
PAGE 1062
SAM E70/S70/V70/V71 Family Two-wire Interface (TWIHS) Figure 43-21.
PAGE 1063
SAM E70/S70/V70/V71 Family Two-wire Interface (TWIHS) Figure 43-22.
PAGE 1064
SAM E70/S70/V70/V71 Family Two-wire Interface (TWIHS) Figure 43-23.
PAGE 1065
SAM E70/S70/V70/V71 Family Two-wire Interface (TWIHS) Figure 43-24.
PAGE 1066
SAM E70/S70/V70/V71 Family Two-wire Interface (TWIHS) Figure 43-25.
PAGE 1067
SAM E70/S70/V70/V71 Family Two-wire Interface (TWIHS) Figure 43-26.
PAGE 1068
SAM E70/S70/V70/V71 Family Two-wire Interface (TWIHS) Figure 43-27.
PAGE 1069
SAM E70/S70/V70/V71 Family Two-wire Interface (TWIHS) As soon as arbitration is lost by a master, it stops sending data and listens to the bus in order to detect a stop. When the stop is detected, the master that has lost arbitration may put its data on the bus by respecting arbitration. Arbitration is illustrated in Arbitration Cases. 43.6.4.2 Different Multimaster Modes Two Multimaster modes may be distinguished: 1. 2. The TWIHS is considered as a master only and is never addressed.
PAGE 1070
SAM E70/S70/V70/V71 Family Two-wire Interface (TWIHS) Figure 43-29.
PAGE 1071
SAM E70/S70/V70/V71 Family Two-wire Interface (TWIHS) Figure 43-30.
PAGE 1072
SAM E70/S70/V70/V71 Family Two-wire Interface (TWIHS) In this mode, the device never initiates and never completes the transmission (START, REPEATED_START and STOP conditions are always provided by the master). 43.6.5.2 Programming Slave Mode The following fields must be programmed before entering Slave mode: 1. 2. 3. 4. TWIHS_SMR.SADR: The slave device address is used in order to be accessed by master devices in Read or Write mode. (Optional) TWIHS_SMR.
PAGE 1073
SAM E70/S70/V70/V71 Family Two-wire Interface (TWIHS) 43.6.5.4 Data Transfer 43.6.5.4.1 Read Operation The Read mode is defined as a data requirement from the master. After a START or a REPEATED START condition is detected, the decoding of the address starts. If the slave address (SADR) is decoded, SVACC is set and SVREAD indicates the direction of the transfer. Until a STOP or REPEATED START condition is detected, the TWIHS continues sending data loaded in TWIHS_THR.
PAGE 1074
SAM E70/S70/V70/V71 Family Two-wire Interface (TWIHS) Note: 1. When SVACC is low, the state of SVREAD becomes irrelevant. 2. RXRDY is set when data has been transmitted from the internal shifter to TWIHS_RHR and reset when this data is read. 43.6.5.4.3 General Call The general call is performed in order to change the address of the slave. If a GENERAL CALL is detected, GACC is set. After the detection of general call, decode the commands that follow.
PAGE 1075
SAM E70/S70/V70/V71 Family Two-wire Interface (TWIHS) Figure 43-34.
PAGE 1076
SAM E70/S70/V70/V71 Family Two-wire Interface (TWIHS) 43.6.5.4.5 Reversal after a Repeated Start Reversal of Read to Write The master initiates the communication by a read command and finishes it by a write command. The figure below describes the REPEATED START and the reversal from Read mode to Write mode. Figure 43-36.
PAGE 1077
SAM E70/S70/V70/V71 Family Two-wire Interface (TWIHS) 5. 6. Disable the DMA. (Only if peripheral clock must be disabled) Wait for the TXCOMP flag to be raised in TWIHS_SR. 43.6.5.5.2 Data Receive with the DMA in Slave Mode The following procedure shows an example to transmit data with DMA where the number of characters to receive is known. 1. 2. 3. 4. 5. 6. Initialize the DMA (channels, memory pointers, size, etc.). Configure the Slave mode. Enable the DMA.
PAGE 1078
SAM E70/S70/V70/V71 Family Two-wire Interface (TWIHS) Note: When slave clock stretching is disabled, the TWIHS_RHR must always be read before receiving the next data (MASTER write frame). It is strongly recommended to use either the polling method on the RXRDY flag in TWIHS_SR, or the DMA. If the receive is managed by an interrupt, the TWIHS interrupt priority must be set to the right level and its latency minimized to avoid receive overrun.
PAGE 1079
SAM E70/S70/V70/V71 Family Two-wire Interface (TWIHS) Figure 43-39. Address Match Only (Data Matching Disabled) Address Matching Area Clock Stretching SADR S PClk R/W A DATA A/NA DATA A/NA P A/NA P PClk Startup PClk_request SystemWakeUp_req Figure 43-40. No Address Match (Data Matching Disabled) Address Matching Area Clock Stretching SADR S PClk R/W NA P A DATA PClk Startup PClk_request SystemWakeUp_req Figure 43-41.
PAGE 1080
SAM E70/S70/V70/V71 Family Two-wire Interface (TWIHS) Figure 43-42. Address Match and No Data Match (Data Matching Enabled) Address Matching + Data Matching Area Clock Stretching S PClk SADR W A DATA NA DATA NA P PClk Startup PClk_request SystemWakeUp_req 43.6.5.9 Slave Read Write Flowcharts The flowchart below illustrates an example of read and write operations in Slave mode. A polling or interrupt method can be used to check the status bits.
PAGE 1081
SAM E70/S70/V70/V71 Family Two-wire Interface (TWIHS) Figure 43-43. Read Write Flowchart in Slave Mode Set the SLAVE mode: SADR + MSDIS + SVEN Read Status Register SVACC = 1 ? No No No GACC = 1 ? No SVREAD = 1 ? EOSACC = 1 ? TXRDY= 1 ? No No Write in TWIHS_THR TXCOMP = 1 ? RXRDY= 1 ? No END Read TWIHS_RHR GENERAL CALL TREATMENT Decoding of the programming sequence Prog seq OK ? No Change SADR © 2019 Microchip Technology Inc.
PAGE 1082
SAM E70/S70/V70/V71 Family Two-wire Interface (TWIHS) Figure 43-44.
PAGE 1083
SAM E70/S70/V70/V71 Family Two-wire Interface (TWIHS) Figure 43-45. Read Write Flowchart in Slave Mode with SMBus PEC and Alternative Command Mode Set SLAVE mode: SADR + MSDIS + SVEN + SMBEN + PECEN + ACMEN Read Status Register SVACC = 1 ? GACC = 1 ? SVREAD = 1 ? No No No No EOSACC = 1 ? TXRDY= 1 ? No No Write in TWIHS_THR TXCOMP = 1 ? RXRDY= 1 ? No END Read TWIHS_RHR GENERAL CALL TREATMENT Decoding of the programming sequence Prog seq OK ? No Change SADR 43.6.
PAGE 1084
SAM E70/S70/V70/V71 Family Two-wire Interface (TWIHS) The following registers can be write-protected: • TWIHS Clock Waveform Generator Register © 2019 Microchip Technology Inc.
PAGE 1085
SAM E70/S70/V70/V71 Family Two-wire Interface (TWIHS) 43.7 Register Summary Offset Name 0x00 TWIHS_CR 0x04 TWIHS_MMR 0x08 TWIHS_SMR 0x0C TWIHS_IADR 0x10 TWIHS_CWGR 0x14 ... 0x1F 0x20 0x24 0x28 0x2C 0x30 0x34 Bit Pos.
PAGE 1086
SAM E70/S70/V70/V71 Family Two-wire Interface (TWIHS) ...........continued Offset Name Bit Pos. 0x44 TWIHS_FILTR 7:0 15:8 23:16 31:24 0x48 ... 0x4B Reserved 0x4C TWIHS_SWMR 0x50 ... 0xE3 Reserved 0xE4 0xE8 TWIHS_WPMR TWIHS_WPSR 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 © 2019 Microchip Technology Inc.
PAGE 1087
SAM E70/S70/V70/V71 Family Two-wire Interface (TWIHS) 43.7.
PAGE 1088
SAM E70/S70/V70/V71 Family Two-wire Interface (TWIHS) Value 1 Description Alternative Command mode enabled. Bit 15 – CLEAR Bus CLEAR Command Value Description 0 No effect. 1 If Master mode is enabled, sends a bus clear command. Bit 14 – PECRQ PEC Request Value Description 0 No effect. 1 A PEC check or transmission is requested. Bit 13 – PECDIS Packet Error Checking Disable Value Description 0 No effect. 1 SMBus PEC (CRC) generation and check disabled.
PAGE 1089
SAM E70/S70/V70/V71 Family Two-wire Interface (TWIHS) Value 1 Description The Slave mode is disabled. The shifter and holding characters (if it contains data) are transmitted in case of read operation. In write operation, the character being transferred must be completely received before disabling. Bit 4 – SVEN TWIHS Slave Mode Enabled Switching from Master to Slave mode is only permitted when TXCOMP = 1. Value Description 0 No effect. 1 Enables the Slave mode (SVDIS must be written to 0).
PAGE 1090
SAM E70/S70/V70/V71 Family Two-wire Interface (TWIHS) 43.7.
PAGE 1091
SAM E70/S70/V70/V71 Family Two-wire Interface (TWIHS) 43.7.
PAGE 1092
SAM E70/S70/V70/V71 Family Two-wire Interface (TWIHS) Bit 6 – SCLWSDIS Clock Wait State Disable Value Description 0 No effect. 1 Clock stretching disabled in Slave mode, OVRE and UNRE indicate an overrun/underrun. Bit 3 – SMHH SMBus Host Header Value Description 0 Acknowledge of the SMBus host header disabled. 1 Acknowledge of the SMBus host header enabled. Bit 2 – SMDA SMBus Default Address Value Description 0 Acknowledge of the SMBus default address disabled.
PAGE 1093
SAM E70/S70/V70/V71 Family Two-wire Interface (TWIHS) 43.7.
PAGE 1094
SAM E70/S70/V70/V71 Family Two-wire Interface (TWIHS) 43.7.5 TWIHS Clock Waveform Generator Register Name: Offset: Reset: Property: TWIHS_CWGR 0x10 0x00000000 Read/Write This register can only be written if the WPEN bit is cleared in the TWIHS Write Protection Mode Register. TWIHS_CWGR is used in Master mode only.
PAGE 1095
SAM E70/S70/V70/V71 Family Two-wire Interface (TWIHS) 43.7.
PAGE 1096
SAM E70/S70/V70/V71 Family Two-wire Interface (TWIHS) Value 1 Description An SMBus timeout occurred since the last read of TWIHS_SR. Bit 16 – MCACK Master Code Acknowledge (cleared on read) MACK used in Slave mode: Value Description 0 No Master Code has been received since the last read of TWIHS_SR. 1 A Master Code has been received since the last read of TWIHS_SR. Bit 11 – EOSACC End Of Slave Access (cleared on read) This bit is used in Slave mode only.
PAGE 1097
SAM E70/S70/V70/V71 Family Two-wire Interface (TWIHS) Bit 5 – GACC General Call Access (cleared on read) This bit is used in Slave mode only. GACC behavior can be seen in Master Performs a General Call. Value Description 0 No general call has been detected. 1 A general call has been detected. After the detection of general call, if need be, the user may acknowledge this access and decode the following bytes and respond according to the value of the bytes.
PAGE 1098
SAM E70/S70/V70/V71 Family Two-wire Interface (TWIHS) Bit 0 – TXCOMP Transmission Completed (cleared by writing TWIHS_THR) • TXCOMP used in Master mode: 0: During the length of the current frame. 1: When both holding register and internal shifter are empty and STOP condition has been sent. TXCOMP behavior in Master mode can be seen in Master Write with One-Byte Internal Address and Multiple Data Bytes and in Master Read with Multiple Data Bytes.
PAGE 1099
SAM E70/S70/V70/V71 Family Two-wire Interface (TWIHS) 43.7.7 TWIHS SMBus Timing Register Name: Offset: Reset: Property: TWIHS_SMBTR 0x38 0x00000000 Read/Write This register can only be written if the WPEN bit is cleared in the TWIHS Write Protection Mode Register.
PAGE 1100
SAM E70/S70/V70/V71 Family Two-wire Interface (TWIHS) 43.7.8 TWIHS Filter Register Name: Offset: Reset: Property: TWIHS_FILTR 0x44 0x00000000 Read/Write TWIHS digital input filtering follows a majority decision based on three samples from SDA/SCL lines at peripheral clock frequency.
PAGE 1101
SAM E70/S70/V70/V71 Family Two-wire Interface (TWIHS) 43.7.9 TWIHS Interrupt Enable Register Name: Offset: Reset: Property: TWIHS_IER 0x24 – Write-only The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Enables the corresponding interrupt.
PAGE 1102
SAM E70/S70/V70/V71 Family Two-wire Interface (TWIHS) Bit 4 – SVACC Slave Access Interrupt Enable Bit 2 – TXRDY Transmit Holding Register Ready Interrupt Enable Bit 1 – RXRDY Receive Holding Register Ready Interrupt Enable Bit 0 – TXCOMP Transmission Completed Interrupt Enable © 2019 Microchip Technology Inc.
PAGE 1103
SAM E70/S70/V70/V71 Family Two-wire Interface (TWIHS) 43.7.10 TWIHS Interrupt Disable Register Name: Offset: Reset: Property: TWIHS_IDR 0x28 – Write-only The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Disables the corresponding interrupt.
PAGE 1104
SAM E70/S70/V70/V71 Family Two-wire Interface (TWIHS) Bit 4 – SVACC Slave Access Interrupt Disable Bit 2 – TXRDY Transmit Holding Register Ready Interrupt Disable Bit 1 – RXRDY Receive Holding Register Ready Interrupt Disable Bit 0 – TXCOMP Transmission Completed Interrupt Disable © 2019 Microchip Technology Inc.
PAGE 1105
SAM E70/S70/V70/V71 Family Two-wire Interface (TWIHS) 43.7.11 TWIHS Interrupt Mask Register Name: Offset: Reset: Property: TWIHS_IMR 0x2C 0x00000000 Read-only The following configuration values are valid for all listed bit names of this register: 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
PAGE 1106
SAM E70/S70/V70/V71 Family Two-wire Interface (TWIHS) Bit 4 – SVACC Slave Access Interrupt Mask Bit 2 – TXRDY Transmit Holding Register Ready Interrupt Mask Bit 1 – RXRDY Receive Holding Register Ready Interrupt Mask Bit 0 – TXCOMP Transmission Completed Interrupt Mask © 2019 Microchip Technology Inc.
PAGE 1107
SAM E70/S70/V70/V71 Family Two-wire Interface (TWIHS) 43.7.12 TWIHS Receive Holding Register Name: Offset: Reset: Property: Bit TWIHS_RHR 0x30 0x00000000 Read-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 R 0 R 0 R 0 Access Reset Bit Access Reset Bit Access Reset Bit RXDATA[7:0] Access Reset R 0 R 0 R 0 R 0 Bits 7:0 – RXDATA[7:0] Master or Slave Receive Holding Data © 2019 Microchip Technology Inc.
PAGE 1108
SAM E70/S70/V70/V71 Family Two-wire Interface (TWIHS) 43.7.13 TWIHS SleepWalking Matching Register Name: Offset: Reset: Property: TWIHS_SWMR 0x4C 0x00000000 Read/Write This register can only be written if the WPEN bit is cleared in the TWIHS Write Protection Mode Register.
PAGE 1109
SAM E70/S70/V70/V71 Family Two-wire Interface (TWIHS) 43.7.14 TWIHS Transmit Holding Register Name: Offset: Reset: Property: Bit TWIHS_THR 0x34 0x00000000 Write-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 W 0 W 0 W 0 W 0 Access Reset Bit Access Reset Bit Access Reset Bit TXDATA[7:0] Access Reset W 0 W 0 W 0 W 0 Bits 7:0 – TXDATA[7:0] Master or Slave Transmit Holding Data © 2019 Microchip Technology Inc.
PAGE 1110
SAM E70/S70/V70/V71 Family Two-wire Interface (TWIHS) 43.7.
PAGE 1111
SAM E70/S70/V70/V71 Family Two-wire Interface (TWIHS) 43.7.
PAGE 1112
SAM E70/S70/V70/V71 Family Synchronous Serial Controller (SSC) 44. 44.1 Synchronous Serial Controller (SSC) Description The Synchronous Serial Controller (SSC) provides a synchronous communication link with external devices. It supports many serial synchronous communication protocols generally used in audio and telecom applications such as I2S, Short Frame Sync, Long Frame Sync, etc. The SSC contains an independent receiver and transmitter and a common clock divider.
PAGE 1113
SAM E70/S70/V70/V71 Family Synchronous Serial Controller (SSC) 44.3 Block Diagram Figure 44-1. Block Diagram System Bus Peripheral Bridge DMA Bus Clock Peripheral Bus TF TK TD Peripheral Clock PMC PIO SSC Interface RF RK Interrupt Control RD SSC Interrupt 44.4 Application Block Diagram Figure 44-2. Application Block Diagram OS or RTOS Driver Power Management Interrupt Management Test Management SSC Serial AUDIO 44.
PAGE 1114
SAM E70/S70/V70/V71 Family Synchronous Serial Controller (SSC) Figure 44-3. Audio Application Block Diagram Clock SCK TK Word Select WS I2S RECEIVER TF SSC Data SD TD RD Clock SCK RF Word Select WS RK MSB Data SD LSB Left Channel MSB Right Channel Figure 44-4.
PAGE 1115
SAM E70/S70/V70/V71 Family Synchronous Serial Controller (SSC) Figure 44-5. Time Slot Application Block Diagram SCLK TK FSYNC TF CODEC First Time Slot Data Out TD SSC Data In RD RF RK CODEC Second Time Slot Serial Data Clock (SCLK) First Time Slot Frame Sync (FSYNC) Dstart Second Time Slot Dend Serial Data Out Serial Data in 44.6 Pin Name List Table 44-1. I/O Lines Description 44.7 44.7.
PAGE 1116
SAM E70/S70/V70/V71 Family Synchronous Serial Controller (SSC) 44.7.2 Power Management The SSC is not continuously clocked. The SSC interface may be clocked through the Power Management Controller (PMC), therefore the programmer must first configure the PMC to enable the SSC clock. 44.7.3 Interrupt The SSC interface has an interrupt line connected to the interrupt controller. Handling interrupts requires programming the interrupt controller before configuring the SSC.
PAGE 1117
SAM E70/S70/V70/V71 Family Synchronous Serial Controller (SSC) 44.8.
PAGE 1118
SAM E70/S70/V70/V71 Family Synchronous Serial Controller (SSC) Figure 44-9. Transmit Clock Management TK (pin) Receive Clock Tri_state Controller Clock Output MUX Divider Clock CKO CKS Data Transfer INV MUX Tri_state Controller CKI CKG Transmit Clock 44.8.1.3 Receive Clock Management The receive clock is generated from the transmit clock or the divider clock or an external clock scanned on the RK I/O pad. The Receive Clock is selected by the CKS field in SSC_RCMR (Receive Clock Mode Register).
PAGE 1119
SAM E70/S70/V70/V71 Family Synchronous Serial Controller (SSC) • • Peripheral clock divided by 2 if Receive Frame Synchronization is input Peripheral clock divided by 3 if Receive Frame Synchronization is output In addition, the maximum clock speed allowed on the TK pin is: • Peripheral clock divided by 6 if Transmit Frame Synchronization is input • Peripheral clock divided by 2 if Transmit Frame Synchronization is output These are only theoretical speed limits for first order calculations.
PAGE 1120
SAM E70/S70/V70/V71 Family Synchronous Serial Controller (SSC) Receive Holding Register (SSC_RHR), the status flag OVERUN is set in the SSC_SR and the receiver shift register is transferred in the SSC_RHR. Figure 44-12. Receive Block Diagram SSC_CR.RXEN SSC_SR.RXEN SSC_CR.RXDIS SSC_TCMR.START SSC_RCMR.START TXEN RX Start RF Start Selector RXEN RF RC0R Start Selector SSC_RFMR.MSBF SSC_RFMR.DATNB RX Start RX Controller RD Receive Shift Register SSC_RCMR.STTDLY != 0 load SSC_RSHR SSC_RFMR.
PAGE 1121
SAM E70/S70/V70/V71 Family Synchronous Serial Controller (SSC) Figure 44-13. Transmit Start Mode TK TF (Input) Start = Low Level on TF Start = Falling Edge on TF Start = High Level on TF Start = Rising Edge on TF TD (Output) TD (Output) X BO X TD (Output) TD (Output) B1 STTDLY BO X BO B1 STTDLY BO B1 BO B1 BO B1 BO B1 BO B1 X X STTDLY B1 X TD (Output) TD Start = Level Change on TF (Output) Start = Any Edge on TF BO STTDLY B1 STTDLY STTDLY Figure 44-14.
PAGE 1122
SAM E70/S70/V70/V71 Family Synchronous Serial Controller (SSC) During the Frame Sync signal, the receiver can sample the RD line and store the data in the Receive Sync Holding Register and the transmitter can transfer Transmit Sync Holding Register in the shift register. The data length to be sampled/shifted out during the Frame Sync signal is programmed by the FSLEN field in SSC_RFMR/SSC_TFMR and has a maximum value of 256.
PAGE 1123
SAM E70/S70/V70/V71 Family Synchronous Serial Controller (SSC) Table 44-2.
PAGE 1124
SAM E70/S70/V70/V71 Family Synchronous Serial Controller (SSC) Figure 44-18. Receive Frame Format in Continuous Mode (STTDLY = 0) Start = Enable Receiver Data Data To SSC_RHR To SSC_RHR DATLEN DATLEN RD 44.8.8 Loop Mode The receiver can be programmed to receive transmissions from the transmitter. This is done by setting the Loop Mode (LOOP) bit in the SSC_RFMR. In this case, RD is connected to TD, RF is connected to TF and RK is connected to TK. 44.8.
PAGE 1125
SAM E70/S70/V70/V71 Family Synchronous Serial Controller (SSC) • • • • SSC Transmit Clock Mode Register SSC Transmit Frame Mode Register SSC Receive Compare 0 Register SSC Receive Compare 1 Register © 2019 Microchip Technology Inc.
PAGE 1126
SAM E70/S70/V70/V71 Family Synchronous Serial Controller (SSC) 44.9 Register Summary Note: Offsets 0x100–0x128 are reserved for PDC registers. Offset 0x00 Name SSC_CR 0x04 SSC_CMR 0x08 ... 0x0F Reserved 0x10 0x14 0x18 0x1C SSC_RCMR SSC_RFMR SSC_TCMR SSC_TFMR 0x20 SSC_RHR 0x24 SSC_THR 0x28 ... 0x2F Reserved 0x30 SSC_RSHR 0x34 SSC_TSHR 0x38 SSC_RC0R 0x3C SSC_RC1R Bit Pos.
PAGE 1127
SAM E70/S70/V70/V71 Family Synchronous Serial Controller (SSC) ...........continued Offset Name 0x40 SSC_SR 0x44 SSC_IER 0x48 SSC_IDR 0x4C SSC_IMR 0x50 ... 0xE3 Reserved 0xE4 0xE8 SSC_WPMR SSC_WPSR Bit Pos. 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 © 2019 Microchip Technology Inc.
PAGE 1128
SAM E70/S70/V70/V71 Family Synchronous Serial Controller (SSC) 44.9.1 SSC Control Register Name: Offset: Reset: Property: Bit SSC_CR 0x0 – Write-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 SWRST W – 14 13 12 11 10 9 TXDIS W – 8 TXEN W – 7 6 5 4 3 2 1 RXDIS W – 0 RXEN W – Access Reset Bit Access Reset Bit Access Reset Bit Access Reset Bit 15 – SWRST Software Reset Value Description 0 No effect. 1 Performs a software reset.
PAGE 1129
SAM E70/S70/V70/V71 Family Synchronous Serial Controller (SSC) 44.9.2 SSC Clock Mode Register Name: Offset: Reset: Property: SSC_CMR 0x4 0x00000000 Read/Write This register can only be written if the WPEN bit is cleared in the SSC Write Protection Mode Register.
PAGE 1130
SAM E70/S70/V70/V71 Family Synchronous Serial Controller (SSC) 44.9.3 SSC Receive Clock Mode Register Name: Offset: Reset: Property: SSC_RCMR 0x10 0x00000000 Read/Write This register can only be written if the WPEN bit is cleared in the SSC Write Protection Mode Register.
PAGE 1131
SAM E70/S70/V70/V71 Family Synchronous Serial Controller (SSC) Value 8 Name CMP_0 Description Compare 0 Bits 7:6 – CKG[1:0] Receive Clock Gating Selection Value Name Description 0 CONTINUOUS None 1 EN_RF_LOW Receive Clock enabled only if RF Low 2 EN_RF_HIGH Receive Clock enabled only if RF High Bit 5 – CKI Receive Clock Inversion CKI affects only the Receive Clock and not the output clock signal. Value Description 0 The data inputs (Data and Frame Sync signals) are sampled on Receive Clock falling edge.
PAGE 1132
SAM E70/S70/V70/V71 Family Synchronous Serial Controller (SSC) 44.9.4 SSC Receive Frame Mode Register Name: Offset: Reset: Property: SSC_RFMR 0x14 0x00000000 Read/Write This register can only be written if the WPEN bit is cleared in the SSC Write Protection Mode Register.
PAGE 1133
SAM E70/S70/V70/V71 Family Synchronous Serial Controller (SSC) Bit 7 – MSBF Most Significant Bit First Value Description 0 The lowest significant bit of the data register is sampled first in the bit stream. 1 The most significant bit of the data register is sampled first in the bit stream. Bit 5 – LOOP Loop Mode Value Description 0 Normal operating mode. 1 RD is driven by TD, RF is driven by TF and TK drives RK.
PAGE 1134
SAM E70/S70/V70/V71 Family Synchronous Serial Controller (SSC) 44.9.5 SSC Transmit Clock Mode Register Name: Offset: Reset: Property: SSC_TCMR 0x18 0x00000000 Read/Write This register can only be written if the WPEN bit is cleared in the SSC Write Protection Mode Register.
PAGE 1135
SAM E70/S70/V70/V71 Family Synchronous Serial Controller (SSC) Value 2 Name EN_TF_HIGH Description Transmit Clock enabled only if TF High Bit 5 – CKI Transmit Clock Inversion CKI affects only the Transmit Clock and not the Output Clock signal. Value Description 0 The data outputs (Data and Frame Sync signals) are shifted out on Transmit Clock falling edge. The Frame Sync signal input is sampled on Transmit Clock rising edge.
PAGE 1136
SAM E70/S70/V70/V71 Family Synchronous Serial Controller (SSC) 44.9.6 SSC Transmit Frame Mode Register Name: Offset: Reset: Property: SSC_TFMR 0x1C 0x00000000 Read/Write This register can only be written if the WPEN bit is cleared in the SSC Write Protection Mode Register.
PAGE 1137
SAM E70/S70/V70/V71 Family Synchronous Serial Controller (SSC) Bits 11:8 – DATNB[3:0] Data Number per Frame This field defines the number of data words to be transferred after each transfer start, which is equal to (DATNB + 1). Bit 7 – MSBF Most Significant Bit First Value Description 0 The lowest significant bit of the data register is shifted out first in the bit stream. 1 The most significant bit of the data register is shifted out first in the bit stream.
PAGE 1138
SAM E70/S70/V70/V71 Family Synchronous Serial Controller (SSC) 44.9.
PAGE 1139
SAM E70/S70/V70/V71 Family Synchronous Serial Controller (SSC) 44.9.
PAGE 1140
SAM E70/S70/V70/V71 Family Synchronous Serial Controller (SSC) 44.9.
PAGE 1141
SAM E70/S70/V70/V71 Family Synchronous Serial Controller (SSC) 44.9.
PAGE 1142
SAM E70/S70/V70/V71 Family Synchronous Serial Controller (SSC) 44.9.11 SSC Receive Compare 0 Register Name: Offset: Reset: Property: SSC_RC0R 0x38 0x00000000 Read/Write This register can only be written if the WPEN bit is cleared in the SSC Write Protection Mode Register.
PAGE 1143
SAM E70/S70/V70/V71 Family Synchronous Serial Controller (SSC) 44.9.12 SSC Receive Compare 1 Register Name: Offset: Reset: Property: SSC_RC1R 0x3C 0x00000000 Read/Write This register can only be written if the WPEN bit is cleared in the SSC Write Protection Mode Register.
PAGE 1144
SAM E70/S70/V70/V71 Family Synchronous Serial Controller (SSC) 44.9.13 SSC Status Register Name: Offset: Reset: Property: Bit SSC_SR 0x40 0x00000000 Read-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 RXEN R 0 16 TXEN R 0 15 14 13 12 11 RXSYN R 0 10 TXSYN R 0 9 CP1 R 0 8 CP0 R 0 7 6 5 OVRUN R 0 4 RXRDY R 0 3 2 1 TXEMPTY R 0 0 TXRDY R 0 Access Reset Bit Access Reset Bit Access Reset Bit Access Reset Bit 17 – RXEN Receive Enable Value Description 0 Receive is disabled.
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SAM E70/S70/V70/V71 Family Synchronous Serial Controller (SSC) Value 1 Description A compare 0 has occurred since the last read of the Status Register. Bit 5 – OVRUN Receive Overrun Value Description 0 No data has been loaded in SSC_RHR while previous data has not been read since the last read of the Status Register. 1 Data has been loaded in SSC_RHR while previous data has not yet been read since the last read of the Status Register. Bit 4 – RXRDY Receive Ready Value Description 0 SSC_RHR is empty.
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SAM E70/S70/V70/V71 Family Synchronous Serial Controller (SSC) 44.9.14 SSC Interrupt Enable Register Name: Offset: Reset: Property: Bit SSC_IER 0x44 – Write-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 RXSYN W – 10 TXSYN W – 9 CP1 W – 8 CP0 W – 7 6 5 OVRUN W – 4 RXRDY W – 3 2 1 TXEMPTY W – 0 TXRDY W – Access Reset Bit Access Reset Bit Access Reset Bit Access Reset Bit 11 – RXSYN Rx Sync Interrupt Enable Value Description 0 No effect.
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SAM E70/S70/V70/V71 Family Synchronous Serial Controller (SSC) Value 1 Description Enables the Receive Ready Interrupt. Bit 1 – TXEMPTY Transmit Empty Interrupt Enable Value Description 0 No effect. 1 Enables the Transmit Empty Interrupt. Bit 0 – TXRDY Transmit Ready Interrupt Enable Value Description 0 No effect. 1 Enables the Transmit Ready Interrupt. © 2019 Microchip Technology Inc.
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SAM E70/S70/V70/V71 Family Synchronous Serial Controller (SSC) 44.9.15 SSC Interrupt Disable Register Name: Offset: Reset: Property: Bit SSC_IDR 0x48 – Write-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 RXSYN W – 10 TXSYN W – 9 CP1 W – 8 CP0 W – 7 6 5 OVRUN W – 4 RXRDY W – 3 2 1 TXEMPTY W – 0 TXRDY W – Access Reset Bit Access Reset Bit Access Reset Bit Access Reset Bit 11 – RXSYN Rx Sync Interrupt Enable Value Description 0 No effect.
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SAM E70/S70/V70/V71 Family Synchronous Serial Controller (SSC) Value 1 Description Disables the Receive Ready Interrupt. Bit 1 – TXEMPTY Transmit Empty Interrupt Disable Value Description 0 No effect. 1 Disables the Transmit Empty Interrupt. Bit 0 – TXRDY Transmit Ready Interrupt Disable Value Description 0 No effect. 1 Disables the Transmit Ready Interrupt. © 2019 Microchip Technology Inc.
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SAM E70/S70/V70/V71 Family Synchronous Serial Controller (SSC) 44.9.
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SAM E70/S70/V70/V71 Family Synchronous Serial Controller (SSC) Value 1 Description The Receive Ready Interrupt is enabled. Bit 1 – TXEMPTY Transmit Empty Interrupt Mask Value Description 0 The Transmit Empty Interrupt is disabled. 1 The Transmit Empty Interrupt is enabled. Bit 0 – TXRDY Transmit Ready Interrupt Mask Value Description 0 The Transmit Ready Interrupt is disabled. 1 The Transmit Ready Interrupt is enabled. © 2019 Microchip Technology Inc.
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SAM E70/S70/V70/V71 Family Synchronous Serial Controller (SSC) 44.9.
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SAM E70/S70/V70/V71 Family Synchronous Serial Controller (SSC) 44.9.
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SAM E70/S70/V70/V71 Family Inter-IC Sound Controller (I2SC) 45. Inter-IC Sound Controller (I2SC) 45.1 Description The Inter-IC Sound Controller (I2SC) provides a 5-wire, bidirectional, synchronous, digital audio link to external audio devices: I2SC_DI, I2SC_DO, I2SC_WS, I2SC_CK, and I2SC_MCK pins. The I2SC is compliant with the Inter-IC Sound (I2S) bus specification.
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SAM E70/S70/V70/V71 Family Inter-IC Sound Controller (I2SC) 45.3 Block Diagram Figure 45-1. I2SC Block Diagram Bus Matrix CCFG_PCCR Peripheral Clock PMC I2SC 0 PIO Selected Clock GCLK[PID](1) 1 Bus Interface I2SC_MCK I2SC_CK Clocks I2SC_WS Peripheral Bus Bridge DMA Controller Receiver I2SC_DI Transmitter I2SC_DO Events Interrupt Controller (1) For the value of ‘PID’, refer to I2SCx in the table “Peripheral Identifiers”. Related Links 14.1 Peripheral Identifiers 45.
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SAM E70/S70/V70/V71 Family Inter-IC Sound Controller (I2SC) 45.5.3 Clocks The clock for the I2SC bus interface is generated by the Power Management Controller (PMC). I2SC must be disabled before disabling the clock to avoid freezing the I2SC in an undefined state. 45.5.4 DMA Controller The I2SC interfaces to the DMA Controller. Using the I2SC DMA functionality requires the DMA Controller to be programmed first. 45.5.5 Interrupt Sources The I2SC interrupt line is connected to the Interrupt Controller.
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SAM E70/S70/V70/V71 Family Inter-IC Sound Controller (I2SC) Related Links 19. Bus Matrix (MATRIX) 45.6.4 I2S Reception and Transmission Sequence As specified in the I2S protocol, data bits are left-justified in the word select time slot, with the MSB transmitted first, starting one clock period after the transition on the word select line. Figure 45-2.
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SAM E70/S70/V70/V71 Family Inter-IC Sound Controller (I2SC) Example: If the sampling rate is 44.1 kHz with an I2S master clock (I2SC_MCK) ratio of 256, the core frequency must be an integer multiple of 11.2896 MHz. Assuming an integer multiple of 4, the IMCKDIV field must be configured to 4; the field IMCKFS must then be set to 31. The serial clock (I2SC_CK) frequency is 2 × Slot Length times the sample frequency (fs), where Slot Length is defined in the following table. Table 45-2. Slot Length I2SC_MR.
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SAM E70/S70/V70/V71 Family Inter-IC Sound Controller (I2SC) Figure 45-3. I2SC Clock Generation MATRIX.CCFG_PCCR.I2SCxCC I2SC I2SC_CR.CKEN/CKDIS Peripheral Clock 0 GCLK[PID] 1 Selected Clock I2SC_MR.IMCKMODE Clock Divider Clock Enable Clock Divider I2SC_MR.IMCKMODE 0 I2SC_MR.IMCKDIV 1 I2SC_MCK I2SC_MR.IMCKFS I2SC_MR.DATALENGTH I2SC_CK Master 0 i2sck_in Slave 1 Clock Enable I2SC_CR.CKEN/CKDIS I2SC_MR.MODE i2sck_in Internal bit clock Clock Divider I2SC_MR.
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SAM E70/S70/V70/V71 Family Inter-IC Sound Controller (I2SC) 45.6.8 DMA Controller Operation All receiver audio channels can be assigned to a single DMA Controller channel or individual audio channels can be assigned to one DMA Controller channel per audio channel. The same channel assignment choice applies to the transmitter audio channels. Channel assignment is selected by writing to the I2SC_MR.RXDMA and I2SC_MR.TXDMA bits.
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SAM E70/S70/V70/V71 Family Inter-IC Sound Controller (I2SC) Figure 45-5. Slave Transmitter I2SC Application Example I2SC Serial Clock I2SCK Stereo Audio DAC Word Select I2SWS Serial Data Out I2SDO I2SDI Serial Clock Word Select Serial Data Out © 2019 Microchip Technology Inc.
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SAM E70/S70/V70/V71 Family Inter-IC Sound Controller (I2SC) Figure 45-6. Dual Microphone Application Block Diagram I2S Microphone for Left Channel I2SC I2SMCK I2SCK I2SWS Serial Clock Word Select SCK WS L/R Tied to 1 I2SDO I2SDI Serial Data In SD I2S Microphone for Right Channel SCK WS L/R Tied to 0 SD Serial Clock Word Select Left Channel Right Channel Dstart Dend Serial Data In © 2019 Microchip Technology Inc.
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SAM E70/S70/V70/V71 Family Inter-IC Sound Controller (I2SC) Figure 45-7. Codec Application Block Diagram I2SC Master Clock I2SMCK Serial Clock I2SCK Word Select I2SWS Serial Data Out I2SDO Serial Data In I2SDI MCLK I2S Audio Codec BCLK LRCLK/WCLK DAC_SDATA/DIN ADC_SDATA/DOUT Serial Clock Word Select Left Time Slot Dend Dstart Right Time Slot Serial Data Out Serial Data In © 2019 Microchip Technology Inc.
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SAM E70/S70/V70/V71 Family Inter-IC Sound Controller (I2SC) 45.8 Register Summary Offset Name 0x00 I2SC_CR 0x04 0x08 I2SC_MR I2SC_SR 0x0C I2SC_SCR 0x10 I2SC_SSR 0x14 I2SC_IER 0x18 I2SC_IDR 0x1C I2SC_IMR 0x20 I2SC_RHR 0x24 I2SC_THR Bit Pos.
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SAM E70/S70/V70/V71 Family Inter-IC Sound Controller (I2SC) 45.8.1 I2SC Control Register Name: Offset: Property: Bit I2SC_CR 0x00 Write-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 SWRST W – 6 5 TXDIS W – 4 TXEN W – 3 CKDIS W – 2 CKEN W – 1 RXDIS W – 0 RXEN W – Access Reset Bit Access Reset Bit Access Reset Bit Access Reset Bit 7 – SWRST Software Reset Value Description 0 Writing a ’0’ to this bit has no effect.
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SAM E70/S70/V70/V71 Family Inter-IC Sound Controller (I2SC) Value 1 Description Writing a ’1’ to this bit disables the I2SC receiver. Bit I2SC_SR.RXEN is cleared when the receiver is stopped. Bit 0 – RXEN Receiver Enable Value Description 0 Writing a ’0’ to this bit has no effect. 1 Writing a ’1’ to this bit enables the I2SC receiver, if RXDIS is not one. Bit I2SC_SR.RXEN is set when the receiver is activated. © 2019 Microchip Technology Inc.
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SAM E70/S70/V70/V71 Family Inter-IC Sound Controller (I2SC) 45.8.2 I2SC Mode Register Name: Offset: Reset: Property: I2SC_MR 0x04 0x00000000 Read/Write The I2SC_MR must be written when the I2SC is stopped. The proper sequence is to write to I2SC_MR, then write to I2SC_CR to enable the I2SC or to disable the I2SC before writing a new value to I2SC_MR.
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SAM E70/S70/V70/V71 Family Inter-IC Sound Controller (I2SC) Value 47 63 Name M2SF1536 M2SF2048 Description Sample frequency ratio set to 1536 Sample frequency ratio set to 2048 Bits 21:16 – IMCKDIV[5:0] Selected Clock to I2SC Master Clock Ratio I2SC_MCK Master clock output frequency is Selected Clock divided by (IMCKDIV + 1). Refer to the IMCKFS field description. Note: 1. This field is write-only. Always read as ‘0’. 2. Do not write a ‘0’ to this field.
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SAM E70/S70/V70/V71 Family Inter-IC Sound Controller (I2SC) Value 0 1 Name Description SLAVE I2SC_CK and I2SC_WS pin inputs used as bit clock and word select/frame synchronization. MASTER Bit clock and word select/frame synchronization generated by I2SC from MCK and output to I2SC_CK and I2SC_WS pins. Peripheral clock or GCLK is output as master clock on I2SC_MCK if I2SC_MR.IMCKMODE is set. © 2019 Microchip Technology Inc.
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SAM E70/S70/V70/V71 Family Inter-IC Sound Controller (I2SC) 45.8.
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SAM E70/S70/V70/V71 Family Inter-IC Sound Controller (I2SC) Value 0 1 Description This bit is cleared when the corresponding bit in I2SC_SCR is written to ’1’. This bit is set when an overrun error occurs on I2SC_RHR or when the corresponding bit in I2SC_SSR is written to ’1’. Bit 1 – RXRDY Receive Ready Value Description 0 This bit is cleared when I2SC_RHR is read. 1 This bit is set when received data is present in I2SC_RHR.
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SAM E70/S70/V70/V71 Family Inter-IC Sound Controller (I2SC) 45.8.4 I2SC Status Clear Register Name: Offset: Reset: Property: Bit I2SC_SCR 0x0C – Write-only 31 30 29 23 22 21 28 27 26 25 24 20 19 18 17 16 11 10 9 8 Access Reset Bit TXURCH[1:0] Access Reset Bit 15 14 W – W – 13 12 RXORCH[1:0] Access Reset Bit Access Reset 7 6 TXUR W – 5 4 3 2 RXOR W – W – W – 1 0 Bits 21:20 – TXURCH[1:0] Transmit Underrun Per Channel Status Clear Writing a ’0’ has no effect.
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SAM E70/S70/V70/V71 Family Inter-IC Sound Controller (I2SC) 45.8.5 I2SC Status Set Register Name: Offset: Property: Bit I2SC_SSR 0x10 Write-only 31 30 29 23 22 21 28 27 26 25 24 20 19 18 17 16 11 10 9 8 Access Reset Bit TXURCH[1:0] Access Reset Bit 15 14 W – W – 13 12 RXORCH[1:0] Access Reset Bit Access Reset 7 6 TXUR W – 5 4 3 2 RXOR W – W – W – 1 0 Bits 21:20 – TXURCH[1:0] Transmit Underrun Per Channel Status Set Writing a ’0’ has no effect.
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SAM E70/S70/V70/V71 Family Inter-IC Sound Controller (I2SC) 45.8.6 I2SC Interrupt Enable Register Name: Offset: Property: Bit I2SC_IER 0x14 Write-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 TXUR W – 5 TXRDY W – 4 3 2 RXOR W – 1 RXRDY W – 0 Access Reset Bit Access Reset Bit Access Reset Bit Access Reset Bit 6 – TXUR Transmit Underflow Interrupt Enable Value Description 0 Writing a ’0’ to this bit has no effect.
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SAM E70/S70/V70/V71 Family Inter-IC Sound Controller (I2SC) 45.8.7 I2SC Interrupt Disable Register Name: Offset: Property: Bit I2SC_IDR 0x18 Write-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 TXUR W – 5 TXRDY W – 4 3 2 RXOR W – 1 RXRDY W – 0 Access Reset Bit Access Reset Bit Access Reset Bit Access Reset Bit 6 – TXUR Transmit Underflow Interrupt Disable Value Description 0 Writing a ’0’ to this bit has no effect.
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SAM E70/S70/V70/V71 Family Inter-IC Sound Controller (I2SC) 45.8.8 I2SC Interrupt Mask Register Name: Offset: Reset: Property: Bit I2SC_IMR 0x1C 0x00000000 Read-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 TXUR R 0 5 TXRDY R 0 4 3 2 RXOR R 0 1 RXRDY R 0 0 Access Reset Bit Access Reset Bit Access Reset Bit Access Reset Bit 6 – TXUR Transmit Underflow Interrupt Disable Value Description 0 The corresponding interrupt is disabled.
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SAM E70/S70/V70/V71 Family Inter-IC Sound Controller (I2SC) 45.8.
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SAM E70/S70/V70/V71 Family Inter-IC Sound Controller (I2SC) 45.8.
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SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... 46. Universal Synchronous Asynchronous Receiver Transceiver (USART) 46.1 Description The Universal Synchronous Asynchronous Receiver Transceiver (USART) provides one full duplex universal synchronous asynchronous serial link. Data frame format is widely programmable (data length, parity, number of stop bits) to support a maximum of standards. The receiver implements parity error, framing error and overrun error detection.
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SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc...
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SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... 46.3 Block Diagram Figure 46-1. USART Block Diagram USART Interrupt Interrupt Controller PIO Controller USART RXD Receiver Channel RTS (Peripheral) DMA Controller TXD Channel Transmitter CTS DTR Modem Signals Control Bus clock Bridge APB DCD RI User Interface SCK Baud Rate Generator Peripheral clock PMC DSR Peripheral clock/DIV PCK 46.4 I/O Lines Description Table 46-1.
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SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... 46.5 46.5.1 Product Dependencies I/O Lines The pins used for interfacing the USART may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the desired USART pins to their peripheral function. If I/O lines of the USART are not used by the application, they can be used for other purposes by the PIO Controller. All the pins of the modems may or may not be implemented on the USART.
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SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... Figure 46-2. Baud Rate Generator USCLKS Peripheral clock Peripheral clock/DIV PMC.PCKx 0 1 CD 2 16-bit Counter (CLKO = 0) FIDI >1 3 SCK SCK (CLKO = 1) CD Selected Clock 1 Selected Clock 0 0 0 SYNC OVER Sampling Divider 0 1 1 Baud Rate Clock SYNC Sampling Clock USCLKS = 3 46.6.1.
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SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... ...........continued Source Clock (MHz) Expected Baud Rate (bit/s) Calculation Result CD Actual Baud Rate (bit/s) Error 25,000,000 38,400 40.69 40 38,109.76 0.76% 32,000,000 38,400 52.08 52 38,461.54 0.16% 32,768,000 38,400 53.33 53 38,641.51 0.63% 33,000,000 38,400 53.71 54 38,194.44 0.54% 40,000,000 38,400 65.10 65 38,461.54 0.16% 50,000,000 38,400 81.38 81 38,580.25 0.
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SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... When the value of US_BRGR.FP is greater than '0', the SCK (oversampling clock) generates non-constant duty cycles. The SCK high duration is increased by “selected clock” period from time to time. The duty cycle depends on the value of USART_BRGR.CD. WARNING 46.6.1.3 Baud Rate in Synchronous Mode or SPI Mode If the USART is programmed to operate in Synchronous mode, the selected clock is divided by the value of US_BRGR.CD.
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SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... 16 23.25 34.87 46.5 69.75 93 116.2 32 48 64 96 128 32 11.62 17.43 23.25 34.87 46.5 58.13 16 24 32 48 64 12 31 46.5 62 93 124 155 42.66 64 85.33 128 170.6 20 18.6 27.9 37.2 55.8 74.4 93 25.6 38.4 51.2 76.8 102.4 If the USART is configured in ISO7816 mode, the clock selected by US_MR.USCLKS is first divided by the value programmed in US_BRGR.CD.
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SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... The number of data bits is configured in the US_MR.CHRL and the US_MR.MODE9. Nine bits are selected by writing a ‘1’ to US_MR.MODE9 regardless of the CHRL field. The parity is selected by US_MR.PAR. Even, odd, space, marked or none parity bit can be configured. US_MR.MSBF configures which data bit is sent first. If written to ‘1’, the most significant bit is sent first. If written to ‘0’, the less significant bit is sent first.
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SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... preamble waveform is not generated prior to any character. The preamble pattern is chosen among the following sequences: ALL_ONE, ALL_ZERO, ONE_ZERO or ZERO_ONE by configuring US_MAN.TX_PP. US_MAN.TX_PL is used to configure the preamble length. Figure 46-8 illustrates and defines the valid patterns. To improve flexibility, the encoding scheme can be configured using US_MAN.TX_MPOL.
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SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... Figure 46-9. Start Frame Delimiter Preamble Length is set to 0 Manchester Encoded Data Manchester Encoded Data Manchester Encoded Data SFD DATA TXD SFD One bit start frame delimiter DATA TXD Command Sync start frame delimiter SFD DATA TXD Data Sync start frame delimiter 46.6.3.2.1 Drift Compensation Drift compensation is available only in 16X Oversampling mode.
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SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... Figure 46-11. Asynchronous Start Detection Baud Rate Clock Sampling Clock (x16) RXD Sampling 1 2 3 4 5 6 7 8 1 2 3 4 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 D0 Sampling Start Detection RXD Sampling 1 2 3 4 5 6 0 1 Start Rejection 7 Figure 46-12.
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SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... The receiver is activated and starts preamble and frame delimiter detection, sampling the data at one quarter and then three quarters. If a valid preamble pattern or start frame delimiter is detected, the receiver continues decoding with the same synchronization. If the stream does not match a valid pattern or a valid start frame delimiter, the receiver resynchronizes on the next valid edge.
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SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... Figure 46-16.
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SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... Figure 46-18. FSK Modulator Output 1 0 0 1 NRZ Stream Manchester Encoded Data Default Polarity Unipolar Output TXD FSK Modulator Output Upstream Frequencies [F0, F0+offset] 46.6.3.6 Synchronous Receiver In Synchronous mode (US_MR.SYNC = 1), the receiver samples the RXD signal on each rising edge of the baud rate clock. If a low level is detected, it is considered as a start.
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SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... 46.6.3.8 Parity The USART supports five Parity modes. The PAR field also enables Multidrop mode, see “Multidrop Mode”. Even and odd parity bit generation and error detection are supported. The configuration is done in US_MR.PAR. If even parity is selected, the parity generator of the transmitter drives the parity bit to 0 if a number of 1s in the character data bit is even, and to 1 if the number of 1s is odd.
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SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... The transmitter sends an address byte (parity bit set) when US_CR.SENDA = 1. In this case, the next byte written to US_THR is transmitted as an address. Any character written in the US_THR without having written SENDA is transmitted normally with the parity at 0. 46.6.3.10 Transmitter Timeguard The timeguard feature enables the USART interface with slow remote devices.
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SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... The timeout delay period (during which the receiver waits for a new character) is programmed in the TO field of the Receiver Timeout register (US_RTOR). If TO is written to ‘0’, the Receiver Timeout is disabled and no timeout is detected. US_CSR.TIMEOUT remains at ‘0’. Otherwise, the receiver loads a 16-bit counter with the value programmed in US_RTOR.TO.
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SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... Figure 46-24. Framing Error Status Baud Rate Clock RXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit RSTSTA = 1 Write US_CR FRAME RXRDY 46.6.3.13 Transmit Break The user can request the transmitter to generate a break condition on the TXD line. A break condition drives the TXD line low during at least one complete character. It appears the same as a 0x00 character sent with the parity and the stop bits at 0.
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SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... Figure 46-25. Break Transmission Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit STTBRK = 1 Write US_CR Break Transmission End of Break STPBRK = 1 TXRDY TXEMPTY 46.6.3.14 Receive Break The receiver detects a break condition when all data, parity and stop bits are low. This corresponds to detecting a framing error with data to 0x00, but FRAME remains low.
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SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... Figure 46-28. Transmitter Behavior when Operating with Hardware Handshaking CTS TXD 46.6.4 ISO7816 Mode The USART features an ISO7816-compatible operating mode. This mode permits interfacing with smart cards and Security Access Modules (SAM) communicating through an ISO7816 link. Both T = 0 and T = 1 protocols defined by the ISO7816 specification are supported. Setting the USART in ISO7816 mode is performed by writing US_MR.
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SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... Figure 46-30. T = 0 Protocol without Parity Error Baud Rate Clock RXD Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Guard Guard Next Bit Time 1 Time 2 Start Bit Figure 46-31. T = 0 Protocol with Parity Error Baud Rate Clock Error I/O Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Guard Bit Time 1 Guard Start Time 2 Bit D0 D1 Repetition 46.6.4.2.
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SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... The IrDA mode is enabled by writing the value 0x8 to US_MR.USART_MODE. The IrDA Filter register (US_IF) is used to configure the demodulator filter. The USART transmitter and receiver operate in a normal Asynchronous mode and all parameters are accessible. Note that the modulator and the demodulator are activated. Figure 46-32.
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SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... Table 46-10. IrDA Baud Rate Error Peripheral Clock Baud Rate (bit/s) CD Baud Rate Error Pulse Time (μs) 3,686,400 115,200 2 0.00% 1.63 20,000,000 115,200 11 1.38% 1.63 32,768,000 115,200 18 1.25% 1.63 40,000,000 115,200 22 1.38% 1.63 3,686,400 57,600 4 0.00% 3.26 20,000,000 57,600 22 1.38% 3.26 32,768,000 57,600 36 1.25% 3.26 40,000,000 57,600 43 0.93% 3.26 3,686,400 38,400 6 0.
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SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... Figure 46-34. IrDA Demodulator Operations MCK RXD Counter Value Receiver Input 6 5 4 3 Pulse rejected 2 6 6 5 4 3 2 1 0 Pulse accepted The programmed value in the US_IF register must always meet the following criterion: tperipheral clock × (IRDA_FILTER + 3) < 1.
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SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... 46.6.7 Modem Mode The USART features the Modem mode, which enables control of the signals DTR (Data Terminal Ready), DSR (Data Set Ready), RTS (Request to Send), CTS (Clear to Send), DCD (Data Carrier Detect), and RI (Ring Indicator). While operating in Modem mode, the USART behaves as a DTE (Data Terminal Equipment) as it drives DTR and RTS and can detect level change on DSR, DCD, CTS, and RI.
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SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... 46.6.8.1 Modes of Operation The USART can operate in SPI Master mode or in SPI Slave mode. SPI Master mode is enabled by writing 0xE to US_MR.USART_MODE.
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SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... ...........continued SPI Bus Protocol Mode CPOL CPHA 2 1 1 3 1 0 Figure 46-37. SPI Transfer Format (CPHA = 1, 8 bits per transfer) 1 SCK cycle (for reference) 2 3 4 6 5 7 8 SCK (CPOL = 0) SCK (CPOL = 1) MOSI SPI Master ->TXD SPI Slave -> RXD MISO SPI Master -> RXD SPI Slave -> TXD MSB MSB 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB 6 7 8 NSS SPI Master -> RTS SPI Slave -> CTS Figure 46-38.
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SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... The chip select line is deasserted for a period equivalent to three bits between the transmission of two data. The transmitter reports two status bits in US_CSR: TXRDY (Transmitter Ready), which indicates that US_THR is empty and TXEMPTY, which indicates that all the characters written in US_THR have been processed.
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SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... • • LIN master node (USART_MODE = 0xA) LIN slave node (USART_MODE = 0xB) In order to avoid unpredictable behavior, any change of the LIN node configuration must be followed by a software reset of the transmitter and of the receiver (except the initial node configuration after a hardware reset). (See “Receiver and Transmitter Control”.) 46.6.9.
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SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... 46.6.9.7 Header Reception (Slave Node Configuration) All the LIN frames start with a header which is sent by the master node and consists of a Synch Break Field, Synch Field and Identifier Field. In slave node configuration, the frame handling starts with the reception of the header. The USART uses a break detection threshold of 11 nominal bit times at the actual baud rate.
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SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... Once the Synch Field has been entirely received, the clock divider (LINCD) and the fractional part (LINFP) are updated in the LIN Baud Rate register (US_LINBRR) with the computed values, if the Synchronization is not disabled by the SYNCDIS bit in the LIN Mode register (US_LINMR).
PAGE 1211
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... • • • Baud rate = 20 kbit/s, OVER = 1 (Oversampling 8X) => fNom(min) = 1.47 MHz Baud rate = 1 kbit/s, OVER = 0 (Oversampling 16X) => fNom(min) = 132 kHz Baud rate = 1 kbit/s, OVER = 1 (Oversampling 8X) => fNom(min) = 74 kHz 46.6.9.9 Identifier Parity A protected identifier consists of two subfields: the identifier and the identifier parity.
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SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... NACT(slave2)=PUBLISH 46.6.9.11 Response Data Length The LIN response data length is the number of data fields (bytes) of the response excluding the checksum. The response data length can either be configured by the user or be defined automatically by bits 4 and 5 of the Identifier (compatibility to LIN Specification 1.1). The user can choose between these two modes using the US_LINMR.
PAGE 1213
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... If the Checksum is sent (CHKDIS = 0): tHeader_Nominal = 34 × tbit tResponse_Nominal = 10 × (NData + 1) × tbit tFrame_Maximum = 1.4 × (tHeader_Nominal + tResponse_Nominal + 1)(1) tFrame_Maximum = 1.4 × (34 + 10 × (DLC + 1 + 1) + 1) × tbit tFrame_Maximum = (77 + 14 × DLC) × tbit If the Checksum is not sent (CHKDIS = 1): tHeader_Nominal = 34 × tbit tResponse_Nominal = 10 × NData × tbit tFrame_Maximum = 1.
PAGE 1214
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... 46.6.9.14.5 Slave Not Responding Error This error is generated in master of slave node configuration, when the USART expects a response from another node (NACT = SUBSCRIBE) but no valid message appears on the bus within the time given by the maximum length of the message frame, tFrame_Maximum (see Frame Slot Mode). This error is disabled if the USART does not expect any message (NACT = PUBLISH or NACT = IGNORE).
PAGE 1215
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... Figure 46-45. Master Node Configuration, NACT = PUBLISH Frame slot = tFrame_Maximum Frame Header Break Synch Data3 Interframe space Response space Protected Identifier Response Data 1 Data N-1 Data N Checksum TXRDY FSDIS=1 FSDIS=0 RXRDY Write US_LINIR Write US_THR Data 1 Data 2 Data 3 Data N LINTC Figure 46-46.
PAGE 1216
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... • Write NACT, PARDIS, CHKDIS, CHKTYPE, DLCM and DLC in US_LINMR to configure the frame transfer. IMPORTANT: If the NACT configuration for this frame is PUBLISH, the US_LINMR must be written with NACT = PUBLISH even if this field is already correctly configured, in order to set the TXREADY flag and the corresponding write transfer request.
PAGE 1217
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... Figure 46-50. Slave Node Configuration, NACT = IGNORE Break Synch Protected Identifier Data 1 Data N-1 Data N Checksum TXRDY RXRDY LINIDRX Read US_LINID Read US_RHR LINTC 46.6.9.16 LIN Frame Handling with the DMAC The USART can be used in association with the DMAC in order to transfer data directly into/from the on- and off-chip memories without any processor intervention.
PAGE 1218
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... Figure 46-52. Master Node with DMAC (PDCM = 0) WRITE BUFFER WRITE BUFFER IDENTIFIER IDENTIFIER NODE ACTION = PUBLISH NODE ACTION = SUBSCRIBE APB bus DATA 0 APB bus READ BUFFER (Peripheral) DMA Controller USART LIN Controller TXRDY DATA 0 (Peripheral) DMA Controller RXRDY USART LIN Controller TXRDY DATA N DATA N 46.6.9.16.2 Slave Node Configuration In this configuration, the DMAC transfers only the DATA.
PAGE 1219
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... each bit period and reloaded each time a new character is received. If the counter reaches 0, US_CSR.TIMEOUT rises. If US_CR.STTTO is written to ‘1’, the counter clock is stopped until a first character is received. If US_CR.RETTO is written to ‘1’, the counter starts counting down immediately from the value TO. Table 46-14. Receiver Timeout Programming LIN Specification Baud Rate Timeout period US_RTOR.TO 2.
PAGE 1220
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... 46.6.10.1 Mode of Operation To configure the USART to act as a LON node, the value 0x9 must be written to US_MR.USART_MODE. To avoid unpredictable behavior, any change of the LON node configuration must be preceded by a software reset of the transmitter and the receiver (except the initial node configuration after a hardware reset) and followed by a transmitter/receiver enable. See Section 7.10.2. 46.6.10.
PAGE 1221
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... Figure 46-57. Preamble Patterns Differential Manchester encoded data DATA TXD 8-bit "ALL_ONE" Preamble (bit-sync) Differential Manchester encoded data byte-sync DATA TXD 8-bit "ALL_ZERO" Preamble (bit-sync) byte-sync 46.6.10.5.3 Preamble Reception LON received frames begin with a preamble of variable length.
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SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... 46.6.10.6.2 comm_type In the CEA-709 standard, two communication configurations are defined and configurable through the comm_type variable. The comm_type variable value can be set in the USART LON Mode register (US_LONMR) through the COMMT bit.
PAGE 1223
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... 46.6.10.7 LON Node Backlog Estimation As defined in the CEA-709 standard, the LON node maintains its own backlog estimation. The node backlog estimation is initially set to 1, will always be greater than 1 and will never exceed 63. If the node backlog estimation exceeds the maximum backlog value, the backlog value is set to 63 and a backlog overflow error flag is set (LBLOVFE flag).
PAGE 1224
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... 46.6.10.8.5 Priority Slots On a channel by channel basis, the protocol supports optional priority. Priority slots, if any, follow immediately after the Beta1 period that follows the transmission of a packet (see Figure 46-59). The number of priority slots per channel ranges from 0 to 127.
PAGE 1225
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... Figure 46-60. Bit Resynchronization Oversampling 16X Clock RXD Sampling point Expected edge Synchro Error Synchro Jump Synchro Error 46.6.10.11 LON Frame Handling 46.6.10.11.1 Sending A Frame 1. Write TXEN and RXEN in US_CR to enable both the transmitter and the receiver. 2. Write USART_MODE in US_MR to select the LON mode configuration. 3. Write CD and FP in US_BRGR to configure the baud rate. 4.
PAGE 1226
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... 6. Write RXIDLEV and RX_PL in US_MAN to indicate the receiver line value and select the preamble pattern to use. 7. Wait until RXRDY in US_CSR rises. 8. Read RCHR in US_RHR. 9. If all the data and the two CRC bytes have not been read, redo the two previous steps. 10. Wait until LRXD in US_CSR rises. 11. Check the LON errors. 12. Figure 46-62.
PAGE 1227
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... Figure 46-64. DMAM = 0 WRITE BUFFER READ BUFFER L2HDR L2HDR NODE ACTION = TRANSMIT NODE ACTION = RECEIVE APB bus DATA 0 DMA APB bus DATA 0 USART LON Controller USART LON Controller DMA TXRDY RXRDY DATA N DATA N 46.6.10.12.
PAGE 1228
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... Figure 46-66. Normal Mode Configuration Receiver RXD Transmitter TXD 46.6.11.2 Automatic Echo Mode Automatic Echo mode allows bit-by-bit retransmission. When a bit is received on the RXD pin, it is sent to the TXD pin, as shown in the following figure. Programming the transmitter has no effect on the TXD pin. The RXD pin is still connected to the receiver input, thus the receiver remains active. Figure 46-67.
PAGE 1229
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc...
PAGE 1230
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... 46.7 Register Summary Offset Name 0x00 US_CR 0x00 US_CR (SPI_MODE) 0x04 US_MR 0x04 US_MR (SPI_MODE) 0x08 US_IER 0x08 US_IER (SPI_MODE) 0x08 US_IER (LIN_MODE) 0x08 US_IER (LON_MODE) 0x0C US_IDR 0x0C US_IDR (SPI_MODE) 0x0C US_IDR (LIN_MODE) 0x0C US_IDR (LON_MODE) 0x10 US_IMR 0x10 US_IMR (SPI_MODE) Bit Pos.
PAGE 1231
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... ...........continued Offset Name 0x10 US_IMR (LIN_MODE) 0x10 US_IMR (LON_MODE) 0x14 US_CSR 0x14 US_CSR (SPI_MODE) 0x14 US_CSR (LIN_MODE) 0x14 0x18 US_CSR (LON_MODE) US_RHR 0x1C US_THR 0x20 US_BRGR 0x24 US_RTOR 0x28 US_TTGR 0x28 US_TTGR (LON_MODE) 0x2C ... 0x3F Reserved 0x40 US_FIDI 0x40 US_FIDI (LON_MODE) Bit Pos.
PAGE 1232
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... ...........continued Offset Name Bit Pos. US_NER 7:0 15:8 23:16 31:24 NB_ERRORS[7:0] 0x44 0x48 ...
PAGE 1233
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... ...........continued Offset Name 0x80 US_IDTTX 0x84 US_IDTRX 0x88 US_ICDIFF 0x8C ... 0xE3 Reserved 0xE4 0xE8 US_WPMR US_WPSR Bit Pos. 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 © 2019 Microchip Technology Inc.
PAGE 1234
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... 46.7.1 USART Control Register Name: Offset: Property: US_CR 0x0000 Write-only For SPI control, see “USART Control Register (SPI_MODE)”.
PAGE 1235
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... Value 0 1 Description No effect. Drives the pin DTR to 0. Bit 15 – RETTO Start Timeout Immediately Value Description 0 No effect 1 Immediately restarts timeout period. Bit 14 – RSTNACK Reset Non Acknowledge Value Description 0 No effect 1 Resets NACK in US_CSR. Bit 13 – RSTIT Reset Iterations Value Description 0 No effect. 1 Resets ITER in US_CSR. No effect if the ISO7816 is not enabled.
PAGE 1236
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... Bit 5 – RXDIS Receiver Disable Value Description 0 No effect. 1 Disables the receiver. Bit 4 – RXEN Receiver Enable Value Description 0 No effect. 1 Enables the receiver, if RXDIS is 0. Bit 3 – RSTTX Reset Transmitter Value Description 0 No effect. 1 Resets the transmitter. Bit 2 – RSTRX Reset Receiver Value Description 0 No effect. 1 Resets the receiver. © 2019 Microchip Technology Inc.
PAGE 1237
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... 46.7.2 USART Control Register (SPI_MODE) Name: Offset: Property: US_CR (SPI_MODE) 0x0000 Write-only This configuration is relevant only if USART_MODE = 0xE or 0xF in the USART Mode Register.
PAGE 1238
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... Value 0 1 Description No effect. Disables the receiver. Bit 4 – RXEN Receiver Enable Value Description 0 No effect. 1 Enables the receiver, if RXDIS is 0. Bit 3 – RSTTX Reset Transmitter Value Description 0 No effect. 1 Resets the transmitter. Bit 2 – RSTRX Reset Receiver Value Description 0 No effect. 1 Resets the receiver. © 2019 Microchip Technology Inc.
PAGE 1239
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... 46.7.3 USART Mode Register Name: Offset: Reset: Property: US_MR 0x0004 0x0 Read/Write This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register. For SPI configuration, see “USART Mode Register (SPI_MODE)”.
PAGE 1240
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... Value 0 1 Description The data field transmitted on TXD line is the same as the one written in US_THR or the content read in US_RHR is the same as RXD line. Normal mode of operation. The data field transmitted on TXD line is inverted (voltage polarity only) compared to the value written on US_THR or the content read in US_RHR is inverted compared to what is received on RXD line (or ISO7816 IO line).
PAGE 1241
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... Value 0 1 2 Name 1_BIT 1_5_BIT 2_BIT Description 1 stop bit 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) 2 stop bits Bits 11:9 – PAR[2:0] Parity Type Value Name 0 EVEN 1 ODD 2 SPACE 3 MARK 4 NO 6 MULTIDROP Description Even parity Odd parity Parity forced to 0 (Space) Parity forced to 1 (Mark) No parity Multidrop mode Bit 8 – SYNC Synchronous Mode Select Value Description 0 USART operates in Asynchronous mode.
PAGE 1242
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... 46.7.4 USART Mode Register (SPI_MODE) Name: Offset: Reset: Property: US_MR (SPI_MODE) 0x0004 0x0 Read/Write This configuration is relevant only if USART_MODE = 0xE or 0xF in the USART Mode Register. This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register.
PAGE 1243
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... Value 1 Description Data is captured on the leading edge of SPCK and changed on the following edge of SPCK.
PAGE 1244
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... 46.7.5 USART Interrupt Enable Register Name: Offset: Property: US_IER 0x0008 Write-only For SPI specific configuration, see “USART Interrupt Enable Register (SPI_MODE)”. For LIN specific configuration, see “USART Interrupt Enable Register (LIN_MODE)”. For LON specific configuration, see “USART Interrupt Enable Register (LON_MODE)”.
PAGE 1245
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... Bit 5 – OVRE Overrun Error Interrupt Enable Bit 2 – RXBRK Receiver Break Interrupt Enable Bit 1 – TXRDY TXRDY Interrupt Enable Bit 0 – RXRDY RXRDY Interrupt Enable © 2019 Microchip Technology Inc.
PAGE 1246
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... 46.7.6 USART Interrupt Enable Register (SPI_MODE) Name: Offset: Property: US_IER (SPI_MODE) 0x0008 Write-only This configuration is relevant only if USART_MODE = 0xE or 0xF in the USART Mode Register. The following configuration values are valid for all listed bit names of this register: 0: No effect 1: Enables the corresponding interrupt.
PAGE 1247
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... 46.7.7 USART Interrupt Enable Register (LIN_MODE) Name: Offset: Property: US_IER (LIN_MODE) 0x0008 Write-only This configuration is relevant only if USART_MODE = 0xA or 0xB in the USART Mode Register. The following configuration values are valid for all listed bit names of this register: 0: No effect 1: Enables the corresponding interrupt.
PAGE 1248
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... Bit 7 – PARE Parity Error Interrupt Enable Bit 6 – FRAME Framing Error Interrupt Enable Bit 5 – OVRE Overrun Error Interrupt Enable Bit 1 – TXRDY TXRDY Interrupt Enable Bit 0 – RXRDY RXRDY Interrupt Enable © 2019 Microchip Technology Inc.
PAGE 1249
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... 46.7.8 USART Interrupt Enable Register (LON_MODE) Name: Offset: Property: US_IER (LON_MODE) 0x0008 Write-only This register is relevant only if USART_MODE = 0x9 in the USART Mode Register. The following configuration values are valid for all listed bit names of this register: 0: No effect 1: Enables the corresponding interrupt.
PAGE 1250
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... 46.7.9 USART Interrupt Disable Register Name: Offset: Property: US_IDR 0x000C Write-only For SPI specific configuration, see “USART Interrupt Disable Register (SPI_MODE)”. For LIN specific configuration, see “USART Interrupt Disable Register (LIN_MODE)”. For LON specific configuration, see “USART Interrupt Disable Register (LON_MODE)”.
PAGE 1251
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... Bit 5 – OVRE Overrun Error Interrupt Enable Bit 2 – RXBRK Receiver Break Interrupt Disable Bit 1 – TXRDY TXRDY Interrupt Disable Bit 0 – RXRDY RXRDY Interrupt Disable © 2019 Microchip Technology Inc.
PAGE 1252
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... 46.7.10 USART Interrupt Disable Register (SPI_MODE) Name: Offset: Property: US_IDR (SPI_MODE) 0x000C Write-only This configuration is relevant only if USART_MODE = 0xE or 0xF in the USART Mode Register. The following configuration values are valid for all listed bit names of this register: 0: No effect 1: Disables the corresponding interrupt.
PAGE 1253
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... 46.7.11 USART Interrupt Disable Register (LIN_MODE) Name: Offset: Property: US_IDR (LIN_MODE) 0x000C Write-only This configuration is relevant only if USART_MODE = 0xA or 0xB in the USART Mode Register. The following configuration values are valid for all listed bit names of this register: 0: No effect 1: Disables the corresponding interrupt.
PAGE 1254
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... Bit 8 – TIMEOUT Timeout Interrupt Disable Bit 7 – PARE Parity Error Interrupt Disable Bit 6 – FRAME Framing Error Interrupt Disable Bit 5 – OVRE Overrun Error Interrupt Disable Bit 1 – TXRDY TXRDY Interrupt Disable Bit 0 – RXRDY RXRDY Interrupt Disable © 2019 Microchip Technology Inc.
PAGE 1255
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... 46.7.12 USART Interrupt Disable Register (LON_MODE) Name: Offset: Property: US_IDR (LON_MODE) 0x000C Write-only This configuration is relevant only if USART_MODE = 0x9 in the USART Mode Register. The following configuration values are valid for all listed bit names of this register: 0: No effect 1: Disables the corresponding interrupt.
PAGE 1256
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... 46.7.13 USART Interrupt Mask Register Name: Offset: Reset: Property: US_IMR 0x0010 0x0 Read-only For SPI specific configuration, see “USART Interrupt Mask Register (SPI_MODE)”. For LIN specific configuration, see “USART Interrupt Mask Register (LIN_MODE)”. For LON specific configuration, see “USART Interrupt Mask Register (LON_MODE)”.
PAGE 1257
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... Bit 6 – FRAME Framing Error Interrupt Mask Bit 5 – OVRE Overrun Error Interrupt Mask Bit 2 – RXBRK Receiver Break Interrupt Mask Bit 1 – TXRDY TXRDY Interrupt Mask Bit 0 – RXRDY RXRDY Interrupt Mask © 2019 Microchip Technology Inc.
PAGE 1258
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... 46.7.14 USART Interrupt Mask Register (SPI_MODE) Name: Offset: Reset: Property: US_IMR (SPI_MODE) 0x0010 0x0 Read-only This configuration is relevant only if USART_MODE = 0xE or 0xF in the USART Mode Register. The following configuration values are valid for all listed bit names of this register: 0: The corresponding interrupt is not enabled. 1: The corresponding interrupt is enabled.
PAGE 1259
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... 46.7.15 USART Interrupt Mask Register (LIN_MODE) Name: Offset: Reset: Property: US_IMR (LIN_MODE) 0x0010 0x0 Read-only This configuration is relevant only if USART_MODE = 0xA or 0xB in the USART Mode Register. The following configuration values are valid for all listed bit names of this register: 0: The corresponding interrupt is not enabled. 1: The corresponding interrupt is enabled.
PAGE 1260
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... Bit 8 – TIMEOUT Timeout Interrupt Mask Bit 7 – PARE Parity Error Interrupt Mask Bit 6 – FRAME Framing Error Interrupt Mask Bit 5 – OVRE Overrun Error Interrupt Mask Bit 1 – TXRDY TXRDY Interrupt Mask Bit 0 – RXRDY RXRDY Interrupt Mask © 2019 Microchip Technology Inc.
PAGE 1261
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... 46.7.16 USART Interrupt Mask Register (LON_MODE) Name: Offset: Reset: Property: US_IMR (LON_MODE) 0x0010 0x0 Read-only This configuration is relevant only if USART_MODE = 0x9 in the USART Mode Register. The following configuration values are valid for all listed bit names of this register: 0: The corresponding interrupt is not enabled. 1: The corresponding interrupt is enabled.
PAGE 1262
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... 46.7.17 USART Channel Status Register Name: Offset: Reset: Property: US_CSR 0x0014 0x0 Read-only For SPI specific configuration, see “USART Channel Status Register (SPI_MODE)”. For LIN specific configuration, see “USART Channel Status Register (LIN_MODE)”. For LON specific configuration, see “USART Channel Status Register (LON_MODE)”.
PAGE 1263
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... Bit 19 – CTSIC Clear to Send Input Change Flag (cleared on read) Value Description 0 No input change has been detected on the CTS pin since the last read of US_CSR. 1 At least one input change has been detected on the CTS pin since the last read of US_CSR. Bit 18 – DCDIC Data Carrier Detect Input Change Flag (cleared on read) Value Description 0 No input change has been detected on the DCD pin since the last read of US_CSR.
PAGE 1264
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... Bit 2 – RXBRK Break Received/End of Break (cleared by writing a one to bit US_CR.RSTSTA) Value Description 0 No break received or end of break detected since the last RSTSTA. 1 Break received or end of break detected since the last RSTSTA.
PAGE 1265
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... 46.7.18 USART Channel Status Register (SPI_MODE) Name: Offset: Reset: Property: US_CSR (SPI_MODE) 0x0014 0x0 Read-only This configuration is relevant only if USART_MODE = 0xE or 0xF in the USART Mode Register.
PAGE 1266
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... Value 0 1 Description A character is in the US_THR waiting to be transferred to the Transmit Shift Register or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1. There is no character in the US_THR. Bit 0 – RXRDY Receiver Ready (cleared by reading US_RHR) Value Description 0 No complete character has been received since the last read of US_RHR or the receiver is disabled.
PAGE 1267
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... 46.7.19 USART Channel Status Register (LIN_MODE) Name: Offset: Reset: Property: US_CSR (LIN_MODE) 0x0014 0x0 Read-only This configuration is relevant only if USART_MODE = 0xA or 0xB in the USART Mode Register.
PAGE 1268
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... Value 1 Description The USART is configured as a slave node and a LIN Inconsistent synch field error has been detected since the last RSTSTA. Bit 25 – LINBE LIN Bit Error (cleared by writing a one to bit US_CR.RSTSTA) Value Description 0 No bit error has been detected since the last RSTSTA. 1 A bit error has been detected since the last RSTSTA. Bit 23 – LINBLS LIN Bus Line Status Value Description 0 LIN bus line is set to 0.
PAGE 1269
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... Bit 5 – OVRE Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) Value Description 0 No overrun error has occurred since the last RSTSTA. 1 At least one overrun error has occurred since the last RSTSTA. Bit 1 – TXRDY Transmitter Ready (cleared by writing US_THR) Value Description 0 A character is in the US_THR waiting to be transferred to the Transmit Shift Register or the transmitter is disabled.
PAGE 1270
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... 46.7.20 USART Channel Status Register (LON_MODE) Name: Offset: Reset: Property: US_CSR (LON_MODE) 0x0014 0x0 Read-only This configuration is relevant only if USART_MODE = 0x9 in the USART Mode Register.
PAGE 1271
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... Value 0 1 Description No LON underrun error has occurred since the last RSTSTA. At least one LON underrun error has occurred since the last RSTSTA. Bit 9 – TXEMPTY Transmitter Empty (cleared by writing US_THR) Value Description 0 There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled. 1 There are no characters in US_THR, nor in the Transmit Shift Register.
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SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... 46.7.21 USART Receive Holding Register Name: Offset: Reset: Property: Bit US_RHR 0x0018 0x0 Read-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RXSYNH 14 13 12 11 10 9 8 RXCHR[8] Access Reset Bit Access Reset Bit Access Reset 0 Bit 7 0 6 5 4 3 2 1 0 0 0 0 0 RXCHR[7:0] Access Reset 0 0 0 0 Bit 15 – RXSYNH Received Sync Value Description 0 Last character received is a data.
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SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... 46.7.22 USART Transmit Holding Register Name: Offset: Property: Bit US_THR 0x001C Write-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 TXSYNH 14 13 12 11 10 9 8 TXCHR[8] 7 6 5 4 3 2 1 0 Access Reset Bit Access Reset Bit Access Reset Bit TXCHR[7:0] Access Reset Bit 15 – TXSYNH Sync Field to be Transmitted Value Description 0 The next character sent is encoded as a data.
PAGE 1274
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... 46.7.23 USART Baud Rate Generator Register Name: Offset: Reset: Property: US_BRGR 0x0020 0x0 Read/Write This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register.
PAGE 1275
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... 46.7.24 USART Receiver Timeout Register Name: Offset: Reset: Property: US_RTOR 0x0024 0x0 Read/Write This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register.
PAGE 1276
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... 46.7.25 USART Transmitter Timeguard Register Name: Offset: Reset: Property: US_TTGR 0x0028 0x0 Read/Write This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register. For LON specific configuration, see “USART Transmitter Timeguard Register (LON_MODE)”.
PAGE 1277
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... 46.7.26 USART Transmitter Timeguard Register (LON_MODE) Name: Offset: Reset: Property: US_TTGR (LON_MODE) 0x0028 0x0 Read/Write This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register.
PAGE 1278
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... 46.7.27 USART FI DI RATIO Register Name: Offset: Reset: Property: US_FIDI 0x0040 0x174 Read/Write This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register. For LON specific configuration, see “USART Transmitter Timeguard Register (LON_MODE)”.
PAGE 1279
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... 46.7.28 USART FI DI RATIO Register (LON_MODE) Name: Offset: Reset: Property: US_FIDI (LON_MODE) 0x0040 0x174 Read/Write This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register.
PAGE 1280
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... 46.7.29 USART Number of Errors Register Name: Offset: Reset: Property: US_NER 0x0044 0x0 Read-only This register is relevant only if USART_MODE = 0x4 or 0x6 in the USART Mode Register.
PAGE 1281
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... 46.7.30 USART IrDA Filter Register Name: Offset: Reset: Property: US_IF 0x004C 0x0 Read/Write This register is relevant only if USART_MODE = 0x8 in the USART Mode Register. This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register.
PAGE 1282
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... 46.7.31 USART Manchester Configuration Register Name: Offset: Reset: Property: US_MAN 0x0050 0xB30011004 Read/Write This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register.
PAGE 1283
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... Value 0 1–15 Description The receiver preamble pattern detection is disabled The detected preamble length is RX_PL × Bit Period Bit 12 – TX_MPOL Transmitter Manchester Polarity Value Description 0 Logic zero is coded as a zero-to-one transition, Logic one is coded as a one-to-zero transition. 1 Logic zero is coded as a one-to-zero transition, Logic one is coded as a zero-to-one transition.
PAGE 1284
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... 46.7.32 USART LIN Mode Register Name: Offset: Reset: Property: US_LINMR 0x0054 0x0 Read/Write This register is relevant only if USART_MODE = 0xA or 0xB in the USART Mode Register.
PAGE 1285
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... Value 1 Description The response data length is defined by bits 5 and 6 of the identifier (IDCHR in US_LINIR). Bit 4 – CHKTYP Checksum Type Value Description 0 LIN 2.0 “enhanced” checksum 1 LIN 1.3 “classic” checksum Bit 3 – CHKDIS Checksum Disable Value Description 0 In master node configuration, the checksum is computed and sent automatically. In slave node configuration, the checksum is checked automatically.
PAGE 1286
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... 46.7.33 USART LIN Identifier Register Name: Offset: Reset: Property: US_LINIR 0x0058 0x0 Read/Write(1) This register is relevant only if USART_MODE = 0xA or 0xB in the USART Mode Register.
PAGE 1287
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... 46.7.34 USART LIN Baud Rate Register Name: Offset: Reset: Property: US_LINBRR 0x005C 0x0 Read-only This register is relevant only if USART_MODE = 0xA or 0xB in the USART Mode Register. Returns the baud rate value after the synchronization process completion.
PAGE 1288
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... 46.7.35 USART LON Mode Register Name: Offset: Reset: Property: US_LONMR 0x0060 0x0 Read/Write This register is relevant only if USART_MODE = 0x9 in the USART Mode Register. This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register.
PAGE 1289
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... Value 0 1 Description LON collision detection feature disabled. LON collision detection feature enabled. Bit 0 – COMMT LON comm_type Parameter Value Value Description 0 LON comm_type = 1 mode. 1 LON comm_type = 2 mode. © 2019 Microchip Technology Inc.
PAGE 1290
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... 46.7.36 USART LON Preamble Register Name: Offset: Reset: Property: US_LONPR 0x0064 0x0 Read/Write This register is relevant only if USART_MODE = 0x9 in the USART Mode Register. This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register.
PAGE 1291
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... 46.7.37 USART LON Data Length Register Name: Offset: Reset: Property: US_LONDL 0x0068 0x0 Read/Write This register is relevant only if USART_MODE = 0x9 in the USART Mode Register.
PAGE 1292
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... 46.7.38 USART LON L2HDR Register Name: Offset: Reset: Property: US_LONL2HDR 0x006C 0x0 Read/Write This register is relevant only if USART_MODE = 0x9 in the USART Mode Register.
PAGE 1293
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... 46.7.39 USART LON Backlog Register Name: Offset: Reset: Property: US_LONBL 0x0070 0x0 Read This register is relevant only if USART_MODE = 0x9 in the USART Mode Register.
PAGE 1294
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... 46.7.40 USART LON Beta1 Tx Register Name: Offset: Reset: Property: US_LONB1TX 0x0074 0x0 Read/Write This register is relevant only if USART_MODE = 0x9 in the USART Mode Register. This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register.
PAGE 1295
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... 46.7.41 USART LON Beta1 Rx Register Name: Offset: Reset: Property: US_LONB1RX 0x0078 0x0 Read/Write This register is relevant only if USART_MODE = 0x9 in the USART Mode Register. This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register.
PAGE 1296
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... 46.7.42 USART LON Priority Register Name: Offset: Reset: Property: US_LONPRIO 0x007C 0x0 Read/Write This register is relevant only if USART_MODE = 0x9 in the USART Mode Register. This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register.
PAGE 1297
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... 46.7.43 USART LON IDT Tx Register Name: Offset: Reset: Property: US_IDTTX 0x0080 0x0 Read/Write This register is relevant only if USART_MODE = 0x9 in the USART Mode Register. This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register.
PAGE 1298
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... 46.7.44 USART LON IDT Rx Register Name: Offset: Reset: Property: US_IDTRX 0x0084 0x0 Read/Write This register is relevant only if USART_MODE = 0x9 in the USART Mode Register. This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register.
PAGE 1299
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... 46.7.45 USART IC DIFF Register Name: Offset: Reset: Property: US_ICDIFF 0x0088 0x0 Read/Write This register is relevant only if USART_MODE = 0x9 in the USART Mode Register. This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register.
PAGE 1300
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... 46.7.
PAGE 1301
SAM E70/S70/V70/V71 Family Universal Synchronous Asynchronous Receiver Transc... 46.7.
PAGE 1302
SAM E70/S70/V70/V71 Family Universal Asynchronous Receiver Transmitter (UART) 47. Universal Asynchronous Receiver Transmitter (UART) 47.1 Description The Universal Asynchronous Receiver Transmitter (UART) features a two-pin UART that can be used for communication and trace purposes and offers an ideal medium for in-situ programming solutions. Moreover, the association with a DMA controller permits packet handling for these tasks with processor time reduced to a minimum. 47.
PAGE 1303
SAM E70/S70/V70/V71 Family Universal Asynchronous Receiver Transmitter (UART) 47.4 Product Dependencies 47.4.1 I/O Lines The UART pins are multiplexed with PIO lines. The user must first configure the corresponding PIO Controller to enable I/O line operations of the UART. 47.4.2 Power Management The UART clock can be controlled through the Power Management Controller (PMC). In this case, the user must first configure the PMC to enable the UART clock.
PAGE 1304
SAM E70/S70/V70/V71 Family Universal Asynchronous Receiver Transmitter (UART) 47.5.2 Receiver 47.5.2.1 Receiver Reset, Enable and Disable After device reset, the UART receiver is disabled and must be enabled before being used. The receiver can be enabled by writing the Control Register (UART_CR) with the bit RXEN at 1. At this command, the receiver starts looking for a start bit. The programmer can disable the receiver by writing UART_CR with the bit RXDIS at 1.
PAGE 1305
SAM E70/S70/V70/V71 Family Universal Asynchronous Receiver Transmitter (UART) Figure 47-5. Receiver Ready URXD S D0 D1 D2 D3 D4 D5 D6 D7 D0 S P D1 D2 D3 D4 D5 D6 D7 P RXRDY Read UART_RHR 47.5.2.4 Receiver Overrun The OVRE status bit in UART_SR is set if UART_RHR has not been read by the software (or the DMA Controller) since the last transfer, the RXRDY bit is still set and a new character is received.
PAGE 1306
SAM E70/S70/V70/V71 Family Universal Asynchronous Receiver Transmitter (UART) 47.5.2.7 Receiver Digital Filter The UART embeds a digital filter on the receive line. It is disabled by default and can be enabled by writing a logical 1 in the FILTER bit of UART_MR. When enabled, the receive line is sampled using the 16x bit clock and a threesample filter (majority 2 over 3) determines the value of the line. 47.5.3 Transmitter 47.5.3.
PAGE 1307
SAM E70/S70/V70/V71 Family Universal Asynchronous Receiver Transmitter (UART) Figure 47-10. Transmitter Control UART_THR Data 0 Data 1 Shift Register UTXD Data 0 Data 0 S Data 1 P S stop Data 1 P stop TXRDY TXEMPTY Write Data 0 in UART_THR 47.5.4 Write Data 1 in UART_THR DMA Support Both the receiver and the transmitter of the UART are connected to a DMA Controller (DMAC) channel. The DMA Controller channels are programmed via registers that are mapped within the DMAC user interface. 47.
PAGE 1308
SAM E70/S70/V70/V71 Family Universal Asynchronous Receiver Transmitter (UART) 47.5.6 Asynchronous and Partial Wake-up (SleepWalking) Asynchronous and partial wake-up (SleepWalking) is a means of data pre-processing that qualifies an incoming event, thus allowing the UART to decide whether or not to wake up the system. SleepWalking is used primarily when the system is in Wait mode (refer to section “Power Management Controller (PMC)”) but can also be enabled when the system is fully running.
PAGE 1309
SAM E70/S70/V70/V71 Family Universal Asynchronous Receiver Transmitter (UART) Figure 47-12.
PAGE 1310
SAM E70/S70/V70/V71 Family Universal Asynchronous Receiver Transmitter (UART) Figure 47-13.
PAGE 1311
SAM E70/S70/V70/V71 Family Universal Asynchronous Receiver Transmitter (UART) Figure 47-14. Test Modes Automatic Echo RXD Receiver Transmitter Disabled TXD Local Loopback Disabled Receiver RXD VDD Disabled Transmitter Remote Loopback Receiver Transmitter © 2019 Microchip Technology Inc.
PAGE 1312
SAM E70/S70/V70/V71 Family Universal Asynchronous Receiver Transmitter (UART) 47.6 Register Summary Offset Name 0x00 UART_CR 0x04 UART_MR 0x08 UART_IER 0x0C UART_IDR 0x10 UART_IMR 0x14 UART_SR 0x18 UART_RHR 0x1C UART_THR 0x20 UART_BRGR 0x24 UART_CMPR 0x28 ... 0xE3 Reserved 0xE4 UART_WPMR Bit Pos.
PAGE 1313
SAM E70/S70/V70/V71 Family Universal Asynchronous Receiver Transmitter (UART) 47.6.1 UART Control Register Name: Offset: Reset: Property: Bit UART_CR 0x00 – Write-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 REQCLR W – 11 10 9 8 RSTSTA W – 7 TXDIS W – 6 TXEN W – 5 RXDIS W – 4 RXEN W – 3 RSTTX W – 2 RSTRX W – 1 0 Access Reset Bit Access Reset Bit Access Reset Bit Access Reset Bit 12 – REQCLR Request Clear • SleepWalking enabled: 0: No effect.
PAGE 1314
SAM E70/S70/V70/V71 Family Universal Asynchronous Receiver Transmitter (UART) Value 0 1 Description No effect. The receiver is disabled. If a character is being processed and RSTRX is not set, the character is completed before the receiver is stopped. Bit 4 – RXEN Receiver Enable Value Description 0 No effect. 1 The receiver is enabled if RXDIS is 0. Bit 3 – RSTTX Reset Transmitter Value Description 0 No effect. 1 The transmitter logic is reset and disabled.
PAGE 1315
SAM E70/S70/V70/V71 Family Universal Asynchronous Receiver Transmitter (UART) 47.6.
PAGE 1316
SAM E70/S70/V70/V71 Family Universal Asynchronous Receiver Transmitter (UART) 47.6.3 UART Interrupt Enable Register Name: Offset: Reset: Property: UART_IER 0x08 – Write-only The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Enables the corresponding interrupt.
PAGE 1317
SAM E70/S70/V70/V71 Family Universal Asynchronous Receiver Transmitter (UART) 47.6.4 UART Interrupt Disable Register Name: Offset: Reset: Property: UART_IDR 0x0C – Write-only The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Disables the corresponding interrupt.
PAGE 1318
SAM E70/S70/V70/V71 Family Universal Asynchronous Receiver Transmitter (UART) 47.6.5 UART Interrupt Mask Register Name: Offset: Reset: Property: UART_IMR 0x10 0x00000000 Read-only The following configuration values are valid for all listed bit names of this register: 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
PAGE 1319
SAM E70/S70/V70/V71 Family Universal Asynchronous Receiver Transmitter (UART) 47.6.
PAGE 1320
SAM E70/S70/V70/V71 Family Universal Asynchronous Receiver Transmitter (UART) Value 0 1 Description A character has been written to UART_THR and not yet transferred to the internal shift register, or the transmitter is disabled. There is no character written to UART_THR not yet transferred to the internal shift register. Bit 0 – RXRDY Receiver Ready Value Description 0 No character has been received since the last read of the UART_RHR, or the receiver is disabled.
PAGE 1321
SAM E70/S70/V70/V71 Family Universal Asynchronous Receiver Transmitter (UART) 47.6.7 UART Receiver Holding Register Name: Offset: Reset: Property: Bit UART_RHR 0x18 0x00000000 Read-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 R 0 R 0 R 0 Access Reset Bit Access Reset Bit Access Reset Bit RXCHR[7:0] Access Reset R 0 R 0 R 0 R 0 Bits 7:0 – RXCHR[7:0] Received Character Last received character if RXRDY is set.
PAGE 1322
SAM E70/S70/V70/V71 Family Universal Asynchronous Receiver Transmitter (UART) 47.6.
PAGE 1323
SAM E70/S70/V70/V71 Family Universal Asynchronous Receiver Transmitter (UART) 47.6.
PAGE 1324
SAM E70/S70/V70/V71 Family Universal Asynchronous Receiver Transmitter (UART) 47.6.
PAGE 1325
SAM E70/S70/V70/V71 Family Universal Asynchronous Receiver Transmitter (UART) 47.6.
PAGE 1326
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) 48. Media Local Bus (MLB) 48.1 Description The MediaLB (MLB) maps all the MOST Network data types (transport methods) into a single low-cost, scalable, and standardized hardware interface between a MediaLB Controller and at least one other MediaLB Device. The use of MediaLB simplifies the hardware interface, reduces the pin count, and facilitates the design of modular reusable hardware.
PAGE 1327
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) The ChannelAddresses output by the Controller for each logical channel are used in normal data transport and can be statically or dynamically assigned. To support dynamic configuration of MediaLB Devices, a unique DeviceAddress must be assigned to all MediaLB Devices before startup. DeviceAddresses allow the External Host Controller (EHC) and MediaLB Controller to dynamically determine which Devices exist on the bus. At the request of a MediaLB Device (e.g.
PAGE 1328
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) 48.4 Signal Description 48.4.1 Definition of Terms The following terms will be used when referring to specific implementations of MediaLB. Table 48-1.
PAGE 1329
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) 48.5.4 3-pin MediaLB Interface 48.5.4.1 Pin Description The MediaLB system clock is generated by a single MediaLB Controller. The MediaLB Controller outputs the clock on the MLBCLK pin, which is connected to the clock input of all other MediaLB Devices in the system. All MediaLB Devices (including the MediaLB Controller), share the signals connected to the MLBSIG and MLBDAT pins.
PAGE 1330
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) A 16-bit token, which is sent on the MLBS line by the MediaLB Controller at the end of a physical channel. A unique ChannelAddress defines a logical channel and grants a particular physical channel to a transmitting (Tx) and a receiving (Rx) MediaLB Device. • Command: A byte-wide value sent by the transmitting (Tx) MediaLB Device on the MLBS line at the start of a physical channel.
PAGE 1331
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) are never assigned to physical channels. Once a Device is found, the ChannelAddresses used in normal operation can be assigned. MediaLB Devices are encouraged to support dynamic configuration, where a preset DeviceAddress is used to assign the ChannelAddresses for each logical channel. Dynamic configuration avoids collisions of ChannelAddresses on different Devices.
PAGE 1332
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) ...........continued Value (see Note) Command Description 02h...0Eh rsvd Reserved 10h Tx Device sends out SyncData command to indicate synchronous stream data. SyncData 12h...1Eh rsvd Reserved 20h AsyncStart Asynchronous logical channel. Start of a packet. 22h AsyncContinue Asynchronous logical channel. Middle of a packet. 24h AsyncEnd Asynchronous logical channel. End of a packet. 26h AsyncBreak Asynchronous logical channel.
PAGE 1333
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) ...........continued Value (see Note) Command Description System Commands (Controller sends in System Channel): 00h NoData The Controller has no System command to send out. E0h MOSTLock The Controller issues a MOST Network lock command in the System Channel to notify Devices that the MOST Network is in lock. E2h MOSTUnlock The Controller issues a MOST Network unlock command in the System Channel to notify Devices that the MOST Network is unlocked.
PAGE 1334
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) Table 48-6. MediaLB RxStatus Responses Value (see Note) RxStatus Description Normal Responses (Rx Device response in non-System Channels): 00h ReceiverReady Current state indicating the receiving Device is ready to receive the data. This is the default for the bus. The Rx Devices should not drive this response for broadcast channels. 02h...0Eh rsvd Reserved 10h Current state indicating the Rx Device is not ready to receive the data.
PAGE 1335
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) The MLBSubCmd command is used for configuration and status information from the Controller to Devices. A subcommand is contained in the first byte of the MLBD quadlet. When MediaLB Device interfaces receive the MLBSubCmd command, they will store the command and corresponding data quadlet (sub-command). Currently, only one sub-command is defined (scSetCA) and is used in dynamic configuration.
PAGE 1336
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) • The Rx MediaLB Device responds in the same physical channel by shifting out its status response (RxStatus) onto the MLBS line after the Tx Device’s Command. The RxStatus reports the status of the receiving Device to the sender. For asynchronous, control and isochronous (non-broadcast) transmissions, the data sent is accepted if the receiver presents a status response of ReceiverReady or rejected if the receiver presents a status response of ReceiverBusy.
PAGE 1337
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) ...........continued MediaLB Speed Physical Channels per Frame Available Physical Channels per Frame (see Note) 512×Fs 16 15 (PC1–PC15) Note: PC0 (first physical channel of the MediaLB frame) is always used as the System Channel. The MLBS and MLBD physical channel associated with the FRAMESYNC ChannelAddress (PC0), is defined as the System Channel and can be used by the Controller to broadcast system control and status information to all Devices.
PAGE 1338
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) activity exists on MediaLB, the Controller can shut off the MLBC placing MediaLB in a low-power state. The ChannelAddress assignments are not affected in low-power state; therefore, the same communication paths exists once MLBC is restarted. MediaLB Devices are synchronously slaved to the MediaLB Controller through the MLBC signal.
PAGE 1339
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) The flow diagram contains four states: Idle, Start, Continue, and End. Each state uses a different command when sending the data. The Idle state is the starting point, waiting for the application to initiate a packet transfer. When a quadlet is ready to be transferred, the flow diagram moves to the Start state.
PAGE 1340
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) Figure 48-6. Control Packet Tx Device Protocol: Start Init GoTo Idle State = Idle Packet ready to send ? no Send Command = NoData Send Data = 0x00000000 Receive RxStatus yes RxStatus == ReceiverProtocolError ? State = Start † yes Report Protocol Error to Application no * Application request break ? no yes * Supporting application Break requests other than after an RxStatus of ReceiverBusy is optional.
PAGE 1341
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) Figure 48-7. Control Packet Tx Device Protocol: Middle GoTo Next Increment to next quadlet Last quadlet ? yes GoTo EndState no State = Continue * Supporting application Break requests other than after an RxStatus of ReceiverBusy is optional.
PAGE 1342
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) Figure 48-8. Control Packet Tx Device Protocol: End GoTo EndState State = End * Application request break ? yes * Supporting application Break requests other than after an RxStatus of ReceiverBusy is optional.
PAGE 1343
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) Figure 48-9.
PAGE 1344
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) Figure 48-10 illustrates the synchronous data formats for MediaLB. For stereo 24-bit data, two physical channels (PCn) are needed per frame where the data is packed and left-justified in the two quadlets. In the 32-bit sequential format, data fills the entire quadlet with the internal data format determined by the system implementor. Figure 48-10.
PAGE 1345
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) Figure 48-12. Synchronous Data Rx Device Protocol Init State = Continue Receive Command Receive Data RxStatus ReceiverReady yes Command SyncData no Store received data in Rx Buffer Report Protocol Error to Application discard received data, substitute safe data Isochronous Isochronous data is sent in a streaming fashion, similar to synchronous data.
PAGE 1346
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) RxStatus (default ReceiverReady response), then the isochronous stream can support multiple Rx Devices (broadcast). Figure 48-14.
PAGE 1347
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) Figure 48-15.
PAGE 1348
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) Physical Layer portion of this specification must be met by all Devices for whichever speeds a particular Device supports. All MediaLB Devices must support the rules for synchronization to MediaLB. For MediaLB Controllers, all System commands are optional, including support for dynamic system configuration and DeviceAddresses. For MediaLB Devices, support for all transport methods is optional.
PAGE 1349
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) ...........continued Channel Address Logical Channel 0x007E 63 0x01FE 0(1) Note: 1. Logical Channel 0 is the System Channel and is reserved. 48.6.3.2 Host Bus Interface Block The Host Bus Interface (HBI) block provides a 16-bit parallel slave port that provides an external Host Controller (HC) with access to all MOST channels and data types.
PAGE 1350
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) Receive devices retain the write address pointer to the associated circular data buffer in the DBR, while transmit devices retain the read address pointer. The DMA controllers in the routing fabric are responsible for ensuring that the circular buffers do not overflow or underflow. Each channel type (e.g., synchronous, isochronous, asynchronous and control) has Full and Empty detection.
PAGE 1351
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) ...........continued Label Address Bits 127…96 ADT(1) 0x40 ADT0[127:0] 0x41 ADT1[127:0] 0x42 ADT2[127:0] ... ... 0x7D ADT61[127:0] 0x7E ADT62[127:0] 0x7F ADT63[127:0] Bits 95…64 Bits 63…32 Bits 31…0 Channel Allocation Table (CAT): CAT for MediaLB CAT for HBI(1) 0x80 CAT7 CAT6 CAT5 CAT4 CAT3 CAT2 CAT1 CAT0 ... ... ... ... ... ... ... ... ...
PAGE 1352
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) Table 48-13.
PAGE 1353
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) Figure 48-16. MLB DBR Directional Relationship MediaLB CAT RNW = 0 HBI CAT RNW = 1 Host Controller (HC) Rx Rx Host Bus Interface AMBA Tx Data Buffer Ram (DBR) HBI CAT RNW = 0 MediaLB Interface MediaLB Bus Tx MediaLB CAT RNW = 1 Channel Descriptor Table The Channel Descriptor Table (CDT) is comprised of 64 CTR entries (addresses 0x00–0x3F), as shown in Table 48-10.
PAGE 1354
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) ...........continued Bit Offset 15 14 13 12 11 10 32 Reserved 48 Reserved 64 WSTS[3:0] WPTR[11:0] 80 RSTS[3:0] RPTR[11:0] 96 Reserved BD[11:0] 112 Reserved 9 8 7 6 5 4 3 2 1 0 BA[13:0] Table 48-15.
PAGE 1355
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) ...........continued Field Description Reserved Reserved Details Accessibility - Software writes a zero to all reserved bits when the entry is initialized. The reserved bits are Read-only after initialization. r,w,u (1) Notes: 1. “u” means “Updated periodically by hardware”. 2. Only valid for DMA pointers associated with the MediaLB block (Not valid for HBI block related pointers).
PAGE 1356
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) ...........
PAGE 1357
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) ...........
PAGE 1358
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) Figure 48-18. MIF CTR Read and Write Flow Diagrams MIF CTR Write: MIF CTR Read: Start Start Write data to MDAT Write address & control to MADR Write MDWE MCTL.XCMP = 0 Transfer Complete? Write address & control to MADR MCTL.XCMP = 1 MCTL.XCMP = 0 Transfer Complete? Read data from MDAT Stop MCTL.XCMP = 1 Stop Direct CTR Writes For a direct write of the CTR, the HC first loads the 128-bit data entry into the MLB_MDAT0–3 registers.
PAGE 1359
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) The MIF block allows the HC to access the external Data Buffer RAM (DBR) directly when MLB_MADR.TB is set. Any write to the MLB_MADR triggers a single read or write cycle. Reading from the MLB_MADR register does not initiate read/write access. Figure 48-19. MIF DBR Read and Write Flow Diagrams MIF DBR Write: MIF DBR Read: Start Start Write data to MDAT Write address & control to MADR Write address & control to MADR MCTL.
PAGE 1360
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) 48.6.3.6 AHB Block The AHB block manages data exchange between local channel data buffers within the MLB and the system memory buffer. To support system memory buffering, a ping-pong memory structure is implemented on a per-channel basis using 128-bit descriptors for AHB Descriptor Table (ADT) entries. Note: The 64 ADT entries are directly mapped to the 64 HBI physical channels.
PAGE 1361
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) ...........continued Field No. of Bits Description Accessibility PS1 1 r,w,u (1) (both Tx and Rx) Packet start bit for ping buffer page: 0 = No packet start 1 = Packet start Reserved for synchronous and isochronous channels. PS2 1 Packet start bit for pong buffer page: 0 = No packet start r,w,u (1) (both Tx and Rx) 1 = Packet start Reserved for synchronous and isochronous channels.
PAGE 1362
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) Figure 48-20. Endianness Overview 32-bit Word Byte 3 Byte 2 Byte 1 Byte 0 Big Endian MSB LSB Little Endian LSB MSB The following figure shows an example of the ping-pong system memory structure. This system memory structure is similar for all channel types and shows the relationship between the BAn, BDn, and PG descriptor fields. Figure 48-21.
PAGE 1363
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) Table 48-22.
PAGE 1364
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) Figure 48-22.
PAGE 1365
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) For Rx packet channels in multiple-packet mode, PSn has no meaning and should be ignored. Software is responsible for keeping track of where each packet starts and ends within the multiple-packet buffer via the packet PML. The buffer done bit (DNEn) is set in hardware for Rx channels when a buffer is full (see Buffer 1 in Figure 48-23) or if a packet ends exactly 1-byte before the end of the buffer (see Buffer 2 in Figure 48-23).
PAGE 1366
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) 48.6.4.1 Channel Initialization The software flow required to initialize a channel must be performed in order to ensure proper operation. For clarity, the software flow is grouped as follows: • • • • Configure the Hardware Program the Routing Fabric Block Program the AHB Block DMAs Synchronize and Unmute Synchronous Channel Configure the Hardware The MLB_MLBC0, HMCR0, HMCR1 and MLB_HCTL registers are accessible directly via APB reads and writes. 1. 2. 3.
PAGE 1367
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) 5.4. 6. Set the channel type: CT[2:0] = 010 (asynchronous), 001 (control), 011 (isochronous), or 000 (synchronous) 5.5. Set the channel label: CL[5:0] = N 5.6. If CT[2:0] = 000 (synchronous), set the mute bit (MT = 1) 5.7. Set the channel enable: CE = 1 5.8.
PAGE 1368
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) 3. 4. 5. Poll for MediaLB lock (MLB_MLBC0.MLBLK = 1) Wait four frames Unmute synchronous channel(s) 48.6.4.2 Channel Servicing After initialization, each channel will require periodic servicing.
PAGE 1369
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) The MLB supports the MediaLB System Commands (e.g. MlbScan, MlbReset, MOST_Unlock). The MediaLB System Status (MLB_MSS) Register is used to detect a System Command received from the MediaLB Controller. The MLB automatically sends the appropriate system response to the MediaLB Controller. The procedure for the application is: 1. 2. 3. The application periodically polls the MLB_MSS register.
PAGE 1370
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) 48.7 Register Summary Offset Name Bit Pos. 0x00 MLB_MLBC0 7:0 15:8 23:16 31:24 0x04 ... 0x0B Reserved 0x0C MLB_MS0 0x10 ... 0x13 Reserved 0x14 MLB_MS1 0x18 ... 0x1F Reserved 0x20 MLB_MSS 0x24 MLB_MSD 0x28 ... 0x2B Reserved 0x2C MLB_MIEN 0x30 ... 0x3B Reserved 0x3C MLB_MLBC1 0x40 ... 0x7F Reserved 0x80 MLB_HCTL 0x84 ...
PAGE 1371
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) ...........continued Offset Name 0x8C MLB_HCMR1 0x90 MLB_HCER0 0x94 MLB_HCER1 0x98 MLB_HCBR0 0x9C MLB_HCBR1 0xA0 ... 0xBF Reserved 0xC0 MLB_MDAT0 0xC4 MLB_MDAT1 0xC8 MLB_MDAT2 0xCC MLB_MDAT3 0xD0 MLB_MDWE0 0xD4 MLB_MDWE1 0xD8 MLB_MDWE2 0xDC MLB_MDWE3 0xE0 MLB_MCTL Bit Pos.
PAGE 1372
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) ...........continued Offset Name Bit Pos. 0xE4 MLB_MADR 7:0 15:8 23:16 31:24 0xE8 ... 0x03BF ADDR[7:0] ADDR[13:8] WNR TB Reserved 0x03C0 MLB_ACTL 0x03C4 ... 0x03CF Reserved 0x03D0 MLB_ACSR0 0x03D4 MLB_ACSR1 0x03D8 MLB_ACMR0 0x03DC MLB_ACMR1 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 © 2019 Microchip Technology Inc.
PAGE 1373
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) 48.7.
PAGE 1374
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) Bit 5 – ZERO Must be Written to 0 Bits 4:2 – MLBCLK[2:0] MLBCLK (MediaLB clock) Speed Select Value Name Description 0 256_FS 256xFs (for MLBPEN = 0) 1 512_FS 512xFs (for MLBPEN = 0) 2 1024_FS 1024xFs (for MLBPEN = 0) 3 2048_FS 2048xFs (for MLBPEN = 0) 4 3072_FS 3072xFs (for MLBPEN = 0) 5 4096_FS 4096xFs (for MLBPEN = 0) 6 6144_FS 6144xFs (for MLBPEN = 0) Bit 0 – MLBEN MediaLB Enable Value Description 1 MLBCLK (MediaLB clock), MLBSIG (signal), and MLBDATA (dat
PAGE 1375
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) 48.7.2 MediaLB Channel Status 0 Register Name: Offset: Reset: Property: MLB_MS0 0x00C 0x00000000 Read/Write Each bit can be cleared by writing a 0.
PAGE 1376
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) 48.7.3 MediaLB Channel Status1 Register Name: Offset: Reset: Property: MLB_MS1 0x014 0x00000000 Read/Write Each bit can be cleared by writing a 0.
PAGE 1377
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) 48.7.
PAGE 1378
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) 48.7.
PAGE 1379
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) 48.7.
PAGE 1380
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) Bit 22 – ATX_BREAK Asynchronous Tx Break Enable Value Description 1 A ReceiverBreak response received from the receiver on an asynchronous Tx channel causes the appropriate channel bit in the MLB_MS0 or MLB_MS1 registers to be set. Bit 21 – ATX_PE Asynchronous Tx Protocol Error Enable Value Description 1 A ProtocolError generated by the receiver on an asynchronous Tx channel causes the appropriate channel bit in the MLB_MS0 or MLB_MS1 registers to be set.
PAGE 1381
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) 48.7.7 MediaLB Control 1 Register Name: Offset: Reset: Property: Bit MLB_MLBC1 0x03C 0x00000000 Read/Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 Access Reset Bit Access Reset Bit NDA[7:0] Access Reset Bit Access Reset 0 0 0 0 0 0 0 0 7 CLKM 6 LOCK 5 4 3 2 1 0 0 0 Bits 15:8 – NDA[7:0] Node Device Address Used for system commands directed to individual MediaLB nodes.
PAGE 1382
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) 48.7.8 HBI Control Register Name: Offset: Reset: Property: MLB_HCTL 0x080 0x00000000 Read/Write The HC can control and monitor general operation of the HBI block by reading and writing the HBI Control Register (MLB_HCTL) through the I/O interface. Each bit of MLB_HCTL is read/write.
PAGE 1383
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) 48.7.9 HBI Channel Mask 0 Register Name: Offset: Reset: Property: MLB_HCMR0 0x088 0x00000000 Read/Write The HC can control which channel(s) are able to generate an HBI interrupt by writing the HBI Channel Mask Registers (HCMRn). Each bit of HCMRn is read/write.
PAGE 1384
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) 48.7.
PAGE 1385
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) 48.7.11 HBI Channel Error 0 Register Name: Offset: Reset: Property: MLB_HCER0 0x090 0x00000000 Read-only The HBI Channel Error Registers (HCERn) indicate which channel(s) have encountered fatal errors.
PAGE 1386
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) 48.7.
PAGE 1387
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) 48.7.13 HBI Channel Busy 0 Register Name: Offset: Reset: Property: MLB_HCBR0 0x098 0x00000000 Read-only The HC can determine which channel(s) are busy by reading the HBI Channel Busy Registers (HCBRn).
PAGE 1388
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) 48.7.
PAGE 1389
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) 48.7.
PAGE 1390
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) 48.7.
PAGE 1391
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) 48.7.
PAGE 1392
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) 48.7.
PAGE 1393
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) 48.7.
PAGE 1394
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) 48.7.
PAGE 1395
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) 48.7.
PAGE 1396
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) 48.7.
PAGE 1397
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) 48.7.23 MIF Control Register Name: Offset: Reset: Property: Bit MLB_MCTL 0x0E0 0x00000000 Read/Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 XCMP Access Reset Bit Access Reset Bit Access Reset Bit Access Reset 0 Bit 0 – XCMP Transfer Complete (Write 0 to Clear) © 2019 Microchip Technology Inc.
PAGE 1398
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) 48.7.
PAGE 1399
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) 48.7.25 AHB Control Register Name: Offset: Reset: Property: MLB_ACTL 0x3C0 0x00000000 Read/Write The AHB Control (MLB_ACTL) register is written by the HC to configure the AHB block for channel interrupts. MLB_ACTL contains three configuration fields, one is used to select the DMA mode, one is used to multiplex channel interrupts onto a single interrupt signal, and the last selects the method of clearing channel interrupts (either software or hardware).
PAGE 1400
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) 48.7.26 AHB Channel Status 0 Register Name: Offset: Reset: Property: MLB_ACSR0 0x3D0 0x00000000 Read/Write The AHB Channel Status (ACSRn) registers contain interrupt bits for each of the 64 physical channels. When an MLB_ACSRn register bit is set, it indicates that the corresponding physical channel has an interrupt pending. An AHB interrupt is triggered when either DNEn or ERRn is set within the AHB Channel Descriptor.
PAGE 1401
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) 48.7.
PAGE 1402
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) 48.7.28 AHB Channel Mask 0 Register Name: Offset: Reset: Property: MLB_ACMR0 0x3D8 0x00000000 Read/Write Using the AHB Channel Mask (ACMRn) register, the HC can control which channel(s) generate interrupts on ahb_int[1:0]. All ACMRn register bits default as ‘0’ (“masked”); therefore, the HC must initially write ACMRn to enable interrupts. Each bit of ACMRn is read/write accessible.
PAGE 1403
SAM E70/S70/V70/V71 Family Media Local Bus (MLB) 48.7.
PAGE 1404
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) 49. 49.1 Controller Area Network (MCAN) Description The Controller Area Network (MCAN) performs communication according to ISO 11898-1:2015 and to Bosch CANFD specification. Additional transceiver hardware is required for connection to the physical layer. All functions concerning the handling of messages are implemented by the Rx Handler and the Tx Handler.
PAGE 1405
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) 49.3 Block Diagram Figure 49-1.
PAGE 1406
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) 49.4.4 Address Configuration The LSBs [bits 15:2] for each section of the CAN Message RAM are configured in the respective buffer configuration registers as detailed in Message RAM. The MSBs [bits 31:16] of the CAN Message RAM for CAN0 and CAN1 are configured in CCFG_CAN0 and CCFG_SYSIO registers. 49.4.5 Timestamping Timestamping uses the value of CV in the TC Counter Value 0 register (TC_CV0) at address 0x4000C010.
PAGE 1407
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) • • Transmit Buffer Add Request (MCAN_TXBAR) Transmit Buffer Cancellation Request (MCAN_TXBCR) MCAN_CCCR.TEST and MCAN_CCCR.MON can only be set when MCAN_CCCR.INIT = ‘1’ and MCAN_CCCR.CCE = ‘1’. Both bits may be cleared at any time. MCAN_CCCR.DAR can only be configured when MCAN_CCCR.INIT = ‘1’ and MCAN_CCCR.CCE = ‘1’. 49.5.1.2 Normal Operation Once the MCAN is initialized and MCAN_CCCR.
PAGE 1408
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) Table 49-1. Coding of DLC in CAN FD DLC 9 10 11 12 13 14 15 Number of Data Bytes 12 16 20 24 32 48 64 In CAN FD frames, the bit timing will be switched inside the frame, after the BRS (Bit Rate Switch) bit, if this bit is recessive. Before the BRS bit, in the CAN FD arbitration phase, the nominal CAN bit timing is used as defined by the Nominal Bit Timing and Prescaler register (MCAN_NBTP).
PAGE 1409
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) The resolution of this measurement is one mtq. Figure 49-2. Transmitter Delay Measurement Transmitter Delay FDF CANTX res BRS arbitration phase CANRX CAN core clock DLC data phase arbitration phase Start E S I data phase Stop Delay Delay Counter SSP Position MCAN_TDCR.
PAGE 1410
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) Figure 49-3. Pin Control in Bus Monitoring Mode CANTX CANRX =1 • Tx • Rx MCAN Bus Monitoring Mode 49.5.1.7 Disabled Automatic Retransmission According to the CAN Specification (see ISO11898-1, 6.3.3 Recovery Management), the MCAN provides means for automatic retransmission of frames that have lost arbitration or that have been disturbed by errors during transmission. By default automatic retransmission is enabled.
PAGE 1411
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) timing and it can drive constant dominant or recessive values. The actual value at pin CANRX can be read from MCAN_TEST.RX. Both functions can be used to check the CAN bus’ physical layer. Due to the synchronization mechanism between CAN clock and system bus clock domain, there may be a delay of several system bus clock periods between writing to MCAN_TEST.TX until the new configuration is visible at output pin CANTX.
PAGE 1412
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) actual counter value can be read from MCAN_TOCV.TOC. The Timeout Counter can only be started while MCAN_CCCR.INIT = ‘0’. It is stopped when MCAN_CCCR.INIT = ‘1’, e.g. when the MCAN enters Bus_Off state. The operating mode is selected by MCAN_TOCC.TOS. When operating in Continuous mode, the counter starts when MCAN_CCCR.INIT is reset. A write to MCAN_TOCV presets the counter to the value configured by MCAN_TOCC.TOP and continues down-counting.
PAGE 1413
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) • • Rx Buffer New Data flag of matching Rx Buffer is not set, but Rx Buffer (partly) overwritten with received data. For error type, see MCAN_PSR.LEC and MCAN_PSR.DLEC. Rx FIFO Put index of matching Rx FIFO is not updated, but related Rx FIFO element (partly) overwritten with received data. For error type, see MCAN_PSR.LEC and MCAN_PSR.DLEC.
PAGE 1414
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) Figure 49-5. Standard Message ID Filter Path valid frame received 11 bit 29 bit 11 / 29 bit identifier remote frame no yes reject remote frames MCAN_GFC.RRFS = ‘1’ MCAN_GFC.RRFS = ‘0’ MCAN_SIDFC.LSS[7:0] = 0 receive filter list enabled MCAN_SIDFC.LSS[7:0] > 0 yes match filter element #0 no reject match filter element #MCAN_SIDFC.LSS yes acceptance / rejection no accept non-matching frames accept MCAN.GFC.
PAGE 1415
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) Figure 49-6. Extended Message ID Filter Path valid frame received 11 bit MCAN_GFC.RRFE = ‘1’ 11 / 29 bit identifier yes reject remote frames MCAN_GFC.RRFE = ‘0’ 29 bit remote frame no receive filter list enabled yes match filter element #0 no reject acceptance / rejection yes accept match filter element #MCAN_XIDFC.LSE no MCAN_GFC.ANFE[1] = ‘1’ discard frame MCAN_XIDFC.LSE[6:0] = 0 MCAN_XIDFC.
PAGE 1416
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) Figure 49-7. Rx FIFO Status Get Index MCAN_RXFnS.FnGI 7 Put Index MCAN_RXFnS.FnPI 0 6 1 5 2 4 3 Fill Level MCAN_RXFnS.FnFL When reading from an Rx FIFO, Rx FIFO Get Index MCAN_RXFnS.FnGI × FIFO Element Size has to be added to the corresponding Rx FIFO start address MCAN_RXFnC.FnSA. Table 49-2. Rx Buffer / FIFO Element Size MCAN_RXESC.RBDS[2:0] MCAN_RXESC.
PAGE 1417
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) When an Rx FIFO is operated in Overwrite mode and an Rx FIFO full condition is signalled, reading of the Rx FIFO elements should start at least at get index + 1. The reason for that is, that it might happen, that a received message is written to the Message RAM (put index) while the processor is reading from the Message RAM (get index). In this case inconsistent data may be read from the respective Rx FIFO element.
PAGE 1418
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) While an Rx Buffer’s New Data flag is set, a Message ID Filter Element referencing this specific Rx Buffer will not match, causing the acceptance filtering to continue. Following Message ID Filter Elements may cause the received message to be stored into another Rx Buffer, or into an Rx FIFO, or the message may be rejected, depending on filter configuration. 49.5.4.3.1 Rx Buffer Handling • Reset interrupt flag IR.
PAGE 1419
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) Figure 49-9.
PAGE 1420
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) The Tx Handler starts a Tx scan to check for the highest priority pending Tx request (Tx Buffer with lowest Message ID) when MCAN_TXBRP is updated, or when a transmission has been started. 49.5.5.1 Transmit Pause The transmit pause feature is intended for use in CAN systems where the CAN message identifiers are (permanently) specified to specific values and cannot easily be changed.
PAGE 1421
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) New transmit messages have to be written to the Tx FIFO starting with the Tx Buffer referenced by the Put Index MCAN_TXFQS.TFQPI. An Add Request increments the Put Index to the next free Tx FIFO element. When the Put Index reaches the Get Index, Tx FIFO Full (MCAN_TXFQS.TFQF = ‘1’) is signalled. In this case no further messages should be written to the Tx FIFO until the next message has been transmitted and the Get Index has been incremented.
PAGE 1422
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) • Buffer with lowest Message ID gets highest priority and is transmitted next 49.5.5.6 Mixed Dedicated Tx Buffers / Tx Queue In this case the Tx Buffers section in the Message RAM is subdivided into a set of dedicated Tx Buffers and a Tx Queue. The number of dedicated Tx Buffers is configured by MCAN_TXBC.NDTB. The number of Tx Queue Buffers is configured by MCAN_TXBC.TFQS. In case MCAN_TXBC.
PAGE 1423
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) 49.5.6 FIFO Acknowledge Handling The Get Indices of Rx FIFO 0, Rx FIFO 1, and the Tx Event FIFO are controlled by writing to the corresponding FIFO Acknowledge Index in the registers MCAN_RXF0A, MCAN_RXF1A and MCAN_TXEFA. Writing to the FIFO Acknowledge Index will set the FIFO Get Index to the FIFO Acknowledge Index plus one and thereby updates the FIFO Fill Level.
PAGE 1424
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) 49.5.7.2 Rx Buffer and FIFO Element Up to 64 Rx Buffers and two Rx FIFOs can be configured in the Message RAM. Each Rx FIFO section can be configured to store up to 64 received messages. The structure of a Rx Buffer / FIFO element is shown in the table below. The element size can be configured for storage of CAN FD messages with up to 64 bytes data field via register MCAN_RXESC. Table 49-7.
PAGE 1425
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) 1: Frame received with bit rate switching. Note: Bits ESI, FDF, and BRS are only evaluated when CAN FD operation is enabled (MCAN_CCCR.FDOE = 1). Bit BRS is only evaluated when in addition MCAN_CCCR.BRSE = 1. • R1 Bits 19:16 DLC[3:0]: Data Length Code 0-8: CAN + CAN FD: received frame has 0-8 data bytes. 9-15: CAN: received frame has 8 data bytes. 9-15: CAN FD: received frame has 12/16/20/24/32/48/64 data bytes.
PAGE 1426
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) • T0 Bit 30 ESI: Error State Indicator T0 Bit 31 ESI: Error State Indicator 0: ESI bit in CAN FD format depends only on error passive flag 1: ESI bit in CAN FD format transmitted recessive Note: The ESI bit of the transmit buffer is or’ed with the error passive flag to decide the value of the ESI bit in the transmitted FD frame.
PAGE 1427
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) • T3 Bits 23:16 DB6[7:0]: Data Byte 6 • T3 Bits 15:8 DB5[7:0]: Data Byte 5 • T3 Bits 7:0 DB4[7:0]: Data Byte 4 ... ... ... • Tn Bits 31:24 DBm[7:0]: Data Byte m • Tn Bits 23:16 DBm-1[7:0]: Data Byte m-1 • Tn Bits 15:8 DBm-2[7:0]: Data Byte m-2 • Tn Bits 7:0 DBm-3[7:0]: Data Byte m-3 Note: Depending on the configuration of the element size (MCAN_TXESC), between two and sixteen 32-bit words (Tn = 3 ..
PAGE 1428
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) • E1 Bit 20 BRS: Bit Rate Switch 0: Frame transmitted without bit rate switching. 1: Frame transmitted with bit rate switching. • E1 Bits 19:16 DLC[3:0]: Data Length Code 0-8: CAN + CAN FD: frame with 0-8 data bytes transmitted. 9-15: CAN: frame with 8 data bytes transmitted. 9-15: CAN FD: frame with 12/16/20/24/32/48/64 data bytes transmitted • E1 Bits 15:0 TXTS[15:0]: Tx Timestamp Timestamp Counter value captured on start of frame transmission.
PAGE 1429
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) This field has a different meaning depending on the configuration of SFEC: • • SFEC = “001”...“110”–Second ID of standard ID filter element SFEC = “111”–Filter for Rx Buffers or for debug messages SFID2[10:9] decides whether the received message is stored into an Rx Buffer or treated as message A, B, or C of the debug message sequence.
PAGE 1430
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) • F1 Bits 28:0 EFID2[28:0]: Extended Filter ID 2 This field has a different meaning depending on the configuration of EFEC: • EFEC = “001”...“110”–Second ID of extended ID filter element • EFEC = “111”–Filter for Rx Buffers or for debug messages EFID2[10:9] decides whether the received message is stored into an Rx Buffer or treated as message A, B, or C of the debug message sequence.
PAGE 1431
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) 49.6 Register Summary Offset Name 0x00 MCAN_CREL 0x04 MCAN_ENDN 0x08 MCAN_CUST 0x0C MCAN_DBTP 0x10 MCAN_TEST 0x14 MCAN_RWD 0x18 MCAN_CCCR 0x1C 0x20 MCAN_NBTP MCAN_TSCC 0x24 MCAN_TSCV 0x28 MCAN_TOCC 0x2C MCAN_TOCV 0x30 ... 0x3F Reserved 0x40 MCAN_ECR Bit Pos.
PAGE 1432
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) ...........continued Offset Name 0x44 MCAN_PSR 0x48 MCAN_TDCR 0x4C ... 0x4F Reserved 0x50 0x54 0x58 MCAN_IR MCAN_IE MCAN_ILS 0x5C MCAN_ILE 0x60 ... 0x7F Reserved 0x80 0x84 MCAN_GFC MCAN_SIDFC 0x88 MCAN_XIDFC 0x8C ... 0x8F Reserved 0x90 0x94 0x98 MCAN_XIDAM MCAN_HPMS MCAN_NDAT1 Bit Pos.
PAGE 1433
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) ...........continued Offset Name 0x9C MCAN_NDAT2 0xA0 MCAN_RXF0C 0xA4 MCAN_RXF0S 0xA8 MCAN_RXF0A 0xAC MCAN_RXBC 0xB0 0xB4 MCAN_RXF1C MCAN_RXF1S 0xB8 MCAN_RXF1A 0xBC MCAN_RXESC 0xC0 0xC4 MCAN_TXBC MCAN_TXFQS 0xC8 MCAN_TXESC 0xCC MCAN_TXBRP 0xD0 MCAN_TXBAR Bit Pos.
PAGE 1434
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) ...........continued Offset Name 0xD4 MCAN_TXBCR 0xD8 MCAN_TXBTO 0xDC MCAN_TXBCF 0xE0 MCAN_TXBTIE 0xE4 MCAN_TXBCIE 0xE8 ... 0xEF Reserved 0xF0 MCAN_TXEFC 0xF4 MCAN_TXEFS 0xF8 MCAN_TXEFA Bit Pos.
PAGE 1435
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) 49.6.1 MCAN Core Release Register Name: Offset: Reset: Property: MCAN_CREL 0x00 0x32150320 Read-only Due to clock domain crossing, there is a delay between when a register bit or field is written and when the related status register bits are updated.
PAGE 1436
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) 49.6.
PAGE 1437
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) 49.6.
PAGE 1438
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) 49.6.4 MCAN Data Bit Timing and Prescaler Register Name: Offset: Reset: Property: MCAN_DBTP 0x0C 0x00000A33 Read/Write This register can only be written if the bits CCE and INIT are set in MCAN CC Control Register. The CAN bit time may be programmed in the range of 4 to 25 time quanta. The CAN time quantum may be programmed in the range of 1 to 32 CAN core clock periods. tq = (DBRP + 1) CAN core clock periods.
PAGE 1439
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) Bits 7:4 – DTSEG2[3:0] Data Time Segment After Sample Point The duration of time segment is tq x (DTSEG2 + 1). Bits 2:0 – DSJW[2:0] Data (Re) Synchronization Jump Width The duration of a synchronization jump is tq x (DSJW + 1). © 2019 Microchip Technology Inc.
PAGE 1440
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) 49.6.5 MCAN Test Register Name: Offset: Reset: Property: MCAN_TEST 0x10 0x00000000 Read/Write Write access to the Test Register has to be enabled by setting bit MCAN_CCCR.TEST to ‘1’. All MCAN Test Register functions are set to their reset values when bit MCAN_CCCR.TEST is cleared. Loop Back mode and software control of pin CANTX are hardware test modes. Programming of TX ≠ 0 disturbs the message transfer on the CAN bus.
PAGE 1441
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) 49.6.6 MCAN RAM Watchdog Register Name: Offset: Reset: Property: MCAN_RWD 0x14 0x00000000 Read/Write The RAM Watchdog monitors the Message RAM response time. A Message RAM access via the MCAN’s Generic Master Interface starts the Message RAM Watchdog Counter with the value configured by MCAN_RWD.WDC. The counter is reloaded with MCAN_RWD.WDC when the Message RAM signals successful completion by activating its READY output.
PAGE 1442
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) 49.6.
PAGE 1443
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) Bit 8 – FDOE CAN FD Operation Enable (read/write, write protection) 0 (DISABLED): FD operation disabled. 1 (ENABLED): FD operation enabled. Bit 7 – TEST Test Mode Enable (read/write, write protection against ‘1’) 0 (DISABLED): Normal operation, MCAN_TEST register holds reset values. 1 (ENABLED): Test mode, write access to MCAN_TEST register enabled.
PAGE 1444
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) 49.6.8 MCAN Nominal Bit Timing and Prescaler Register Name: Offset: Reset: Property: MCAN_NBTP 0x1C 0x06000A03 Read/Write This register can only be written if the bits CCE and INIT are set in MCAN_CCCR. The CAN bit time may be programmed in the range of 4 to 385 time quanta. The CAN time quantum may be programmed in the range of 1 to 512 CAN core clock periods. tq = tcore clock x (NBRP + 1). NTSEG1 is the sum of Prop_Seg and Phase_Seg1.
PAGE 1445
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) 49.6.9 MCAN Timestamp Counter Configuration Register Name: Offset: Reset: Property: MCAN_TSCC 0x20 0x00000000 Read/Write For a description of the Timestamp Counter see Timestamp Generation. With CAN FD, an external counter is required for timestamp generation (TSS = 2).
PAGE 1446
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) 49.6.
PAGE 1447
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) 49.6.11 MCAN Timeout Counter Configuration Register Name: Offset: Reset: Property: MCAN_TOCC 0x28 0xFFFF0000 Read/Write This register can only be written if the bits CCE and INIT are set in MCAN CC Control Register. For a description of the Timeout Counter, see Timeout Counter.
PAGE 1448
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) 49.6.
PAGE 1449
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) 49.6.13 MCAN Error Counter Register Name: Offset: Reset: Property: MCAN_ECR 0x40 0x00000000 Read-only When MCAN_CCCR.ASM is set, the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected, but CEL is still incremented.
PAGE 1450
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) 49.6.
PAGE 1451
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) Bits 10:8 – DLEC[2:0] Data Phase Last Error Code (set to 111 on read) Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. Coding is the same as for LEC. This field will be cleared to zero when a CAN FD format frame with its BRS flag set has been transferred (reception or transmission) without error. Bit 7 – BO Bus_Off Status Value Description 0 The MCAN is not Bus_Off. 1 The MCAN is in Bus_Off state.
PAGE 1452
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) 49.6.
PAGE 1453
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) 49.6.16 MCAN Interrupt Register Name: Offset: Reset: Property: MCAN_IR 0x50 0x00000000 Read/Write The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the processor clears them. A flag is cleared by writing a ‘1’ to the corresponding bit position. Writing a ‘0’ has no effect. A hard reset will clear the register. The configuration of IE controls whether an interrupt is generated.
PAGE 1454
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) Bit 24 – EW Value 0 1 Warning Status Description Error_Warning status unchanged. Error_Warning status changed. Bit 23 – EP Value 0 1 Error Passive Description Error_Passive status unchanged. Error_Passive status changed. Bit 22 – ELO Error Logging Overflow Value Description 0 CAN Error Logging Counter did not overflow. 1 Overflow of CAN Error Logging Counter occurred.
PAGE 1455
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) Bit 13 – TEFW Tx Event FIFO Watermark Reached Value Description 0 Tx Event FIFO fill level below watermark. 1 Tx Event FIFO fill level reached watermark. Bit 12 – TEFN Tx Event FIFO New Entry Value Description 0 Tx Event FIFO unchanged. 1 Tx Handler wrote Tx Event FIFO element. Bit 11 – TFE Tx FIFO Empty Value Description 0 Tx FIFO non-empty. 1 Tx FIFO empty.
PAGE 1456
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) Value 0 1 Description Receive FIFO 0 not full. Receive FIFO 0 full. Bit 1 – RF0W Receive FIFO 0 Watermark Reached Value Description 0 Receive FIFO 0 fill level below watermark. 1 Receive FIFO 0 fill level reached watermark. Bit 0 – RF0N Receive FIFO 0 New Message Value Description 0 No new message written to Receive FIFO 0. 1 New message written to Receive FIFO 0. © 2019 Microchip Technology Inc.
PAGE 1457
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) 49.6.17 MCAN Interrupt Enable Register Name: Offset: Reset: Property: MCAN_IE 0x54 0x00000000 Read/Write The following configuration values are valid for all listed bit names of this register: 0: Disables the corresponding interrupt. 1: Enables the corresponding interrupt.
PAGE 1458
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) Bit 15 – TEFLE Tx Event FIFO Event Lost Interrupt Enable Bit 14 – TEFFE Tx Event FIFO Full Interrupt Enable Bit 13 – TEFWE Tx Event FIFO Watermark Reached Interrupt Enable Bit 12 – TEFNE Tx Event FIFO New Entry Interrupt Enable Bit 11 – TFEE Tx FIFO Empty Interrupt Enable Bit 10 – TCFE Transmission Cancellation Finished Interrupt Enable Bit 9 – TCE Transmission Completed Interrupt Enable Bit 8 – HPME High Priority Message Interrupt Enable Bit 7 – RF1
PAGE 1459
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) 49.6.18 MCAN Interrupt Line Select Register Name: Offset: Reset: Property: MCAN_ILS 0x58 0x00000000 Read/Write The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the Interrupt Register to one of the two module interrupt lines. 0: Interrupt assigned to interrupt line MCAN_INT0. 1: Interrupt assigned to interrupt line MCAN_INT1.
PAGE 1460
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) Bit 15 – TEFLL Tx Event FIFO Event Lost Interrupt Line Bit 14 – TEFFL Tx Event FIFO Full Interrupt Line Bit 13 – TEFWL Tx Event FIFO Watermark Reached Interrupt Line Bit 12 – TEFNL Tx Event FIFO New Entry Interrupt Line Bit 11 – TFEL Tx FIFO Empty Interrupt Line Bit 10 – TCFL Transmission Cancellation Finished Interrupt Line Bit 9 – TCL Transmission Completed Interrupt Line Bit 8 – HPML High Priority Message Interrupt Line Bit 7 – RF1LL Receive FIFO
PAGE 1461
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) 49.6.19 MCAN Interrupt Line Enable Name: Offset: Reset: Property: MCAN_ILE 0x5C 0x00000000 Read/Write Each of the two interrupt lines to the processor can be enabled/disabled separately by programming bits EINT0 and EINT1.
PAGE 1462
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) 49.6.20 MCAN Global Filter Configuration Name: Offset: Reset: Property: MCAN_GFC 0x80 0x00000000 Read/Write Global settings for Message ID filtering. The Global Filter Configuration controls the filter path for standard and extended messages as illustrated in Standard Message ID Filter Path and Extended Message ID Filter Path. This register can only be written if the bits CCE and INIT are set in MCAN CC Control Register.
PAGE 1463
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) 49.6.21 MCAN Standard ID Filter Configuration Name: Offset: Reset: Property: MCAN_SIDFC 0x84 0x00000000 Read/Write Settings for 11-bit standard Message ID filtering. The Standard ID Filter Configuration controls the filter path for standard messages as illustrated in Standard Message ID Filter Path. This register can only be written if the bits CCE and INIT are set in MCAN CC Control Register.
PAGE 1464
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) 49.6.22 MCAN Extended ID Filter Configuration Name: Offset: Reset: Property: MCAN_XIDFC 0x88 0x00000000 Read/Write Settings for 29-bit extended Message ID filtering. The Extended ID Filter Configuration controls the filter path for standard messages as described in Extended Message ID Filter Path. This register can only be written if the bits CCE and INIT are set in MCAN CC Control Register.
PAGE 1465
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) 49.6.23 MCAN Extended ID AND Mask Name: Offset: Reset: Property: MCAN_XIDAM 0x90 0x1FFFFFFF Read/Write This register can only be written if the bits CCE and INIT are set in MCAN CC Control Register.
PAGE 1466
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) 49.6.24 MCAN High Priority Message Status Name: Offset: Reset: Property: MCAN_HPMS 0x94 0x00000000 Read-only This register is updated every time a Message ID filter element configured to generate a priority event matches. This can be used to monitor the status of incoming high priority messages and to enable fast access to these messages.
PAGE 1467
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) 49.6.
PAGE 1468
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) 49.6.
PAGE 1469
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) 49.6.27 MCAN Receive FIFO 0 Configuration Name: Offset: Reset: Property: MCAN_RXF0C 0xA0 0x00000000 Read/Write This register can only be written if the bits CCE and INIT are set in MCAN CC Control Register.
PAGE 1470
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) 49.6.
PAGE 1471
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) 49.6.
PAGE 1472
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) 49.6.
PAGE 1473
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) 49.6.31 MCAN Receive FIFO 1 Configuration Name: Offset: Reset: Property: MCAN_RXF1C 0xB0 0x00000000 Read/Write This register can only be written if the bits CCE and INIT are set in MCAN CC Control Register.
PAGE 1474
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) 49.6.
PAGE 1475
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) 49.6.
PAGE 1476
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) 49.6.34 MCAN Receive Buffer / FIFO Element Size Configuration Name: Offset: Reset: Property: MCAN_RXESC 0xBC 0x00000000 Read/Write This register can only be written if the bits CCE and INIT are set in MCAN CC Control Register. Configures the number of data bytes belonging to a Receive Buffer / Receive FIFO element. Data field sizes >8 bytes are intended for CAN FD operation only.
PAGE 1477
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) Bits 2:0 – F0DS[2:0] Receive FIFO 0 Data Field Size Value Name Description 0 8_BYTE 8-byte data field 1 12_BYTE 12-byte data field 2 16_BYTE 16-byte data field 3 20_BYTE 20-byte data field 4 24_BYTE 24-byte data field 5 32_BYTE 32-byte data field 6 48_BYTE 48-byte data field 7 64_BYTE 64-byte data field © 2019 Microchip Technology Inc.
PAGE 1478
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) 49.6.35 MCAN Tx Buffer Configuration Name: Offset: Reset: Property: MCAN_TXBC 0xC0 0x00000000 Read/Write This register can only be written if the bits CCE and INIT are set in MCAN CC Control Register. The sum of TFQS and NDTB may not exceed 32. There is no check for erroneous configurations. The Tx Buffers section in the Message RAM starts with the dedicated Tx Buffers.
PAGE 1479
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) 49.6.36 MCAN Tx FIFO/Queue Status Name: Offset: Reset: Property: MCAN_TXFQS 0xC4 0x00000000 Read-only The Tx FIFO/Queue status is related to the pending Tx requests listed in register MCAN_TXBRP. Therefore the effect of Add/Cancellation requests may be delayed due to a running Tx scan (MCAN_TXBRP not yet updated).
PAGE 1480
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) 49.6.37 MCAN Tx Buffer Element Size Configuration Name: Offset: Reset: Property: MCAN_TXESC 0xC8 0x00000000 Read/Write This register can only be written if the bits CCE and INIT are set in MCAN CC Control Register. Configures the number of data bytes belonging to a Tx Buffer element. Data field sizes > 8 bytes are intended for CAN FD operation only.
PAGE 1481
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) 49.6.38 MCAN Transmit Buffer Request Pending Name: Offset: Reset: Property: MCAN_TXBRP 0xCC 0x00000000 Read-only MCAN_TXBRP bits which are set while a Tx scan is in progress are not considered during this particular Tx scan. In case a cancellation is requested for such a Tx Buffer, this Add Request is cancelled immediately, the corresponding MCAN_TXBRP bit is reset.
PAGE 1482
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) 49.6.39 MCAN Transmit Buffer Add Request Name: Offset: Reset: Property: MCAN_TXBAR 0xD0 0x00000000 Read/Write If an add request is applied for a Transmit Buffer with pending transmission request (corresponding MCAN_TXBRP bit already set), this Add Request is ignored.
PAGE 1483
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) 49.6.
PAGE 1484
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) 49.6.
PAGE 1485
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) 49.6.
PAGE 1486
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) 49.6.
PAGE 1487
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) 49.6.
PAGE 1488
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) 49.6.45 MCAN Transmit Event FIFO Configuration Name: Offset: Reset: Property: MCAN_TXEFC 0xF0 0x00000000 Read/Write This register can only be written if the bits CCE and INIT are set in MCAN CC Control Register.
PAGE 1489
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) 49.6.
PAGE 1490
SAM E70/S70/V70/V71 Family Controller Area Network (MCAN) 49.6.
PAGE 1491
SAM E70/S70/V70/V71 Family Timer Counter (TC) 50. Timer Counter (TC) 50.1 Description A Timer Counter (TC) module includes three identical TC channels. The number of implemented TC modules is device-specific. Each TC channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation.
PAGE 1492
SAM E70/S70/V70/V71 Family Timer Counter (TC) 50.3 Block Diagram Table 50-1. Timer Counter Clock Assignment Name Definition TIMER_CLOCK1 PCK6 or PCK7 (TC0 only) TIMER_CLOCK2 MCK/8 TIMER_CLOCK3 MCK/32 TIMER_CLOCK4 MCK/128 TIMER_CLOCK5 (1) SLCK 1. 2. When SLCK is selected for Peripheral Clock (CSS = 0 in PMC Master Clock register), SLCK input is equivalent to Peripheral Clock. The PCK6 or PCK7 (TC0 only) frequency must be at least three times lower than peripheral clock frequency. Figure 50-1.
PAGE 1493
SAM E70/S70/V70/V71 Family Timer Counter (TC) ...........continued 50.4 Signal Name Description TIOBx Capture Mode: Timer Counter Input Waveform Mode: Timer Counter Input/Output INT Interrupt Signal Output (internal signal) SYNC Synchronization Input Signal (from configuration register) Pin List Table 50-3. Pin List Pin Name Description Type TCLK0–TCLK2 External Clock Input Input TIOA0–TIOA2 I/O Line A I/O TIOB0–TIOB2 I/O Line B I/O 50.5 Product Dependencies 50.5.
PAGE 1494
SAM E70/S70/V70/V71 Family Timer Counter (TC) The current value of the counter is accessible in real time by reading the Counter Value register (TC_CV). The counter can be reset by a trigger. In this case, the counter value passes to zero on the next valid edge of the selected clock. 50.6.
PAGE 1495
SAM E70/S70/V70/V71 Family Timer Counter (TC) Figure 50-3. Clock Selection TCCLKS TIMER_CLOCK1 CLKI Synchronous Edge Detection TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 Selected Clock TIMER_CLOCK5 XC0 XC1 XC2 Peripheral Clock BURST 1 50.6.4 Clock Control The clock of each counter can be controlled in two different ways: it can be enabled/disabled and started/stopped, as shown in the following figure.
PAGE 1496
SAM E70/S70/V70/V71 Family Timer Counter (TC) 50.6.5 Operating Modes Each channel can operate independently in two different modes: • • Capture mode provides measurement on signals. Waveform mode provides wave generation. The TC operating mode is programmed with TC_CMRx.WAVE. In Capture mode, TIOAx and TIOBx are configured as inputs. In Waveform mode, TIOAx is always configured to be an output and TIOBx is an output if it is not selected to be the external trigger. 50.6.
PAGE 1497
SAM E70/S70/V70/V71 Family Timer Counter (TC) When DMA is used (on channel 0), the Register AB (TC_RAB) address must be configured as source address of the transfer. TC_RAB provides the next unread value from TC_RA and TC_RB. It may be read by the DMA after a request has been triggered upon loading TC_RA or TC_RB. 50.6.9 Transfer with DMAC in Capture Mode The DMAC can perform access from the TC to system memory in Capture mode only.
PAGE 1498
SAM E70/S70/V70/V71 Family Timer Counter (TC) Figure 50-6.
PAGE 1499
SAM E70/S70/V70/V71 Family Timer Counter (TC) Figure 50-7.
PAGE 1500
SAM E70/S70/V70/V71 Family Timer Counter (TC) Figure 50-8. WAVSEL = 00 without Trigger Counter Value Counter cleared by compare match with 0xFFFF 0xFFFF RC RB RA Time Waveform Examples TIOB TIOA Figure 50-9. WAVSEL = 00 with Trigger Counter Value Counter cleared by compare match with 0xFFFF 0xFFFF Counter cleared by trigger RC RB RA Time Waveform Examples TIOB TIOA 50.6.12.
PAGE 1501
SAM E70/S70/V70/V71 Family Timer Counter (TC) Figure 50-10. WAVSEL = 10 without Trigger Counter Value 2n-1 (n = counter size) Counter cleared by compare match with RC RC RB RA Time Waveform Examples TIOB TIOA Figure 50-11. WAVSEL = 10 with Trigger Counter Value 2n-1 (n = counter size) Counter cleared by compare match with RC Counter cleared by trigger RC RB RA Time Waveform Examples TIOB TIOA 50.6.12.3 WAVSEL = 01 When WAVSEL = 01, the value of TC_CV is incremented from 0 to 216-1 .
PAGE 1502
SAM E70/S70/V70/V71 Family Timer Counter (TC) Figure 50-12. WAVSEL = 01 without Trigger Counter Value Counter decremented by compare match with 0xFFFF 0xFFFF RC RB RA Time Waveform Examples TIOB TIOA Figure 50-13. WAVSEL = 01 with Trigger Counter Value Counter decremented by compare match with 0xFFFF 0xFFFF Counter decremented by trigger RC RB Counter incremented by trigger RA Time Waveform Examples TIOB TIOA 50.6.12.
PAGE 1503
SAM E70/S70/V70/V71 Family Timer Counter (TC) Figure 50-14. WAVSEL = 11 without Trigger Counter Value 2n-1 (n = counter size) Counter decremented by compare match with RC RC RB RA Time Waveform Examples TIOB TIOA Figure 50-15. WAVSEL = 11 with Trigger Counter Value 2n-1 (n = counter size) Counter decremented by compare match with RC RC Counter decremented by trigger RB Counter incremented by trigger RA Time Waveform Examples TIOB TIOA 50.6.
PAGE 1504
SAM E70/S70/V70/V71 Family Timer Counter (TC) 50.6.14 Synchronization with PWM The inputs TIOAx/TIOBx can be bypassed, and thus channel trigger/capture events can be directly driven by the independent PWM module. PWM comparator outputs (internal signals without dead-time insertion - OCx), respectively source of the PWMH/ L[2:0] outputs, are routed to the internal TC inputs. These specific TC inputs are multiplexed with TIOA/B input signal to drive the internal trigger/capture events.
PAGE 1505
SAM E70/S70/V70/V71 Family Timer Counter (TC) 50.6.15 Output Controller The output controller defines the output level changes on TIOAx and TIOBx following an event. TIOBx control is used only if TIOBx is defined as output (not as an external event). The following events control TIOAx and TIOBx: • • • Software trigger External event RC compare RA Compare controls TIOAx, and RB Compare controls TIOBx.
PAGE 1506
SAM E70/S70/V70/V71 Family Timer Counter (TC) Figure 50-17. Predefined Connection of the Quadrature Decoder with Timer Counters Reset pulse SPEEDEN Quadrature Decoder 1 1 (Filter + Edge Detect + QD) TIOA Timer Counter Channel 0 TIOA0 QDEN PHEdges 1 TIOB 1 XC0 TIOB0 TIOA0 PHA TIOB0 PHB TIOB1 IDX XC0 Speed/Position QDEN Index 1 TIOB TIOB1 1 XC0 Timer Counter Channel 1 XC0 Rotation Direction Timer Counter Channel 2 Speed Time Base 50.6.16.
PAGE 1507
SAM E70/S70/V70/V71 Family Timer Counter (TC) Figure 50-18. Input Stage Input Preprocessing MAXFILT SWAP 1 MAXFILT > 0 PHA Filter TIOA0 1 PHedge Direction and Edge Detection INVA 1 PHB Filter TIOB0 1 DIR 1 IDX INVB 1 1 IDX Filter TIOB1 IDXPHB INVIDX Input filtering can efficiently remove spurious pulses that might be generated by the presence of particulate contamination on the optical or magnetic disk of the rotary sensor.
PAGE 1508
SAM E70/S70/V70/V71 Family Timer Counter (TC) Figure 50-19. Filtering Examples MAXFILT = 2 Peripheral Clock particulate contamination PHA,B Filter Out Optical/Magnetic disk strips PHA PHB motor shaft stopped so that rotary sensor cell is aligned with an edge of the disk rotation stop PHA PHB Edge area due to system vibration PHB stop Resulting PHA, PHB electrical waveforms PHA mechanical shock on system PHB vibration PHA, PHB electrical waveforms after filtering PHA PHB 50.6.16.
PAGE 1509
SAM E70/S70/V70/V71 Family Timer Counter (TC) Any change in rotation direction is reported in the TC_QISR and can generate an interrupt. The direction change condition is reported as soon as two consecutive edges on a phase signal have sampled the same value on the other phase signal and there is an edge on the other signal.
PAGE 1510
SAM E70/S70/V70/V71 Family Timer Counter (TC) Figure 50-21. Quadrature Error Detection MAXFILT = 2 Peripheral Clock Abnormally formatted optical disk strips (theoretical view) PHA PHB strip edge inaccuracy due to disk etching/printing process PHA PHB resulting PHA, PHB electrical waveforms PHA Even with an abnormally formatted disk, there is no occurrence of PHA, PHB switching at the same time.
PAGE 1511
SAM E70/S70/V70/V71 Family Timer Counter (TC) This time base is automatically fed back to TIOAx of channel 0 when QDEN and SPEEDEN are set. Channel 0 must be configured in Capture mode (WAVE = 0 in TC_CMR0). TC_CMR0.ABETRG must be configured at 1 to select TIOAx as a trigger for this channel.
PAGE 1512
SAM E70/S70/V70/V71 Family Timer Counter (TC) Figure 50-22. Detection and Autocorrection of Missing Pulses Missing pulse due to a contamination (dust, scratch, etc.) PHA PHB detection Not a change of direction corrections 1 2 3 4 5 6 7 10 12 13 14 15 16 If a quadrature device is undamaged, the number of pulses counted for a predefined period of time must be the same with or without detection and autocorrection feature.
PAGE 1513
SAM E70/S70/V70/V71 Family Timer Counter (TC) It is possible to trigger the FAULT output of the TIMER1 with CPCS from TC_SR0 and/or CPCS from TC_SR1. Each source can be independently enabled/disabled in the TC_FMR. This can be useful to detect an overflow on speed and/or position when QDEC is processed and to act immediately by using the FAULT output. Figure 50-24. Fault Output Generation TC_SR0 flag CPCS AND OR TC_FMR / ENCF0 TC_SR1 flag CPCS FAULT (to PWM input) AND TC_FMR / ENCF1 50.6.
PAGE 1514
SAM E70/S70/V70/V71 Family Timer Counter (TC) 50.7 Register Summary Note: The register TC_CMR has two modes, Capture Mode and Waveform Mode. In this register summary, both modes are displayed Offset Name 0x00 TC_CCR0 0x04 TC_CMR0 0x04 TC_CMR0 0x08 TC_SMMR0 0x0C TC_RAB0 0x10 TC_CV0 0x14 TC_RA0 0x18 TC_RB0 0x1C TC_RC0 0x20 TC_SR0 0x24 TC_IER0 0x28 TC_IDR0 0x2C TC_IMR0 Bit Pos.
PAGE 1515
SAM E70/S70/V70/V71 Family Timer Counter (TC) ...........continued Offset Name Bit Pos. 0x30 TC_EMR0 7:0 15:8 23:16 31:24 0x34 ...
PAGE 1516
SAM E70/S70/V70/V71 Family Timer Counter (TC) ...........continued Offset Name Bit Pos. 0x70 TC_EMR1 7:0 15:8 23:16 31:24 0x74 ...
PAGE 1517
SAM E70/S70/V70/V71 Family Timer Counter (TC) ...........continued Offset Name Bit Pos. 0xB0 TC_EMR2 7:0 15:8 23:16 31:24 0xB4 ... 0xBF Reserved 0xC0 TC_BCR 0xC4 TC_BMR 0xC8 TC_QIER 0xCC 0xD0 0xD4 TC_QIDR TC_QIMR TC_QISR 0xD8 TC_FMR 0xDC ...
PAGE 1518
SAM E70/S70/V70/V71 Family Timer Counter (TC) 50.7.1 TC Channel Control Register Name: Offset: Reset: Property: Bit TC_CCRx 0x00 + x*0x40 [x=0..2] – Write-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 SWTRG W – 1 CLKDIS W – 0 CLKEN W – Access Reset Bit Access Reset Bit Access Reset Bit Access Reset Bit 2 – SWTRG Software Trigger Command Value Description 0 No effect.
PAGE 1519
SAM E70/S70/V70/V71 Family Timer Counter (TC) 50.7.2 TC Channel Mode Register: Capture Mode Name: Offset: Reset: Property: TC_CMRx 0x04 + x*0x40 [x=0..2] 0x00000000 Read/Write This register can be written only if the WPEN bit is cleared in the TC Write Protection Mode Register.
PAGE 1520
SAM E70/S70/V70/V71 Family Timer Counter (TC) Bit 14 – CPCTRG RC Compare Trigger Enable Value Description 0 RC Compare has no effect on the counter and its clock. 1 RC Compare resets the counter and starts the counter clock. Bit 10 – ABETRG TIOAx or TIOBx External Trigger Selection Value Description 0 TIOBx is used as an external trigger. 1 TIOAx is used as an external trigger. Bits 9:8 – ETRGEDG[1:0] External Trigger Edge Selection Value Name Description 0 NONE The clock is not gated by an external signal.
PAGE 1521
SAM E70/S70/V70/V71 Family Timer Counter (TC) 50.7.3 TC Channel Mode Register: Waveform Mode Name: Offset: Reset: Property: TC_CMRx 0x04 + x*0x40 [x=0..2] 0x00000000 Read/Write This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register.
PAGE 1522
SAM E70/S70/V70/V71 Family Timer Counter (TC) Bits 23:22 – ASWTRG[1:0] Software Trigger Effect on TIOAx Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle Bits 21:20 – AEEVT[1:0] External Event Effect on TIOAx Value Name 0 NONE 1 SET 2 CLEAR 3 TOGGLE Description None Set Clear Toggle Bits 19:18 – ACPC[1:0] RC Compare Effect on TIOAx Value Name 0 NONE 1 SET 2 CLEAR 3 TOGGLE Description None Set Clear Toggle Bits 17:16 – ACPA[1:0] RA Compare Effect on TIOAx Value Name 0 NONE 1 SET
PAGE 1523
SAM E70/S70/V70/V71 Family Timer Counter (TC) ...........continued Value Name Description TIOB Direction 3 XC2 XC2 Output Note: If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms and subsequently no IRQs.
PAGE 1524
SAM E70/S70/V70/V71 Family Timer Counter (TC) 50.7.4 TC Stepper Motor Mode Register Name: Offset: Reset: Property: TC_SMMRx 0x08 + x*0x40 [x=0..2] 0x00000000 R/W This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register.
PAGE 1525
SAM E70/S70/V70/V71 Family Timer Counter (TC) 50.7.5 TC Register AB Name: Offset: Reset: Property: Bit 31 TC_RABx 0x0C + x*0x40 [x=0..
PAGE 1526
SAM E70/S70/V70/V71 Family Timer Counter (TC) 50.7.6 TC Counter Value Register Name: Offset: Reset: Property: Bit 31 TC_CVx 0x10 + x*0x40 [x=0..
PAGE 1527
SAM E70/S70/V70/V71 Family Timer Counter (TC) 50.7.7 TC Register A Name: Offset: Reset: Property: TC_RAx 0x14 + x*0x40 [x=0..2] 0x00000000 Read/Write This register has access Read-only if TC_CMRx.WAVE = 0, Read/Write if TC_CMRx.WAVE = 1. This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register.
PAGE 1528
SAM E70/S70/V70/V71 Family Timer Counter (TC) 50.7.8 TC Register B Name: Offset: Reset: Property: TC_RBx 0x18 + x*0x40 [x=0..2] 0x00000000 Read/Write This register has access Read-only if TC_CMRx.WAVE = 0, Read/Write if TC_CMRx.WAVE = 1. This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register.
PAGE 1529
SAM E70/S70/V70/V71 Family Timer Counter (TC) 50.7.9 TC Register C Name: Offset: Reset: Property: TC_RCx 0x1C + x*0x40 [x=0..2] 0x00000000 Read/Write This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register.
PAGE 1530
SAM E70/S70/V70/V71 Family Timer Counter (TC) 50.7.10 TC Interrupt Status Register Name: Offset: Reset: Property: Bit TC_SRx 0x20 + x*0x40 [x=0..
PAGE 1531
SAM E70/S70/V70/V71 Family Timer Counter (TC) Value 0 1 Description RA Load has not occurred since the last read of the Status Register or TC_CMRx.WAVE = 1. RA Load has occurred since the last read of the Status Register, if TC_CMRx.WAVE = 0. Bit 4 – CPCS RC Compare Status (cleared on read) Value Description 0 RC Compare has not occurred since the last read of the Status Register. 1 RC Compare has occurred since the last read of the Status Register.
PAGE 1532
SAM E70/S70/V70/V71 Family Timer Counter (TC) 50.7.11 TC Interrupt Enable Register Name: Offset: Reset: Property: TC_IERx 0x24 + x*0x40 [x=0..2] – Write-only The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Enables the corresponding interrupt.
PAGE 1533
SAM E70/S70/V70/V71 Family Timer Counter (TC) 50.7.12 TC Interrupt Disable Register Name: Offset: Reset: Property: TC_IDRx 0x28 + x*0x40 [x=0..2] – Write-only The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Disables the corresponding interrupt.
PAGE 1534
SAM E70/S70/V70/V71 Family Timer Counter (TC) 50.7.13 TC Interrupt Mask Register Name: Offset: Reset: Property: TC_IMRx 0x2C + x*0x40 [x=0..2] 0x00000000 Read-only The following configuration values are valid for all listed bit names of this register: 0: The corresponding interrupt is not enabled. 1: The corresponding interrupt is enabled.
PAGE 1535
SAM E70/S70/V70/V71 Family Timer Counter (TC) 50.7.14 TC Extended Mode Register Name: Offset: Reset: Property: TC_EMRx 0x30 + x*0x40 [x=0..2] 0x00000000 Read/Write This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register.
PAGE 1536
SAM E70/S70/V70/V71 Family Timer Counter (TC) 50.7.15 TC Block Control Register Name: Offset: Reset: Property: Bit TC_BCR 0xC0 – Write-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SYNC W – Access Reset Bit Access Reset Bit Access Reset Bit Access Reset Bit 0 – SYNC Synchro Command Value Description 0 No effect. 1 Asserts the SYNC signal which generates a software trigger simultaneously for each of the channels.
PAGE 1537
SAM E70/S70/V70/V71 Family Timer Counter (TC) 50.7.16 TC Block Mode Register Name: Offset: Reset: Property: TC_BMR 0xC4 0x00000000 Read/Write This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register.
PAGE 1538
SAM E70/S70/V70/V71 Family Timer Counter (TC) Value 1 Description IDX is inverted before driving the QDEC. Bit 14 – INVB Inverted PHB Value Description 0 PHB (TIOB0) is directly driving the QDEC. 1 PHB is inverted before driving the QDEC. Bit 13 – INVA Inverted PHA Value Description 0 PHA (TIOA0) is directly driving the QDEC. 1 PHA is inverted before driving the QDEC. Bit 12 – EDGPHA Edge on PHA Count Mode Value Description 0 Edges are detected on PHA only. 1 Edges are detected on both PHA and PHB.
PAGE 1539
SAM E70/S70/V70/V71 Family Timer Counter (TC) Value 0 1 2 3 Name TCLK0 – TIOA1 TIOA2 © 2019 Microchip Technology Inc.
PAGE 1540
SAM E70/S70/V70/V71 Family Timer Counter (TC) 50.7.17 TC QDEC Interrupt Enable Register Name: Offset: Reset: Property: Bit TC_QIER 0xC8 – Write-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 MPE W – 2 QERR W – 1 DIRCHG W – 0 IDX W – Access Reset Bit Access Reset Bit Access Reset Bit Access Reset Bit 3 – MPE Value 0 1 Consecutive Missing Pulse Error Description No effect.
PAGE 1541
SAM E70/S70/V70/V71 Family Timer Counter (TC) 50.7.18 TC QDEC Interrupt Disable Register Name: Offset: Reset: Property: Bit TC_QIDR 0xCC – Write-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 MPE W – 2 QERR W – 1 DIRCHG W – 0 IDX W – Access Reset Bit Access Reset Bit Access Reset Bit Access Reset Bit 3 – MPE Value 0 1 Consecutive Missing Pulse Error Description No effect.
PAGE 1542
SAM E70/S70/V70/V71 Family Timer Counter (TC) 50.7.
PAGE 1543
SAM E70/S70/V70/V71 Family Timer Counter (TC) 50.7.20 TC QDEC Interrupt Status Register Name: Offset: Reset: Property: Bit TC_QISR 0xD4 0x00000000 Read-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 DIR R 0 7 6 5 4 3 MPE R 0 2 QERR R 0 1 DIRCHG R 0 0 IDX R 0 Access Reset Bit Access Reset Bit Access Reset Bit Access Reset Bit 8 – DIR Direction Returns an image of the current rotation direction.
PAGE 1544
SAM E70/S70/V70/V71 Family Timer Counter (TC) 50.7.21 TC Fault Mode Register Name: Offset: Reset: Property: TC_FMR 0xD8 0x00000000 Read/Write This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register.
PAGE 1545
SAM E70/S70/V70/V71 Family Timer Counter (TC) 50.7.
PAGE 1546
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) 51. Pulse Width Modulation Controller (PWM) 51.1 Description The Pulse Width Modulation Controller (PWM) generates output pulses on 4 channels independently according to parameters defined per channel. Each channel controls two complementary square output waveforms.
PAGE 1547
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) • • • • • • • • – Independent Update Time Selection of Double Buffering Registers (Polarity, Duty Cycle) for Each Channel, at Each Period for Left-Aligned or Center-Aligned Configuration External Trigger Input Management (e.g.
PAGE 1548
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) 51.3 Block Diagram Figure 51-1. Pulse Width Modulation Controller Block Diagram PWM Controller PPM = Push-Pull Mode Channel x Update Period OCx Comparator Duty-Cycle Clock Selector Counter Channel x 1 PPM DTOHx Dead-Time Generator DTOLx Output Override PWMHx OOOHx Fault OOOLx Protection PWMHx PWMLx PWMLx 0 SYNCx 0 PWMEXTRG2 PIO Glitch Filter 1 PWMEXTRG1 Update PWM_ETRG2.
PAGE 1549
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) Table 51-1. I/O Line Description 51.5 51.5.1 Name Description Type PWMHx PWM Waveform Output High for channel x Output PWMLx PWM Waveform Output Low for channel x Output PWMFIx PWM Fault Input x Input PWMEXTRGy PWM Trigger Input y Input Product Dependencies I/O Lines The pins used for interfacing the PWM are multiplexed with PIO lines.
PAGE 1551
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) Note: 1. FPOL field in PWMC_FMR. 51.6 Functional Description The PWM controller is primarily composed of a clock generator module and 4 channels. • • • 51.6.1 Clocked by the peripheral clock, the clock generator module provides 13 clocks. Each channel can independently choose one of the clock generator outputs.
PAGE 1552
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) After a reset of the PWM controller, DIVA (DIVB) and PREA (PREB) are set to ‘0’. This implies that after reset clkA (clkB) are turned off. At reset, all clocks provided by the modulo n counter are turned off except the peripheral clock. This situation is also true when the PWM peripheral clock is turned off through the Power Management Controller. CAUTION 51.6.
PAGE 1553
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) • • the clock selection. The channel counter is clocked by one of the clocks provided by the clock generator described in the previous section. This channel parameter is defined in the CPRE field of the PWM Channel Mode Register (PWM_CMRx). This field is reset at ‘0’. the waveform period. This channel parameter is defined in the CPRD field of the PWM_CPRDx register.
PAGE 1554
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) Figure 51-4. Non-Overlapped Center-Aligned Waveforms No overlap OC0 OC1 Period Note: See the figure Waveform Properties for a detailed description of center-aligned waveforms. When center-aligned, the channel counter increases up to CPRD and decreases down to 0. This ends the period. When left-aligned, the channel counter increases up to CPRD and is reset. This ends the period.
PAGE 1555
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) Figure 51-5.
PAGE 1556
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) 51.6.2.3 Trigger Selection for Timer Counter The PWM controller can be used as a trigger source for the Timer Counter (TC) to achieve the two application examples described below. 51.6.2.3.1 Delay Measurement To measure the delay between the channel x comparator output (OCx) and the feedback from the bridge driver of the MOSFETs (see the figure below), the bit TCTS in the PWM Channel Mode Register must be at 0.
PAGE 1557
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) Figure 51-7.
PAGE 1558
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) When GCEN0 is set to ‘1’, channels 0 and 1 outputs are driven with gray counter. Figure 51-8. 2-bit Gray Up/Down Counter GCEN0 = 1 PWMH0 PWML0 PWMH1 PWML1 DOWNx 51.6.2.5 Dead-Time Generator The dead-time generator uses the comparator output OCx to provide the two complementary outputs DTOHx and DTOLx, which allows the PWM macrocell to drive external power control switches safely.
PAGE 1559
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) Figure 51-9. Complementary Output Waveforms Output waveform OCx CPOLx = 0 Output waveform DTOHx DTHIx = 0 Output waveform DTOLx DTLIx = 0 Output waveform DTOHx DTHIx = 1 Output waveform DTOLx DTLIx = 1 DTHx DTLx DTHx DTLx Output waveform OCx CPOLx = 1 Output waveform DTOHx DTHIx = 0 Output waveform DTOLx DTLIx = 0 Output waveform DTOHx DTHIx = 1 Output waveform DTOLx DTLIx = 1 51.6.2.5.
PAGE 1560
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) Figure 51-10. PWM Push-Pull Mode PWM Channel x Period Even cycle Odd cycle Odd cycle Even cycle Odd cycle Output Waveform OCx PWM_CMRx.CPOL = 0 Push-Pull Mode Disabled PWM_CMRx.PPM = 0 DTHx Output Waveform DTOHx PWM_CMRx.DTHI = 0 DTLx Output Waveform DTOLx PWM_CMRx.DTLI = 1 Push-Pull Mode Enabled PWM_CMRx.PPM = 1 PWM_CMRx.DPOLI = 0 DTHx Output Waveform DTOHx PWM_CMRx.
PAGE 1561
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) Figure 51-11.
PAGE 1562
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) Figure 51-12.
PAGE 1563
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) Figure 51-13.
PAGE 1564
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) Figure 51-14. Half-Bridge Converter Application: Feedback Regulation C1 VDC + D1 PWMxH L VIN COUT C2 + VOUT D2 + PWMxL PWMx outputs x = [1..2] PWM CONTROLLER PWMEXTRGx x = [1..
PAGE 1565
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) clear registers PWM Output Selection Clear Register (PWM_OSC) and PWM Output Selection Clear Update Register (PWM_OSCUPD) disable the override of the outputs of a channel regardless of other channels. By using buffer registers PWM_OSSUPD and PWM_OSCUPD, the output selection of PWM outputs is done synchronously to the channel counter, at the beginning of the next PWM period.
PAGE 1566
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) (PWM_FCR). In the PWM Fault Status Register (PWM_FSR), the field FIV indicates the current level of the fault inputs and the field FIS indicates whether a fault is currently active. Each fault can be taken into account or not by the fault protection mechanism in each channel. To be taken into account in the channel x, the fault y must be enabled by the bit FPEx[y] in the PWM Fault Protection Enable register (PWM_FPE1).
PAGE 1567
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) channel counter and lasts from the recoverable fault occurrence to the end of the next PWM cycle (if the recoverable fault is no longer present) (see the figure below). The recoverable fault does not trigger an interrupt. The Fault Status FSy (with y = 1 or 2) is not reported in the PWM Fault Status Register when the fault y is a recoverable fault. Figure 51-17.
PAGE 1568
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) 51.6.2.8 Spread Spectrum Counter The PWM macrocell includes a spread spectrum counter allowing the generation of a constantly varying duty cycle on the output PWM waveform (only for the channel 0). This feature may be useful to minimize electromagnetic interference or to reduce the acoustic noise of a PWM driven motor.
PAGE 1569
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) Defining a channel as a synchronous channel while it is an asynchronous channel (by writing the bit SYNCx to ‘1’ while it was at ‘0’) is allowed only if the channel is disabled at this time (CHIDx = 0 in PWM_SR). In the same way, defining a channel as an asynchronous channel while it is a synchronous channel (by writing the SYNCx bit to ‘0’ while it was ‘1’) is allowed only if the channel is disabled at this time.
PAGE 1570
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) 1. 2. 3. 4. 5. 6. Select the manual write of duty-cycle values and the manual update by setting the UPDM field to ‘0’ in the PWM_SCM register. Define the synchronous channels by the SYNCx bits in the PWM_SCM register. Enable the synchronous channels by writing CHID0 in the PWM_ENA register.
PAGE 1571
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) 7. The update of these registers will occur at the beginning of the next PWM period. At this moment the bit UPDULOCK is reset, go to Step 5. for new values. 8. If an update of the duty-cycle values and/or the update period is required, check first that write of new update values is possible by polling the flag WRDY (or by waiting for the corresponding interrupt) in PWM_ISR2. 9.
PAGE 1572
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) • UNRE: this flag is set to ‘1’ when the update period defined by the UPR field has elapsed while the whole data has not been written by the DMA Controller. It is reset to ‘0’ when PWM_ISR2 is read. Depending on the interrupt mask in PWM_IMR2, an interrupt can be generated by these flags. Sequence for Method 3: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13.
PAGE 1573
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) Figure 51-22. Method 3 (UPDM = 2 and PTRM = 1 and PTRCS = 0) CCNT0 CDTYUPD 0x20 UPRUPD 0x1 UPR 0x1 UPRCNT 0x0 CDTY 0x60 0x40 0x80 0xB0 0xA0 0x3 0x3 0x1 0x20 0x0 0x40 0x1 0x0 0x1 0x0 0x1 0x80 0x60 0x2 0x3 0x0 0x1 0x2 0xA0 CMP0 match transfer request WRDY 51.6.2.
PAGE 1574
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) Figure 51-23.
PAGE 1575
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) Figure 51-24. Comparison Waveform CCNT0 0x6 CVUPD 0x6 0x2 CVMVUPD CTRUPD 0x1 0x2 CPRUPD 0x1 0x3 CUPRUPD 0x3 0x2 CV 0x6 0x2 CTR 0x1 0x2 CPR 0x1 0x3 CUPR 0x3 0x2 CUPRCNT 0x0 0x1 0x2 0x3 0x0 0x1 0x2 0x0 0x1 0x2 0x0 0x1 CPRCNT 0x0 0x1 0x0 0x1 0x0 0x1 0x2 0x3 0x0 0x1 0x2 0x3 0x6 CVM Comparison Update CMPU Comparison Match CMPM 51.6.
PAGE 1576
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) Figure 51-26. Event Line Generation Waveform (Example) PWM_CCNTx CPRD(PWM_CPRD0) CV (PWM_CMPV1) CDTY(PWM_CDTY2) CDTY(PWM_CDTY1) CDTY(PWM_CDTY0) CV (PWM_CMPV0) Waveform OC0 Waveform OC1 Waveform OC2 Comparison Unit 0 Output PWM_CMPM0.CEN = 1 Comparison Unit 1 Output PWM_CMPM0.CEN = 1 Event Line 0 (trigger event for ADC) PWM_ELMR0.CSEL0 = 1 PWM_ELMR0.CSEL1 = 1 configurable delay PWM_CMPV0.CV configurable delay PWM_CMPV1.
PAGE 1577
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) Register where x = 1 or 2). Programming the channel to be center-aligned or synchronous while TRGMODE is not 0 could lead to unexpected behavior. 51.6.5.1 External PWM Reset Mode External PWM Reset mode is selected by programming TRGMODE = 1 in the PWM_ETRGx register. In this mode, when an edge is detected on the PWMEXTRGx input, the internal PWM counter is cleared and a new PWM cycle is restarted.
PAGE 1578
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) Figure 51-28. External PWM Reset Mode: Power Factor Correction Application L D IL VIN VAC + CIN COUT VOUT PWMH1 VIN IL IREF Time TRGIN1 TRGEDGE(PWM_ETRG1) = 1 PWMH1 51.6.5.2 External PWM Start Mode External PWM Start mode is selected by programming TRGMODE = 2 in the PWM_ETRGx register.
PAGE 1579
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) Figure 51-29. External PWM Start Mode CNT(PWM_CCNTx) Channel x = [1,2] CPRD(PWM_CPRDx) Channel x = [1,2] tOFF Area CDTY(PWM_CDTYx) Channel x = [1,2] tON Area 0 TRGINx Event TRGEDGE(PWM_ETRGx) = 1 x = [1,2] TRGINx Event TRGEDGE(PWM_ETRGx) = 0 x = [1,2] tON tOFF Minimum tOFF Minimum tOFF Minimum tOFF tON tOFF tON tOFF Output Waveform OCx CPOL(PWM_CMRx) = 1 x = [1,2] Output Waveform OCx CPOL(PWM_CMRx) = 0 x = [1,2] 51.6.5.2.
PAGE 1580
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) Figure 51-30. External PWM Start Mode: Buck DC/DC Converter L IL PWMH1 VDC VIN CIN + D COUT + VOUT switch to high load VOUT VREF Time TRGIN1 TRGEDGE(PWM_ETRG1) = 0 PWMH1 Constant tON tOFF Minimum tOFF 51.6.5.3 Cycle-By-Cycle Duty Mode 51.6.5.3.1 Description Cycle-by-cycle duty mode is selected by programming TRGMODE = 3 in PWM_ETRGx.
PAGE 1581
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) Figure 51-31. Cycle-By-Cycle Duty Mode CNT(PWM_CCNTx) Channel x = [1,2] CPRD(PWM_CPRDx) Channel x = [1,2] CDTY(PWM_CDTYx) Channel x = [1,2] 0 TRGINx Event TRGEDGE(PWM_ETRGx) = 1 x = [1,2] TRGINx Event TRGEDGE(PWM_ETRGx) = 0 x = [1,2] Output Waveform OCx CPOL(PWM_CMRx) = 1 x = [1,2] Output Waveform OCx CPOL(PWM_CMRx) = 0 x = [1,2] 51.6.5.3.
PAGE 1582
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) Figure 51-32. Cycle-By-Cycle Duty Mode: LED String Control L D IL VDC VIN CIN + PWMH0 L COUT + VOUT PWMH1 ILED RSHUNT ILED IREF Time TRGIN1 TRGEDGE(PWM_ETRG1) = 1 PWMH1 51.6.5.4 Leading-Edge Blanking (LEB) PWM channels 1 and 2 support leading-edge blanking. Leading-edge blanking masks the external trigger input when a transient occurs on the corresponding PWM output.
PAGE 1583
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) Figure 51-33. Leading-Edge Blanking Switching Noise Analog Power Signal TRGINx input x = [1,2] Delay Delay Delay Delay Blanking signal on TRGINx x = [1,2] Blanked trigger event x x = [1,2] PWMx Output Waveform x = [1,2] 51.6.6 PWM Controller Operations 51.6.6.
PAGE 1584
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) 51.6.6.2 Source Clock Selection Criteria The large number of source clocks can make selection difficult. The relationship between the value in the PWM Channel Period Register (PWM_CPRDx) and the PWM Channel Duty Cycle Register (PWM_CDTYx) helps the user select the appropriate clock. The event number written in the Period Register gives the PWM accuracy. The DutyCycle quantum cannot be lower than 1/CPRDx value.
PAGE 1585
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) Figure 51-34.
PAGE 1586
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) Figure 51-35. Synchronized Update of Update Period Value of Synchronous Channels User's Writing PWM_SCUPUPD Value PWM_SCUP End of PWM period and end of update period of synchronous channels 51.6.6.5 Changing the Comparison Value and the Comparison Configuration It is possible to change the comparison values and the comparison configurations while the channel 0 is enabled (see PWM Comparison Units).
PAGE 1587
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) Figure 51-36. Synchronized Update of Comparison Values and Configurations User's Writing User's Writing PWM_CMPVUPDx Value Comparison value for comparison x PWM_CMPMUPDx Value Comparison configuration for comparison x PWM_CMPVx PWM_CMPMx End of channel0 PWM period and end of comparison update period and and PWM_CMPMx written End of channel0 PWM period and end of comparison update period 51.6.6.
PAGE 1588
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) • • • – PWM Channel Mode Update Register Register group 3: – PWM Spread Spectrum Register – PWM Spread Spectrum Update Register – PWM Channel Period Register – PWM Channel Period Update Register Register group 4: – PWM Channel Dead Time Register – PWM Channel Dead Time Update Register Register group 5: – PWM Fault Mode Register – PWM Fault Protection Value Register 1 There are two types of write protection: • • SW write protection—can b
PAGE 1589
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) 51.7 Register Summary Offset Name 0x00 PWM_CLK 0x04 PWM_ENA 0x08 PWM_DIS 0x0C PWM_SR 0x10 PWM_IER1 0x14 PWM_IDR1 0x18 PWM_IMR1 0x1C PWM_ISR1 0x20 PWM_SCM 0x24 PWM_DMAR 0x28 PWM_SCUC 0x2C PWM_SCUP 0x30 PWM_SCUPUPD 0x34 PWM_IER2 Bit Pos.
PAGE 1590
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) ...........continued Offset Name 0x38 PWM_IDR2 0x3C PWM_IMR2 0x40 PWM_ISR2 0x44 PWM_OOV 0x48 PWM_OS 0x4C PWM_OSS 0x50 PWM_OSC 0x54 PWM_OSSUPD 0x58 PWM_OSCUPD 0x5C PWM_FMR 0x60 PWM_FSR 0x64 PWM_FCR 0x68 PWM_FPV1 0x6C PWM_FPE 0x70 ... 0x7B Reserved Bit Pos.
PAGE 1591
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) ...........continued Offset Name 0x7C PWM_ELMR0 0x80 PWM_ELMR1 0x84 ... 0x9F Reserved 0xA0 PWM_SSPR 0xA4 PWM_SSPUP 0xA8 ... 0xAF Reserved 0xB0 PWM_SMMR 0xB4 ... 0xBF Reserved 0xC0 PWM_FPV2 0xC4 ... 0xE3 Reserved 0xE4 PWM_WPCR 0xE8 PWM_WPSR 0xEC ... 0x012F Reserved 0x0130 0x0134 0x0138 PWM_CMPV0 PWM_CMPVUPD0 PWM_CMPM0 Bit Pos.
PAGE 1592
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) ...........continued Offset Name 0x013C PWM_CMPMUPD0 0x0140 0x0144 PWM_CMPV1 PWM_CMPVUPD1 0x0148 PWM_CMPM1 0x014C PWM_CMPMUPD1 0x0150 0x0154 PWM_CMPV2 PWM_CMPVUPD2 0x0158 PWM_CMPM2 0x015C PWM_CMPMUPD2 0x0160 0x0164 PWM_CMPV3 PWM_CMPVUPD3 0x0168 PWM_CMPM3 0x016C PWM_CMPMUPD3 0x0170 PWM_CMPV4 Bit Pos.
PAGE 1593
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) ...........continued Offset Name 0x0174 PWM_CMPVUPD4 0x0178 PWM_CMPM4 0x017C PWM_CMPMUPD4 0x0180 0x0184 PWM_CMPV5 PWM_CMPVUPD5 0x0188 PWM_CMPM5 0x018C PWM_CMPMUPD5 0x0190 0x0194 PWM_CMPV6 PWM_CMPVUPD6 0x0198 PWM_CMPM6 0x019C PWM_CMPMUPD6 0x01A0 0x01A4 0x01A8 PWM_CMPV7 PWM_CMPVUPD7 PWM_CMPM7 Bit Pos.
PAGE 1594
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) ...........continued Offset Name Bit Pos. 0x01AC PWM_CMPMUPD7 7:0 15:8 23:16 31:24 0x01B0 ...
PAGE 1595
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) ...........continued Offset Name 0x0234 PWM_CCNT1 0x0238 PWM_DT1 0x023C PWM_DTUPD1 0x0240 PWM_CMR2 0x0244 PWM_CDTY2 0x0248 PWM_CDTYUPD2 0x024C PWM_CPRD2 0x0250 PWM_CPRDUPD2 0x0254 PWM_CCNT2 0x0258 PWM_DT2 0x025C PWM_DTUPD2 0x0260 PWM_CMR3 0x0264 PWM_CDTY3 0x0268 PWM_CDTYUPD3 Bit Pos.
PAGE 1596
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) ...........continued Offset Name 0x026C PWM_CPRD3 0x0270 PWM_CPRDUPD3 0x0274 PWM_CCNT3 0x0278 PWM_DT3 0x027C PWM_DTUPD3 0x0280 ... 0x03FF Reserved 0x0400 PWM_CMUPD0 0x0404 ... 0x041F Reserved 0x0420 PWM_CMUPD1 0x0424 ... 0x042B Reserved 0x042C PWM_ETRG1 0x0430 PWM_LEBR1 0x0434 ... 0x043F Reserved 0x0440 PWM_CMUPD2 0x0444 ... 0x044B Reserved 0x044C PWM_ETRG2 Bit Pos.
PAGE 1597
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) ...........continued Offset Name Bit Pos. 0x0450 PWM_LEBR2 7:0 15:8 23:16 31:24 0x0454 ... 0x045F Reserved 0x0460 PWM_CMUPD3 7:0 15:8 23:16 31:24 © 2019 Microchip Technology Inc.
PAGE 1598
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) 51.7.1 PWM Clock Register Name: Offset: Reset: Property: PWM_CLK 0x00 0x00000000 Read/Write This register can only be written if bits WPSWS0 and WPHWS0 are cleared in the PWM Write Protection Status Register.
PAGE 1599
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) Value 3 4 5 6 7 8 9 10 Other Name CLK_DIV8 CLK_DIV16 CLK_DIV32 CLK_DIV64 CLK_DIV128 CLK_DIV256 CLK_DIV512 CLK_DIV1024 – Description Peripheral clock/8 Peripheral clock/16 Peripheral clock/32 Peripheral clock/64 Peripheral clock/128 Peripheral clock/256 Peripheral clock/512 Peripheral clock/1024 Reserved Bits 7:0 – DIVA[7:0] CLKA Divide Factor Value Name Description 0 CLKA_POFF CLKA clock is turned off 1 PREA CLKA clock is clock selected b
PAGE 1600
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) 51.7.2 PWM Enable Register Name: Offset: Reset: Property: Bit PWM_ENA 0x04 – Write-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 CHID3 W 0 2 CHID2 W 0 1 CHID1 W 0 0 CHID0 W – Access Reset Bit Access Reset Bit Access Reset Bit Access Reset Bits 0, 1, 2, 3 – CHIDx Channel ID Value Description 0 No effect. 1 Enable PWM output for channel x.
PAGE 1601
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) 51.7.3 PWM Disable Register Name: Offset: Reset: Property: PWM_DIS 0x08 – Write-only This register can only be written if bits WPSWS1 and WPHWS1 are cleared in the PWM Write Protection Status Register.
PAGE 1602
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) 51.7.4 PWM Status Register Name: Offset: Reset: Property: Bit PWM_SR 0x0C 0x00000000 Read-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 CHID3 R 0 2 CHID2 R 0 1 CHID1 R 0 0 CHID0 R 0 Access Reset Bit Access Reset Bit Access Reset Bit Access Reset Bits 0, 1, 2, 3 – CHIDx Channel ID Value Description 0 PWM output for channel x is disabled.
PAGE 1603
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) 51.7.5 PWM Interrupt Enable Register 1 Name: Offset: Reset: Property: PWM_IER1 0x10 – Write-only This register can only be written if bits WPSWS1 and WPHWS1 are cleared in the PWM Write Protection Status Register.
PAGE 1604
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) 51.7.6 PWM Interrupt Disable Register 1 Name: Offset: Reset: Property: PWM_IDR1 0x14 – Write-only This register can only be written if bits WPSWS1 and WPHWS1 are cleared in the PWM Write Protection Status Register.
PAGE 1605
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) 51.7.
PAGE 1606
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) 51.7.8 PWM Interrupt Status Register 1 Name: Offset: Reset: Property: PWM_ISR1 0x1C 0x00000000 Read-only Note: Reading PWM_ISR1 automatically clears CHIDx and FCHIDx flags.
PAGE 1607
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) 51.7.9 PWM Sync Channels Mode Register Name: Offset: Reset: Property: PWM_SCM 0x20 0x00000000 Read/Write This register can only be written if bits WPSWS2 and WPHWS2 are cleared in the PWM Write Protection Status Register.
PAGE 1608
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) Note: 1. The update occurs at the beginning of the next PWM period, when the UPDULOCK bit in PWM Sync Channels Update Control Register is set. 2. The update occurs when the Update Period is elapsed. Bits 0, 1, 2, 3 – SYNCx Synchronous Channel x Value Description 0 Channel x is not a synchronous channel. 1 Channel x is a synchronous channel. © 2019 Microchip Technology Inc.
PAGE 1609
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) 51.7.10 PWM DMA Register Name: Offset: Reset: Property: PWM_DMAR 0x24 – Write-only Only the first 16 bits (channel counter size) are significant.
PAGE 1610
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) 51.7.11 PWM Sync Channels Update Control Register Name: Offset: Reset: Property: Bit PWM_SCUC 0x28 0x00000000 Read/Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UPDULOCK R/W 0 Access Reset Bit Access Reset Bit Access Reset Bit Access Reset Bit 0 – UPDULOCK Synchronous Channels Update Unlock This bit is automatically reset when the update is done.
PAGE 1611
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) 51.7.
PAGE 1612
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) 51.7.13 PWM Sync Channels Update Period Update Register Name: Offset: Reset: Property: PWM_SCUPUPD 0x30 – Write-only This register acts as a double buffer for the UPR value. This prevents an unexpected automatic trigger of the update of synchronous channels.
PAGE 1613
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) 51.7.14 PWM Interrupt Enable Register 2 Name: Offset: Reset: Property: PWM_IER2 0x34 – Write-only This register can only be written if bits WPSWS1 and WPHWS1 are cleared in the PWM Write Protection Status Register.
PAGE 1614
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) 51.7.15 PWM Interrupt Disable Register 2 Name: Offset: Reset: Property: PWM_IDR2 0x38 – Write-only This register can only be written if bits WPSWS1 and WPHWS1 are cleared in the PWM Write Protection Status Register.
PAGE 1615
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) 51.7.
PAGE 1616
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) 51.7.17 PWM Interrupt Status Register 2 Name: Offset: Reset: Property: PWM_ISR2 0x40 0x00000000 Read-only Reading PWM_ISR2 automatically clears flags WRDY, UNRE and CMPSx.
PAGE 1617
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) 51.7.
PAGE 1618
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) 51.7.
PAGE 1619
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) 51.7.
PAGE 1620
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) 51.7.
PAGE 1621
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) 51.7.
PAGE 1622
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) 51.7.
PAGE 1623
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) 51.7.24 PWM Fault Mode Register Name: Offset: Reset: Property: PWM_FMR 0x5C 0x00000000 Read/Write This register can only be written if bits WPSWS5 and WPHWS5 are cleared in the PWM Write Protection Status Register. See Fault Inputs for details on fault generation.
PAGE 1624
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) 51.7.25 PWM Fault Status Register Name: Offset: Reset: Property: PWM_FSR 0x60 0x00000000 Read-only Refer to Fault Inputs for details on fault generation.
PAGE 1625
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) 51.7.26 PWM Fault Clear Register Name: Offset: Reset: Property: PWM_FCR 0x64 – Write-only See Fault Inputs for details on fault generation.
PAGE 1626
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) 51.7.27 PWM Fault Protection Value Register 1 Name: Offset: Reset: Property: PWM_FPV1 0x68 0x00000000 Read/Write This register can only be written if bits WPSWS5 and WPHWS5 are cleared in the PWM Write Protection Status Register. See Fault Inputs for details on fault generation.
PAGE 1627
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) 51.7.28 PWM Fault Protection Enable Register Name: Offset: Reset: Property: PWM_FPE 0x6C 0x00000000 Read/Write This register can only be written if bits WPSWS5 and WPHWS5 are cleared in the PWM Write Protection Status Register. Only the first 8 bits (number of fault input pins) of the register fields are significant. Refer to Section 6.4 “Fault Inputs” for details on fault generation.
PAGE 1628
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) 51.7.29 PWM Event Line x Mode Register Name: Offset: Reset: Property: Bit PWM_ELMRx 0x7C + x*0x04 [x=0..
PAGE 1629
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) 51.7.30 PWM Spread Spectrum Register Name: Offset: Reset: Property: PWM_SSPR 0xA0 0x00000000 Read/Write This register can only be written if bits WPSWS3 and WPHWS3 are cleared in the PWM Write Protection Status Register. Only the first 16 bits (channel counter size) are significant.
PAGE 1630
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) 51.7.31 PWM Spread Spectrum Update Register Name: Offset: Reset: Property: PWM_SSPUP 0xA4 – Write-only This register can only be written if bits WPSWS3 and WPHWS3 are cleared in the PWM Write Protection Status Register. This register acts as a double buffer for the SPRD value. This prevents an unexpected waveform when modifying the spread spectrum limit value. Only the first 16 bits (channel counter size) are significant.
PAGE 1631
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) 51.7.32 PWM Stepper Motor Mode Register Name: Offset: Reset: Property: Bit PWM_SMMR 0xB0 0x00000000 Read/Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 DOWN1 16 DOWN0 0 0 Access Reset Bit Access Reset Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 GCEN1 R/W 0 0 GCEN0 R/W 0 Access Reset Bit Access Reset Bits 16, 17 – DOWNx Down Count Value Description 0 Up counter. 1 Down counter.
PAGE 1632
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) 51.7.33 PWM Fault Protection Value Register 2 Name: Offset: Reset: Property: PWM_FPV2 0xC0 0x000F000F Read/Write This register can only be written if bits WPSWS5 and WPHWS5 are cleared in the PWM Write Protection Status Register.
PAGE 1633
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) 51.7.34 PWM Write Protection Control Register Name: Offset: Reset: Property: PWM_WPCR 0xE4 – Write-only See Register Write Protection for the list of registers that can be write-protected.
PAGE 1634
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) 51.7.
PAGE 1635
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) 51.7.36 PWM Comparison x Value Register Name: Offset: Reset: Property: PWM_CMPVx 0x0130 + x*0x10 [x=0..7] 0x00000000 Read/Write Only the first 16 bits (channel counter size) of field CV are significant.
PAGE 1636
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) 51.7.37 PWM Comparison x Value Update Register Name: Offset: Reset: Property: PWM_CMPVUPDx 0x0134 + x*0x10 [x=0..7] – Write-only This register acts as a double buffer for the CV and CVM values. This prevents an unexpected comparison x match. Only the first 16 bits (channel counter size) of field CVUPD are significant. CAUTION Bit The write of the register PWM_CMPVUPDx must be followed by a write of the register PWM_CMPMUPDx.
PAGE 1637
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) 51.7.38 PWM Comparison x Mode Register Name: Offset: Reset: Property: Bit 31 PWM_CMPMx 0x0138 + x*0x10 [x=0..
PAGE 1638
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) 51.7.39 PWM Comparison x Mode Update Register Name: Offset: Reset: Property: PWM_CMPMUPDx 0x013C + x*0x10 [x=0..7] – W This register acts as a double buffer for the CEN, CTR, CPR and CUPR values. This prevents an unexpected comparison x match.
PAGE 1639
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) 51.7.40 PWM Channel Mode Register Name: Offset: Reset: Property: PWM_CMRx 0x0200 + x*0x20 [x=0..3] 0x00000000 Read/Write This register can only be written if bits WPSWS2 and WPHWS2 are cleared in the PWM Write Protection Status Register.
PAGE 1640
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) Bit 12 – DPOLI Disabled Polarity Inverted Value Description 0 When the PWM channel x is disabled (CHIDx(PWM_SR) = 0), the OCx output waveform is the same as the one defined by the CPOL bit. 1 When the PWM channel x is disabled (CHIDx(PWM_SR) = 0), the OCx output waveform is inverted compared to the one defined by the CPOL bit.
PAGE 1641
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) 51.7.41 PWM Channel Duty Cycle Register Name: Offset: Reset: Property: PWM_CDTYx 0x0204 + x*0x20 [x=0..3] 0x00000000 Read/Write Only the first 16 bits (channel counter size) are significant.
PAGE 1642
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) 51.7.42 PWM Channel Duty Cycle Update Register Name: Offset: Reset: Property: PWM_CDTYUPDx 0x0208 + x*0x20 [x=0..3] – Write-only This register acts as a double buffer for the CDTY value. This prevents an unexpected waveform when modifying the waveform duty-cycle. Only the first 16 bits (channel counter size) are significant.
PAGE 1643
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) 51.7.43 PWM Channel Period Register Name: Offset: Reset: Property: PWM_CPRDx 0x020C + x*0x20 [x=0..3] 0x00000000 Read/Write This register can only be written if bits WPSWS3 and WPHWS3 are cleared in the PWM Write Protection Status Register. Only the first 16 bits (channel counter size) are significant.
PAGE 1644
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) 51.7.44 PWM Channel Period Update Register Name: Offset: Reset: Property: PWM_CPRDUPDx 0x0210 + x*0x20 [x=0..3] – Write-only This register can only be written if bits WPSWS3 and WPHWS3 are cleared in the PWM Write Protection Status Register. This register acts as a double buffer for the CPRD value. This prevents an unexpected waveform when modifying the waveform period. Only the first 16 bits (channel counter size) are significant.
PAGE 1645
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) 2 × � × CPRDUPD × DIVA 2 × � × CPRDUPD × DIVB or �peripheral clock �peripheral clock © 2019 Microchip Technology Inc.
PAGE 1646
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) 51.7.45 PWM Channel Counter Register Name: Offset: Reset: Property: PWM_CCNTx 0x0214 + x*0x20 [x=0..3] 0x00000000 Read-only Only the first 16 bits (channel counter size) are significant.
PAGE 1647
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) 51.7.46 PWM Channel Dead Time Register Name: Offset: Reset: Property: PWM_DTx 0x0218 + x*0x20 [x=0..3] 0x00000000 Read/Write This register can only be written if bits WPSWS4 and WPHWS4 are cleared in the PWM Write Protection Status Register. Only the first 12 bits (dead-time counter size) of fields DTH and DTL are significant.
PAGE 1648
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) 51.7.47 PWM Channel Dead Time Update Register Name: Offset: Reset: Property: PWM_DTUPDx 0x021C + x*0x20 [x=0..3] 0x00000000 Write-only This register can only be written if bits WPSWS4 and WPHWS4 are cleared in the PWM Write Protection Status Register. This register acts as a double buffer for the DTH and DTL values. This prevents an unexpected waveform when modifying the dead-time values.
PAGE 1649
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) 51.7.48 PWM Channel Mode Update Register Name: Offset: Reset: Property: PWM_CMUPDx 0x0400 + x*0x20 [x=0..3] – Write-only This register can only be written if bits WPSWS2 and WPHWS2 are cleared in the PWM Write Protection Status Register. This register acts as a double buffer for the CPOL value. This prevents an unexpected waveform when modifying the polarity value.
PAGE 1650
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) 51.7.49 PWM External Trigger Register Name: Offset: Reset: Property: Bit Access Reset Bit Access Reset Bit Access Reset Bit Access Reset PWM_ETRGx 0x042C + (x-1)*0x20 [x=1..
PAGE 1651
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) Bits 23:0 – MAXCNT[23:0] Maximum Counter value Maximum channel x counter value measured at the TRGINx event since the last read of the register. At the TRGINx event, if the channel x counter value is greater than the stored MAXCNT value, then MAXCNT is updated by the channel x counter value. © 2019 Microchip Technology Inc.
PAGE 1652
SAM E70/S70/V70/V71 Family Pulse Width Modulation Controller (PWM) 51.7.50 PWM Leading-Edge Blanking Register Name: Offset: Reset: Property: Bit PWM_LEBRx 0x0430 + (x-1)*0x20 [x=1..
PAGE 1653
SAM E70/S70/V70/V71 Family Analog Front-End Controller (AFEC) 52. 52.
PAGE 1654
SAM E70/S70/V70/V71 Family Analog Front-End Controller (AFEC) • • • 52.3 Standby Mode for Fast Wakeup Time Response – Powerdown capability Automatic Window Comparison of Converted Values Register Write Protection Block Diagram Figure 52-1. Analog Front-End Controller Block Diagram Timer Counter Channels AFE Controller (AFEC) Trigger Selection AFE_ADTRG Channel Sequencer AFE Analog Cell VDDANA 10-bit DA Converter VREFP VREFN Analog Mux n/2->1 AFE_AD0 + PIO Extra Funct.
PAGE 1655
SAM E70/S70/V70/V71 Family Analog Front-End Controller (AFEC) 52.5 52.5.1 Product Dependencies I/O Lines The digital input AFE_ADTRG is multiplexed with digital functions on the I/O line and the selection of AFE_ADTRG is made using the PIO Controller. The analog inputs AFE_ADx are multiplexed with digital functions on the I/O lines. AFE_ADx inputs are selected as inputs of the AFEC when writing a one in the corresponding CHx bit of AFEC_CHER and the digital functions are not selected. 52.5.
PAGE 1656
SAM E70/S70/V70/V71 Family Analog Front-End Controller (AFEC) • • The tracking time represents the time between the channel selection change and the time for the controller to start the AFEC. The AFEC allows a minimum tracking time of 15 AFE clock periods. The conversion time represents the time for the AFEC to convert the analog signal. The AFE clock frequency is selected in the PRESCAL field of the AFEC_MR. The tracking phase starts during the conversion of the previous channel.
PAGE 1657
SAM E70/S70/V70/V71 Family Analog Front-End Controller (AFEC) AFE Clock Trigger event (Hard or Soft) AFEC_ON Commands from controller to analog cell AFEC_Start CH0 AFEC_SEL CH1 CH2 LCDR CH0 CH1 DRDY Start Up Transfer Period Time (and tracking of CH0) Conversion of CH0 Transfer Period Conversion of CH1 Tracking of CH1 Tracking of CH2 Figure 52-3.
PAGE 1658
SAM E70/S70/V70/V71 Family Analog Front-End Controller (AFEC) Note: If ADTRG is asynchronous to the AFEC peripheral clock, the internal resynchronization introduces a jitter of 1 peripheral clock. This jitter may reduce the resolution of the converted signal. Refer to the formula below, where fIN is the frequency of the analog signal to convert and tJ is the half-period of 1 peripheral clock. 52.6.
PAGE 1659
SAM E70/S70/V70/V71 Family Analog Front-End Controller (AFEC) Figure 52-5. EOCx, GOVRE and OVREx Flag Behavior Trigger event CH0 (AFEC_CHSR) CH1 (AFEC_CHSR) AFEC_LCDR Undefined Data AFEC_CDR0 Undefined Data AFEC_CDR1 EOC0 (AFEC_ISR1) Data B Data A Data A Undefined Data Data C Data B Conversion A EOC1 (AFEC_ISR1) Data C Conversion C Conversion B GOVRE (AFEC_ISR1) Read AFEC_CDR0 Read AFEC_CDR1 Read AFEC_SR DRDY (AFEC_ISR1) Read AFEC_OVER OVRE0 (AFEC_OVER) OVRE1 (AFEC_OVER) WARNING 52.6.
PAGE 1660
SAM E70/S70/V70/V71 Family Analog Front-End Controller (AFEC) 52.6.6 Conversion Triggers Conversions of the active analog channels are started with a software or hardware trigger. The software trigger is provided by writing a ‘1’ to the bit START in the Control Register (AFEC_CR). The hardware trigger can be one of the TIOA outputs of the Timer Counter channels, PWM Event line, or the external trigger input of the AFEC (ADTRG). The hardware trigger is selected with AFEC_MR.TRGSEL.
PAGE 1661
SAM E70/S70/V70/V71 Family Analog Front-End Controller (AFEC) Note: The reference voltage pins always remain connected in Normal mode as in Sleep mode. Related Links 58. Electrical Characteristics for SAM V70/V71 52.6.8 Comparison Window The AFEC features automatic comparison functions. It compares converted values to a low threshold, a high threshold or both, depending on the value of AFEC_EMR.CMPMODE. The comparison can be done on all channels or only on the channel specified in AFEC_EMR.CMPSEL.
PAGE 1662
SAM E70/S70/V70/V71 Family Analog Front-End Controller (AFEC) ...........continued Single-Ended Input Pins Differential Input Pins Channel Numbers AFE_AD1 & AFE_AD7 – CH1 ... ... ... AFE_AD4 & AFE_AD10 AFE_AD4–AFE_AD5 & AFE_AD10–AFE_AD11 CH4 AFE_AD5 & AFE_AD11 – CH5 Table 52-4. Input Pins and Channel Numbers in Single Sample-and-Hold Mode Single-Ended Input Pins Differential Input Pins Channel Numbers AFE_AD0 AFE_AD0-AFE_AD1 CH0 AFE_AD1 – CH1 ... ... ...
PAGE 1663
SAM E70/S70/V70/V71 Family Analog Front-End Controller (AFEC) Figure 52-7. Analog Full Scale Ranges in Single-Ended/Differential Applications Versus Gain Single-ended Fully differential VVREFP VIN+ VIN+ gain=1 (½)VVREFP (00) VINVVREFN =0 VVREFP (¾)VVREFP gain=2 VIN+ (01) VIN+ (½)VVREFP VIN(¼)VVREFP VVREFN =0 VVREFP (¾)VVREFP gain=4 VIN+ (10 or 11) (5/8)VVREFP (½)VVREFP (3/8)VVREFP VIN+ VIN- (¼)VVREFP VVREFN =0 52.6.
PAGE 1664
SAM E70/S70/V70/V71 Family Analog Front-End Controller (AFEC) The channel of the temperature sensor is periodically converted together with the other enabled channels and the result is placed into AFEC_LCDR and an internal register (can be read in AFEC_CDR). Thus the temperature conversion result is part of the Peripheral DMA Controller buffer. The temperature channel can be enabled/disabled at any time, but this may not be optimal for downstream processing. Figure 52-8.
PAGE 1665
SAM E70/S70/V70/V71 Family Analog Front-End Controller (AFEC) Figure 52-9. Optimized Temperature Conversion Combined with Classical Conversions AFEC_CHSR[TEMP] = 0, AFEC_MR.TRGEN = 1 and AFEC_TEMPMR.
PAGE 1666
SAM E70/S70/V70/V71 Family Analog Front-End Controller (AFEC) 52.6.14 Enhanced Resolution Mode and Digital Averaging Function The Enhanced Resolution mode is enabled when AFEC_EMR.RES is set to 13-bit resolution or higher. In this mode, the AFEC trades conversion performance for accuracy by averaging multiple samples, thus providing a digital lowpass filter function. The resolution mode selected determines the oversampling, which represents the performance reduction factor.
PAGE 1667
SAM E70/S70/V70/V71 Family Analog Front-End Controller (AFEC) Figure 52-11. Digital Averaging Function Waveforms over Multiple Trigger Events AFEC_EMR.RES = 2, STM = 0, AFEC_CHSR[1:0] = 0x3 and AFEC_MR.USEQ = 0 Internal/External Trigger event 0 1 0 1 AFEC_SEL Internal register CDR[0] 0 1 0i2 0i1 CH0_0 0 1 0 1 0i3 CH0_1 0i1 Read AFEC_CDR & AFEC_CSELR.CSEL = 0 EOC[0] OVR[0] Internal register CDR[1] CH1_0 1i1 1i2 1i3 CH1_1 Read AFEC_CDR Read AFEC_CDR & AFEC_CSELR.
PAGE 1668
SAM E70/S70/V70/V71 Family Analog Front-End Controller (AFEC) When USEQ is set, the user can define the channel sequence to be converted by configuring AFEC_SEQxR and AFEC_CHER so that channels are not interleaved during the averaging period. Under these conditions, a sample is defined for each end of conversion as described in the figure below. Therefore, if the same channel is configured to be converted four times consecutively and AFEC_EMR.
PAGE 1669
SAM E70/S70/V70/V71 Family Analog Front-End Controller (AFEC) • Gs—the value 15 Corrected Data = Converted Data+OFFSETCORR × GAINCORR 2 Gs Figure 52-14. AFE Digital Signal Processing RES ADC_CVR GAINCORR OFFSETCORR Average Calibration ADC_EMR VINP VINN AFE 12-bit 2’s complement data format 12- to 16-bit 2’s complement data format Sign Mode 12- to 16-bit 2’s complement data format AFE_LCDR 12- to 16-bit signed or unsigned data 52.6.
PAGE 1670
SAM E70/S70/V70/V71 Family Analog Front-End Controller (AFEC) • • • • • • • • • • • • AFEC Compare Window Register AFEC Channel Gain 1 Register AFEC Channel Differential Register AFEC Channel Selection Register AFEC Channel Offset Compensation Register AFEC Temperature Sensor Mode Register AFEC Temperature Compare Window Register AFEC Analog Control Register AFEC Sample & Hold Mode Register AFEC Correction Select Register AFEC Correction Values Register AFEC Channel Error Correction Register © 2019 Microc
PAGE 1671
SAM E70/S70/V70/V71 Family Analog Front-End Controller (AFEC) 52.7 Register Summary Offset Name 0x00 AFEC_CR 0x04 0x08 AFEC_MR AFEC_EMR 0x0C AFEC_SEQ1R 0x10 AFEC_SEQ2R 0x14 AFEC_CHER 0x18 AFEC_CHDR 0x1C AFEC_CHSR 0x20 AFEC_LCDR 0x24 0x28 0x2C 0x30 0x34 ... 0x4B AFEC_IER AFEC_IDR AFEC_IMR AFEC_ISR Bit Pos.
PAGE 1672
SAM E70/S70/V70/V71 Family Analog Front-End Controller (AFEC) ...........continued Offset Name 0x4C AFEC_OVER 0x50 AFEC_CWR 0x54 AFEC_CGR 0x58 ... 0x5F Reserved 0x60 0x64 0x68 0x6C 0x70 AFEC_DIFFR AFEC_CSELR AFEC_CDR AFEC_COCR AFEC_TEMPMR 0x74 AFEC_TEMPCWR 0x78 ... 0x93 Reserved 0x94 AFEC_ACR 0x98 ... 0x9F Reserved 0xA0 AFEC_SHMR 0xA4 ... 0xCF Reserved Bit Pos.
PAGE 1673
SAM E70/S70/V70/V71 Family Analog Front-End Controller (AFEC) ...........continued Offset Name 0xD0 AFEC_COSR 0xD4 AFEC_CVR 0xD8 AFEC_CECR 0xDC ... 0xE3 Reserved 0xE4 0xE8 AFEC_WPMR AFEC_WPSR Bit Pos. 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 CSEL ECORR7 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 © 2019 Microchip Technology Inc.
PAGE 1674
SAM E70/S70/V70/V71 Family Analog Front-End Controller (AFEC) 52.7.1 AFEC Control Register Name: Offset: Reset: Property: Bit AFEC_CR 0x00 – Write-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 START W – 0 SWRST W – Access Reset Bit Access Reset Bit Access Reset Bit Access Reset Bit 1 – START Start Conversion Value Description 0 No effect. 1 Begins Analog Front-End conversion.
PAGE 1675
SAM E70/S70/V70/V71 Family Analog Front-End Controller (AFEC) 52.7.2 AFEC Mode Register Name: Offset: Reset: Property: AFEC_MR 0x04 0x00000000 Read/Write This register can only be written if the WPEN bit is cleared in the AFEC Write Protection Mode Register.
PAGE 1676
SAM E70/S70/V70/V71 Family Analog Front-End Controller (AFEC) Value 10 11 12 13 14 15 Name SUT640 SUT704 SUT768 SUT832 SUT896 SUT960 Description 640 periods of AFE clock 704 periods of AFE clock 768 periods of AFE clock 832 periods of AFE clock 896 periods of AFE clock 960 periods of AFE clock Bits 15:8 – PRESCAL[7:0] Prescaler Rate Selection PRESCAL = fperipheral clock/ fAFE Clock - 1 When PRESCAL is cleared, no conversion is performed.
PAGE 1677
SAM E70/S70/V70/V71 Family Analog Front-End Controller (AFEC) 52.7.3 AFEC Extended Mode Register Name: Offset: Reset: Property: AFEC_EMR 0x08 0x00000000 Read/Write This register can only be written if the WPEN bit is cleared in the AFEC Write Protection Mode Register.
PAGE 1678
SAM E70/S70/V70/V71 Family Analog Front-End Controller (AFEC) Value 3 4 5 Name OSR16 OSR64 OSR256 Description 14-bit resolution, AFE sample rate divided by 16 (averaging). 15-bit resolution, AFE sample rate divided by 64 (averaging). 16-bit resolution, AFE sample rate divided by 256 (averaging). Bits 13:12 – CMPFILTER[1:0] Compare Event Filtering Number of consecutive compare events necessary to raise the flag = CMPFILTER+1. When programmed to ‘0’, the flag rises as soon as an event occurs.
PAGE 1679
SAM E70/S70/V70/V71 Family Analog Front-End Controller (AFEC) 52.7.4 AFEC Channel Sequence 1 Register Name: Offset: Reset: Property: AFEC_SEQ1R 0x0C 0x00000000 Read/Write This register can only be written if the WPEN bit is cleared in the AFEC Write Protection Mode Register.
PAGE 1680
SAM E70/S70/V70/V71 Family Analog Front-End Controller (AFEC) 52.7.5 AFEC Channel Sequence 2 Register Name: Offset: Reset: Property: AFEC_SEQ2R 0x10 0x00000000 Read/Write This register can only be written if the WPEN bit is cleared in the AFEC Write Protection Mode Register.
PAGE 1681
SAM E70/S70/V70/V71 Family Analog Front-End Controller (AFEC) 52.7.6 AFEC Channel Enable Register Name: Offset: Reset: Property: AFEC_CHER 0x14 – Write-only This register can only be written if the WPEN bit is cleared in the AFEC Write Protection Mode Register.
PAGE 1682
SAM E70/S70/V70/V71 Family Analog Front-End Controller (AFEC) 52.7.7 AFEC Channel Disable Register Name: Offset: Reset: Property: AFEC_CHDR 0x18 – Write-only This register can only be written if the WPEN bit is cleared in the AFEC Write Protection Mode Register.
PAGE 1683
SAM E70/S70/V70/V71 Family Analog Front-End Controller (AFEC) 52.7.
PAGE 1684
SAM E70/S70/V70/V71 Family Analog Front-End Controller (AFEC) 52.7.
PAGE 1685
SAM E70/S70/V70/V71 Family Analog Front-End Controller (AFEC) 52.7.10 AFEC Interrupt Enable 1 Register Name: Offset: Reset: Property: AFEC_IER 0x24 – Write-only The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Enables the corresponding interrupt.
PAGE 1686
SAM E70/S70/V70/V71 Family Analog Front-End Controller (AFEC) 52.7.11 AFEC Interrupt Disable Register Name: Offset: Reset: Property: AFEC_IDR 0x28 – Write-only The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Disables the corresponding interrupt.
PAGE 1687
SAM E70/S70/V70/V71 Family Analog Front-End Controller (AFEC) 52.7.12 AFEC Interrupt Mask Register Name: Offset: Reset: Property: AFEC_IMR 0x2C 0x00000000 Read-only The following configuration values are valid for all listed bit names of this register: 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
PAGE 1688
SAM E70/S70/V70/V71 Family Analog Front-End Controller (AFEC) 52.7.
PAGE 1689
SAM E70/S70/V70/V71 Family Analog Front-End Controller (AFEC) 52.7.
PAGE 1690
SAM E70/S70/V70/V71 Family Analog Front-End Controller (AFEC) 52.7.15 AFEC Compare Window Register Name: Offset: Reset: Property: AFEC_CWR 0x50 0x00000000 Read/Write This register can only be written if the WPEN bit is cleared in the AFEC Write Protection Mode Register.
PAGE 1691
SAM E70/S70/V70/V71 Family Analog Front-End Controller (AFEC) 52.7.16 AFEC Channel Gain Register Name: Offset: Reset: Property: AFEC_CGR 0x54 0x00000000 Read/Write This register can only be written if the WPEN bit is cleared in the AFEC Write Protection Mode Register.
PAGE 1692
SAM E70/S70/V70/V71 Family Analog Front-End Controller (AFEC) 52.7.17 AFEC Channel Differential Register Name: Offset: Reset: Property: AFEC_DIFFR 0x60 0x00000000 Read/Write This register can only be written if the WPEN bit is cleared in the AFEC Write Protection Mode Register.
PAGE 1693
SAM E70/S70/V70/V71 Family Analog Front-End Controller (AFEC) 52.7.
PAGE 1694
SAM E70/S70/V70/V71 Family Analog Front-End Controller (AFEC) 52.7.
PAGE 1695
SAM E70/S70/V70/V71 Family Analog Front-End Controller (AFEC) 52.7.20 AFEC Channel Offset Compensation Register Name: Offset: Reset: Property: AFEC_COCR 0x6C 0x00000000 Read/Write This register can only be written if the WPEN bit is cleared in the AFEC Write Protection Mode Register.
PAGE 1696
SAM E70/S70/V70/V71 Family Analog Front-End Controller (AFEC) 52.7.21 AFEC Temperature Sensor Mode Register Name: Offset: Reset: Property: AFEC_TEMPMR 0x70 0x00000000 Read/Write This register can only be written if the WPEN bit is cleared in the AFEC Write Protection Mode Register.
PAGE 1697
SAM E70/S70/V70/V71 Family Analog Front-End Controller (AFEC) 52.7.22 AFEC Temperature Compare Window Register Name: Offset: Reset: Property: AFEC_TEMPCWR 0x74 0x00000000 Read/Write This register can only be written if the WPEN bit is cleared in the AFEC Write Protection Mode Register.
PAGE 1698
SAM E70/S70/V70/V71 Family Analog Front-End Controller (AFEC) 52.7.23 AFEC Analog Control Register Name: Offset: Reset: Property: AFEC_ACR 0x94 0x00000100 Read/Write This register can only be written if the WPEN bit is cleared in the AFEC Write Protection Mode Register.
PAGE 1699
SAM E70/S70/V70/V71 Family Analog Front-End Controller (AFEC) 52.7.24 AFEC Sample & Hold Mode Register Name: Offset: Reset: Property: AFEC_SHMR 0xA0 0x00000000 Read/Write This register can only be written if the WPEN bit is cleared in the AFEC Write Protection Mode Register.
PAGE 1700
SAM E70/S70/V70/V71 Family Analog Front-End Controller (AFEC) 52.7.25 AFEC Correction Select Register Name: Offset: Reset: Property: AFEC_COSR 0xD0 0x00000000 Read/Write This register can only be written if the WPEN bit is cleared in the AFEC Write Protection Mode Register.
PAGE 1701
SAM E70/S70/V70/V71 Family Analog Front-End Controller (AFEC) 52.7.26 AFEC Correction Values Register Name: Offset: Reset: Property: AFEC_CVR 0xD4 0x00000000 Read/Write This register can only be written if the WPEN bit is cleared in the AFEC Write Protection Mode Register.
PAGE 1702
SAM E70/S70/V70/V71 Family Analog Front-End Controller (AFEC) 52.7.27 AFEC Channel Error Correction Register Name: Offset: Reset: Property: AFEC_CECR 0xD8 0x00000000 Read/Write This register can only be written if the WPEN bit is cleared in the AFEC Write Protection Mode Register.
PAGE 1703
SAM E70/S70/V70/V71 Family Analog Front-End Controller (AFEC) 52.7.
PAGE 1704
SAM E70/S70/V70/V71 Family Analog Front-End Controller (AFEC) 52.7.
PAGE 1705
SAM E70/S70/V70/V71 Family Digital-to-Analog Converter Controller (DACC) 53. 53.1 Digital-to-Analog Converter Controller (DACC) Description The Digital-to-Analog Converter Controller (DACC) offers up to two single-ended analog outputs or one differential analog output, making it possible for the digital-to-analog conversion to drive up to two independent analog lines. The DACC supports 12-bit resolution. The DACC operates in Free-running mode, Max speed mode, Trigger mode or Interpolation mode.
PAGE 1706
SAM E70/S70/V70/V71 Family Digital-to-Analog Converter Controller (DACC) 53.3 Block Diagram Figure 53-1. Block Diagram Event System Digital-to-Analog Converter Controller (DACC) Trigger Selection DAC Clock Control Logic Trigger Selection DATRG Interrupt Controller Analog Cell (DAC) VDDANA DMA VREFP DAC Core 0 DAC Core 1 Peripheral Bridge User Interface peripheral clock DAC0/DACP 53.4 PMC DAC1/DACN Signal Description Table 53-1.
PAGE 1707
SAM E70/S70/V70/V71 Family Digital-to-Analog Converter Controller (DACC) 53.5 53.5.1 Product Dependencies I/O Lines The digital input DATRG is multiplexed with digital functions on the I/O line and is selected using the PIO Controller. The analog outputs DAC0/DACP, DAC1/DACN are multiplexed with digital functions on the I/O lines .
PAGE 1708
SAM E70/S70/V70/V71 Family Digital-to-Analog Converter Controller (DACC) When set to Single-ended mode (DIFF = 0), each DAC channel can be configured independently. When set to Differential mode (DIFF = 1), the analog outputs DACP and DACN are located on DAC0 and DAC1 outputs, respectively. All operations are driven by channel 0 and activating this channel automatically activates channel 1. Sending a value on channel 0 (DACP) automatically generates the complementary signal to be sent to channel 1 (DACN).
PAGE 1709
SAM E70/S70/V70/V71 Family Digital-to-Analog Converter Controller (DACC) Figure 53-3. Conversion Sequence in Free-running Mode TXRDY Write DACC_CDR0 FIFO 0 is empty d0 d1 d2 d3 d4 Waiting for next write DACC_CDR0 operation FIFO 0 is ready FIFO 0 is full SOC0 DAC conversion period EOC0 DAC Channel 0 Output d0 d4 d1 Read DACC_ISR interrupt 53.6.4.3 Max Speed Mode Max speed mode is enabled by setting DACC_TRIGR.TRGENx and DACC_MR.MAXSx.
PAGE 1710
SAM E70/S70/V70/V71 Family Digital-to-Analog Converter Controller (DACC) 53.6.4.5 Interpolation Mode The DACC integrates interpolation filters that allow OSR of 2×, 4×, 8×, 16× or 32×. This mode can be used only if Trigger mode is enabled and value in the field OSRx is not ‘0’. The OSR of the interpolator is configured in the OSRx field in the DACC Trigger Register (DACC_TRIGR). The data is sampled once every OSR trigger event and then recomputed at the trigger sample rate using a thirdorder SINC filter.
PAGE 1711
SAM E70/S70/V70/V71 Family Digital-to-Analog Converter Controller (DACC) Figure 53-7. Interpolator Spectral Mask for OSR = 8 0 -24 -2.4 Gain (dB), 0–fs/2 mask Gain (dB), overall mask 3rd order SINC filter overall mask for OSR = 8 0 -48 -72 -96 -120 3rd order SINC filter 0–fs/2 mask for OSR = 8 -4.8 -7.2 -9.6 0 0.5*fs 1*fs 1.5*fs 2*fs 2.5*fs Frequency (Hz), overall mask 3*fs 3.
PAGE 1712
SAM E70/S70/V70/V71 Family Digital-to-Analog Converter Controller (DACC) When the FIFO is full or the DACC is not ready to accept conversion requests, the TXRDY flag is inactive. The DACC also offers the possibility of writing two data words in one access by setting the bit WORD in the DACC_MR. In this case, bits 11:0 contain the first data to be converted and bits 27:16 contain the second data to be converted. The two data are written into the FIFO of the selected channel.
PAGE 1713
SAM E70/S70/V70/V71 Family Digital-to-Analog Converter Controller (DACC) 53.7 Register Summary Offset Name 0x00 DACC_CR 0x04 DACC_MR 0x08 DACC_TRIGR 0x0C ... 0x0F Reserved 0x10 0x14 0x18 DACC_CHER DACC_CHDR DACC_CHSR 0x1C DACC_CDR0 0x20 DACC_CDR1 0x24 0x28 0x2C DACC_IER DACC_IDR DACC_IMR 0x30 DACC_ISR 0x34 ... 0x93 Reserved Bit Pos.
PAGE 1714
SAM E70/S70/V70/V71 Family Digital-to-Analog Converter Controller (DACC) ...........continued Offset Name Bit Pos. 0x94 DACC_ACR 7:0 15:8 23:16 31:24 0x98 ... 0xE3 Reserved 0xE4 0xE8 DACC_WPMR DACC_WPSR 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 © 2019 Microchip Technology Inc.
PAGE 1715
SAM E70/S70/V70/V71 Family Digital-to-Analog Converter Controller (DACC) 53.7.1 DACC Control Register Name: Offset: Reset: Property: Bit DACC_CR 0x00 – Write-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SWRST W – Access Reset Bit Access Reset Bit Access Reset Bit Access Reset Bit 0 – SWRST Software Reset Value Description 0 No effect. 1 Resets the DACC simulating a hardware reset. © 2019 Microchip Technology Inc.
PAGE 1716
SAM E70/S70/V70/V71 Family Digital-to-Analog Converter Controller (DACC) 53.7.2 DACC Mode Register Name: Offset: Reset: Property: DACC_MR 0x04 0x00000000 Read/Write This register can only be written if the WPEN bit is cleared in the DACC Write Protection Mode Register.
PAGE 1717
SAM E70/S70/V70/V71 Family Digital-to-Analog Converter Controller (DACC) 53.7.3 DACC Trigger Register Name: Offset: Reset: Property: DACC_TRIGR 0x08 0x00000000 Read/Write This register can only be written if the WPEN bit is cleared in the DACC Write Protection Mode Register.
PAGE 1718
SAM E70/S70/V70/V71 Family Digital-to-Analog Converter Controller (DACC) 53.7.4 DACC Channel Enable Register Name: Offset: Reset: Property: DACC_CHER 0x10 – Write-only This register can only be written if the WPEN bit is cleared in the DACC Write Protection Mode Register.
PAGE 1719
SAM E70/S70/V70/V71 Family Digital-to-Analog Converter Controller (DACC) 53.7.5 DACC Channel Disable Register Name: Offset: Reset: Property: DACC_CHDR 0x14 – Write-only This register can only be written if the WPEN bit is cleared in the DACC Write Protection Mode Register.
PAGE 1720
SAM E70/S70/V70/V71 Family Digital-to-Analog Converter Controller (DACC) 53.7.6 DACC Channel Status Register Name: Offset: Reset: Property: Bit DACC_CHSR 0x18 0x00000000 Read-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 DACRDY1 R 0 8 DACRDY0 R 0 7 6 5 4 3 2 1 CH1 R 0 0 CH0 R 0 Access Reset Bit Access Reset Bit Access Reset Bit Access Reset Bits 8, 9 – DACRDYx DAC Ready Flag Value Description 0 The DACx is not yet ready to receive data.
PAGE 1721
SAM E70/S70/V70/V71 Family Digital-to-Analog Converter Controller (DACC) 53.7.7 DACC Conversion Data Register Name: Offset: Reset: Property: Bit 31 DACC_CDRx 0x1C + x*0x04 [x=0..
PAGE 1722
SAM E70/S70/V70/V71 Family Digital-to-Analog Converter Controller (DACC) 53.7.8 DACC Interrupt Enable Register Name: Offset: Reset: Property: DACC_IER 0x24 – Write-only The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Enables the corresponding interrupt.
PAGE 1723
SAM E70/S70/V70/V71 Family Digital-to-Analog Converter Controller (DACC) 53.7.9 DACC Interrupt Disable Register Name: Offset: Reset: Property: DACC_IDR 0x28 – Write-only The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Disables the corresponding interrupt.
PAGE 1724
SAM E70/S70/V70/V71 Family Digital-to-Analog Converter Controller (DACC) 53.7.10 DACC Interrupt Mask Register Name: Offset: Reset: Property: DACC_IMR 0x2C 0x00000000 Read-only The following configuration values are valid for all listed bit names of this register: 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
PAGE 1725
SAM E70/S70/V70/V71 Family Digital-to-Analog Converter Controller (DACC) 53.7.
PAGE 1726
SAM E70/S70/V70/V71 Family Digital-to-Analog Converter Controller (DACC) 53.7.12 DACC Analog Current Register Name: Offset: Reset: Property: DACC_ACR 0x94 0x00000000 Read/Write This register can only be written if the WPEN bit is cleared in the DACC Write Protection Mode Register.
PAGE 1727
SAM E70/S70/V70/V71 Family Digital-to-Analog Converter Controller (DACC) 53.7.
PAGE 1728
SAM E70/S70/V70/V71 Family Digital-to-Analog Converter Controller (DACC) 53.7.
PAGE 1729
SAM E70/S70/V70/V71 Family Analog Comparator Controller (ACC) 54. Analog Comparator Controller (ACC) 54.1 Description The Analog Comparator Controller (ACC) configures the analog comparator and generates an interrupt depending on user settings. The analog comparator embeds two 8-to-1 multiplexers that generate two internal inputs. These inputs are compared, resulting in a compare output. The hysteresis level, edge detection and polarity are configurable.
PAGE 1730
SAM E70/S70/V70/V71 Family Analog Comparator Controller (ACC) 54.4 Signal Description Table 54-1. ACC Signal Description Pin Name Description Type AFE0_AD[5:0] External analog data inputs Input TS On-chip temperature sensor Input VREFP AFE and DAC voltage reference Input DAC0, DAC1 On-chip DAC outputs Input AFE1_AD[1:0] 54.5 54.5.1 Product Dependencies I/O Lines The analog input pins are multiplexed with digital functions (PIO) on the IO line.
PAGE 1731
SAM E70/S70/V70/V71 Family Analog Comparator Controller (ACC) 54.6.3 Output Masking Period As soon as the analog comparator settings change, the output is invalid for a duration depending on ISEL current. A masking period is automatically triggered as soon as a write access is performed on the ACC_MR or ACC Analog Control Register (ACC_ACR) (regardless of the register data content). When ISEL = 0, the mask period is 8 × tperipheral clock. When ISEL = 1, the mask period is 128 × tperipheral clock.
PAGE 1732
SAM E70/S70/V70/V71 Family Analog Comparator Controller (ACC) 54.7 Register Summary Offset Name 0x00 ACC_CR 0x04 ACC_MR 0x08 ... 0x23 Reserved 0x24 0x28 0x2C 0x30 0x34 ... 0x93 ACC_IER ACC_IDR ACC_IMR ACC_ISR ACC_ACR 0x98 ...
PAGE 1733
SAM E70/S70/V70/V71 Family Analog Comparator Controller (ACC) 54.7.1 ACC Control Register Name: Offset: Reset: Property: Bit ACC_CR 0x00 – Write-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SWRST W – Access Reset Bit Access Reset Bit Access Reset Bit Access Reset Bit 0 – SWRST Software Reset Value Description 0 No effect. 1 Resets the module. © 2019 Microchip Technology Inc.
PAGE 1734
SAM E70/S70/V70/V71 Family Analog Comparator Controller (ACC) 54.7.2 ACC Mode Register Name: Offset: Reset: Property: ACC_MR 0x04 0x00000000 Read/Write This register can only be written if the WPEN bit is cleared in the ACC Write Protection Mode Register.
PAGE 1735
SAM E70/S70/V70/V71 Family Analog Comparator Controller (ACC) Value 3 4 5 6 7 Name AFE0_AD3 AFE0_AD4 AFE0_AD5 AFE1_AD6 AFE1_AD7 Description Select AFE0_AD3 Select AFE0_AD4 Select AFE0_AD5 Select AFE1_AD0 Select AFE1_AD1 Bits 2:0 – SELMINUS[2:0] Selection for Minus Comparator Input 0..7: Selects the input to apply on analog comparator SELMINUS comparison input.
PAGE 1736
SAM E70/S70/V70/V71 Family Analog Comparator Controller (ACC) 54.7.3 ACC Interrupt Enable Register Name: Offset: Reset: Property: Bit ACC_IER 0x24 – Write-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CE W – Access Reset Bit Access Reset Bit Access Reset Bit Access Reset Bit 0 – CE Comparison Edge Value Description 0 No effect. 1 Enables the interrupt when the selected edge (defined by EDGETYP) occurs.
PAGE 1737
SAM E70/S70/V70/V71 Family Analog Comparator Controller (ACC) 54.7.4 ACC Interrupt Disable Register Name: Offset: Reset: Property: Bit ACC_IDR 0x28 – Write-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CE W – Access Reset Bit Access Reset Bit Access Reset Bit Access Reset Bit 0 – CE Comparison Edge Value Description 0 No effect. 1 Disables the interrupt when the selected edge (defined by EDGETYP) occurs.
PAGE 1738
SAM E70/S70/V70/V71 Family Analog Comparator Controller (ACC) 54.7.5 ACC Interrupt Mask Register Name: Offset: Reset: Property: Bit ACC_IMR 0x2C 0x00000000 Read-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CE R 0 Access Reset Bit Access Reset Bit Access Reset Bit Access Reset Bit 0 – CE Comparison Edge Value Description 0 The interrupt is disabled. 1 The interrupt is enabled. © 2019 Microchip Technology Inc.
PAGE 1739
SAM E70/S70/V70/V71 Family Analog Comparator Controller (ACC) 54.7.6 ACC Interrupt Status Register Name: Offset: Reset: Property: Bit Access Reset Bit ACC_ISR 0x30 0x00000000 Read-only 31 MASK R 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 SCO R 0 0 CE R 0 Access Reset Bit Access Reset Bit Access Reset Bit 31 – MASK Flag Mask Value Description 0 The CE flag and SCO value are valid. 1 The CE flag and SCO value are invalid.
PAGE 1740
SAM E70/S70/V70/V71 Family Analog Comparator Controller (ACC) 54.7.7 ACC Analog Control Register Name: Offset: Reset: Property: ACC_ACR 0x94 0 Read/Write This register can only be written if the WPEN bit is cleared in ACC Write Protection Mode Register.
PAGE 1741
SAM E70/S70/V70/V71 Family Analog Comparator Controller (ACC) 54.7.
PAGE 1742
SAM E70/S70/V70/V71 Family Analog Comparator Controller (ACC) 54.7.
PAGE 1743
SAM E70/S70/V70/V71 Family Integrity Check Monitor (ICM) 55. 55.1 Integrity Check Monitor (ICM) Description The Integrity Check Monitor (ICM) is a DMA controller that performs hash calculation over multiple memory regions through the use of transfer descriptors located in memory (ICM Descriptor Area). The Hash function is based on the Secure Hash Algorithm (SHA). The ICM integrates two modes of operation.
PAGE 1744
SAM E70/S70/V70/V71 Family Integrity Check Monitor (ICM) 55.2 Embedded Characteristics • • • • • • • 55.3 DMA AHB Master Interface Supports Monitoring of up to 4 Non-Contiguous Memory Regions Supports Block Gathering Using Linked Lists Supports Secure Hash Algorithm (SHA1, SHA224, SHA256) Compliant with FIPS Publication 180-2 Configurable Processing Period: – When SHA1 algorithm is processed, the runtime period is either 85 or 209 clock cycles.
PAGE 1745
SAM E70/S70/V70/V71 Family Integrity Check Monitor (ICM) 55.4 55.4.1 Product Dependencies Power Management The peripheral clock is not continuously provided to the ICM. The programmer must first enable the ICM clock in the Power Management Controller (PMC) before using the ICM. 55.4.2 Interrupt Sources The ICM interface has an interrupt line connected to the Interrupt Controller. Handling the ICM interrupt requires programming the interrupt controller before configuring the ICM. 55.5 55.5.
PAGE 1746
SAM E70/S70/V70/V71 Family Integrity Check Monitor (ICM) Figure 55-3.
PAGE 1747
SAM E70/S70/V70/V71 Family Integrity Check Monitor (ICM) Figure 55-4.
PAGE 1748
SAM E70/S70/V70/V71 Family Integrity Check Monitor (ICM) Figure 55-5.
PAGE 1749
SAM E70/S70/V70/V71 Family Integrity Check Monitor (ICM) 55.5.2.1 ICM Region Start Address Structure Member Name: Property: ICM_RADDR Read/Write Register offset is calculated as ICM_DSCR+0x000+RID*(0x10).
PAGE 1750
SAM E70/S70/V70/V71 Family Integrity Check Monitor (ICM) 55.5.2.2 ICM Region Configuration Structure Member Name: Property: ICM_RCFG Read/Write Register offset is calculated as ICM_DSCR+0x004+RID*(0x10).
PAGE 1751
SAM E70/S70/V70/V71 Family Integrity Check Monitor (ICM) Value 0 1 Name Description The flag is set when an error is reported on the system bus by the bus matrix. The flag remains cleared even if the setting condition is met. Bit 5 – DMIEN Digest Mismatch Interrupt Disable (Default Enabled) Value Name Description 0 The ICM_ISR.RBE[i] flag is set when the hash value just calculated from the processed region differs from expected hash value. 1 The ICM_ISR.
PAGE 1752
SAM E70/S70/V70/V71 Family Integrity Check Monitor (ICM) 55.5.2.3 ICM Region Control Structure Member Name: Property: ICM_RCTRL Read/Write Register offset is calculated as ICM_DSCR+0x008+RID*(0x10).
PAGE 1753
SAM E70/S70/V70/V71 Family Integrity Check Monitor (ICM) 55.5.2.4 ICM Region Next Address Structure Member Name: Property: ICM_RNEXT Read/Write Register offset is calculated as ICM_DSCR+0x00C+RID*(0x10).
PAGE 1754
SAM E70/S70/V70/V71 Family Integrity Check Monitor (ICM) Table 55-3. LE Resulting SHA-160 Message Digest Memory Mapping Memory Address Address Offset / Byte Lane 0x3 / 31:24 0x2 / 23:16 0x1 / 15:8 0x0 / 7:0 0x000 36 3e 99 a9 0x004 6a 81 06 47 0x008 71 25 3e ba 0x00C 6c c2 50 78 0x010 9d d8 d0 9c Table 55-4.
PAGE 1755
SAM E70/S70/V70/V71 Family Integrity Check Monitor (ICM) Table 55-6. 1024 bits Message Memory Mapping Memory Address 55.5.4 Address Offset / Byte Lane 0x3 / 31:24 0x2 / 23:16 0x1 / 15:8 0x0 / 7:0 0x000 80 63 62 61 0x004–0x078 00 00 00 00 0x07C 18 00 00 00 Using ICM as SHA Engine The ICM can be configured to only calculate a SHA1, SHA224, SHA256 digest value. 55.5.4.
PAGE 1756
SAM E70/S70/V70/V71 Family Integrity Check Monitor (ICM) 55.5.6 Programming the ICM Table 55-7. Region Attributes Transfer Type Single Region Multiple Regions Main List ICM_RCFG CDWBN WRAP EOM NEXT Contiguous list of blocks Digest written to memory Monitoring disabled 1 item 0 0 1 0 The Main List contains only one descriptor. The Secondary List is empty for that descriptor. The digest is computed and saved to memory.
PAGE 1757
SAM E70/S70/V70/V71 Family Integrity Check Monitor (ICM) 55.5.7 Security Features When an undefined register access occurs, the URAD bit in the Interrupt Status Register (ICM_ISR) is set if unmasked. Its source is then reported in the Undefined Access Status Register (ICM_UASR). Only the first undefined register access is available through the ICM_UASR.URAT field.
PAGE 1758
SAM E70/S70/V70/V71 Family Integrity Check Monitor (ICM) 55.6 Register Summary Offset Name 0x00 ICM_CFG 0x04 ICM_CTRL 0x08 ICM_SR 0x0C ... 0x0F Reserved 0x10 0x14 0x18 0x1C ICM_IER ICM_IDR ICM_IMR ICM_ISR 0x20 ICM_UASR 0x24 ... 0x2F Reserved 0x30 ICM_DSCR 0x34 ICM_HASH 0x38 ICM_UIHVAL0 0x3C ICM_UIHVAL1 Bit Pos.
PAGE 1759
SAM E70/S70/V70/V71 Family Integrity Check Monitor (ICM) ...........continued Offset Name 0x40 ICM_UIHVAL2 0x44 ICM_UIHVAL3 0x48 ICM_UIHVAL4 0x4C ICM_UIHVAL5 0x50 ICM_UIHVAL6 0x54 ICM_UIHVAL7 Bit Pos. 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 © 2019 Microchip Technology Inc.
PAGE 1760
SAM E70/S70/V70/V71 Family Integrity Check Monitor (ICM) 55.6.
PAGE 1761
SAM E70/S70/V70/V71 Family Integrity Check Monitor (ICM) Value 0 1 Description Branching to the Secondary List is permitted. Branching to the Secondary List is forbidden. The NEXT field of the ICM_RNEXT structure member has no effect and is always considered as zero. Bit 1 – EOMDIS End of Monitoring Disable Value Description 0 End of Monitoring is permitted. 1 End of Monitoring is forbidden. The EOM bit of the ICM_RCFG structure member has no effect.
PAGE 1762
SAM E70/S70/V70/V71 Family Integrity Check Monitor (ICM) 55.6.
PAGE 1763
SAM E70/S70/V70/V71 Family Integrity Check Monitor (ICM) Value 0 1 Description No effect When set to one, the ICM is activated. © 2019 Microchip Technology Inc.
PAGE 1764
SAM E70/S70/V70/V71 Family Integrity Check Monitor (ICM) 55.6.
PAGE 1765
SAM E70/S70/V70/V71 Family Integrity Check Monitor (ICM) 55.6.
PAGE 1766
SAM E70/S70/V70/V71 Family Integrity Check Monitor (ICM) Value 1 Description When RDM[i] is set to one, the Region i Digest Mismatch interrupt is enabled. Bits 3:0 – RHC[3:0] Region Hash Completed Interrupt Enable Value Description 0 No effect. 1 When RHC[i] is set to one, the Region i Hash Completed interrupt is enabled. © 2019 Microchip Technology Inc.
PAGE 1767
SAM E70/S70/V70/V71 Family Integrity Check Monitor (ICM) 55.6.
PAGE 1768
SAM E70/S70/V70/V71 Family Integrity Check Monitor (ICM) Value 1 Description When RDM[i] is set to one, the Region i Digest Mismatch interrupt is disabled. Bits 3:0 – RHC[3:0] Region Hash Completed Interrupt Disable Value Description 0 No effect. 1 When RHC[i] is set to one, the Region i Hash Completed interrupt is disabled. © 2019 Microchip Technology Inc.
PAGE 1769
SAM E70/S70/V70/V71 Family Integrity Check Monitor (ICM) 55.6.
PAGE 1770
SAM E70/S70/V70/V71 Family Integrity Check Monitor (ICM) Value 1 Description When RDM[i] is set to one, the interrupt is enabled for region i. Bits 3:0 – RHC[3:0] Region Hash Completed Interrupt Mask Value Description 0 When RHC[i] is set to zero, the interrupt is disabled for region i. 1 When RHC[i] is set to one, the interrupt is enabled for region i. © 2019 Microchip Technology Inc.
PAGE 1771
SAM E70/S70/V70/V71 Family Integrity Check Monitor (ICM) 55.6.
PAGE 1772
SAM E70/S70/V70/V71 Family Integrity Check Monitor (ICM) 55.6.
PAGE 1773
SAM E70/S70/V70/V71 Family Integrity Check Monitor (ICM) 55.6.
PAGE 1774
SAM E70/S70/V70/V71 Family Integrity Check Monitor (ICM) 55.6.
PAGE 1775
SAM E70/S70/V70/V71 Family Integrity Check Monitor (ICM) 55.6.11 ICM User Initial Hash Value Register Name: Offset: Reset: Property: Bit ICM_UIHVALx 0x38 + x*0x04 [x=0..
PAGE 1776
SAM E70/S70/V70/V71 Family Integrity Check Monitor (ICM) For ICM_UIHVAL3 field: Example Comment 0x10325476 SHA1 algorithm 0xF70E5939 SHA224 algorithm 0xA54FF53A SHA256 algorithm For ICM_UIHVAL4 field: Example Comment 0xC3D2E1F0 SHA1 algorithm 0xFFC00B31 SHA224 algorithm 0x510E527F SHA256 algorithm For ICM_UIHVAL5 field: Example Comment 0x68581511 SHA224 algorithm 0x9B05688C SHA256 algorithm For ICM_UIHVAL6 field: Example Comment 0x64F98FA7 SHA224 algorithm 0x1F83D9AB SHA256 algori
PAGE 1777
SAM E70/S70/V70/V71 Family True Random Number Generator (TRNG) 56. True Random Number Generator (TRNG) 56.1 Description The True Random Number Generator (TRNG) passes the American NIST Special Publication 800-22 (A Statistical Test Suite for Random and Pseudorandom Number Generators for Cryptographic Applications) and the Diehard Suite of Tests. The TRNG may be used as an entropy source for seeding an NIST approved DRNG (Deterministic RNG) as required by FIPS PUB 140-2 and 140-3. 56.
PAGE 1778
SAM E70/S70/V70/V71 Family True Random Number Generator (TRNG) Status register (TRNG_ISR) is read. The flag TRNG_ISR.DATRDY is set when the random data is ready to be read out on the 32-bit Output Data register (TRNG_ODATA). The normal mode of operation checks that the flag in TRNG_ISR equals ‘1’ before reading TRNG_ODATA when a 32-bit random value is required by the software application. Figure 56-2. TRNG Data Generation Sequence Clock TRNG_CR.
PAGE 1779
SAM E70/S70/V70/V71 Family True Random Number Generator (TRNG) 56.6 Register Summary Offset Name Bit Pos. 0x00 TRNG_CR 7:0 15:8 23:16 31:24 0x04 ... 0x0F Reserved 0x10 0x14 0x18 TRNG_IER TRNG_IDR TRNG_IMR 0x1C TRNG_ISR 0x20 ... 0x4F Reserved 0x50 TRNG_ODATA ENABLE WAKEY[7:0] WAKEY[15:8] WAKEY[23:16] 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 © 2019 Microchip Technology Inc.
PAGE 1780
SAM E70/S70/V70/V71 Family True Random Number Generator (TRNG) 56.6.
PAGE 1781
SAM E70/S70/V70/V71 Family True Random Number Generator (TRNG) 56.6.2 TRNG Interrupt Enable Register Name: Offset: Reset: Property: Bit TRNG_IER 0x10 – Write-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATRDY W – Access Reset Bit Access Reset Bit Access Reset Bit Access Reset Bit 0 – DATRDY Data Ready Interrupt Enable Value Description 0 No effect. 1 Enables the corresponding interrupt. © 2019 Microchip Technology Inc.
PAGE 1782
SAM E70/S70/V70/V71 Family True Random Number Generator (TRNG) 56.6.3 TRNG Interrupt Disable Register Name: Offset: Reset: Property: Bit TRNG_IDR 0x14 – Write-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATRDY W – Access Reset Bit Access Reset Bit Access Reset Bit Access Reset Bit 0 – DATRDY Data Ready Interrupt Disable Value Description 0 No effect. 1 Disables the corresponding interrupt. © 2019 Microchip Technology Inc.
PAGE 1783
SAM E70/S70/V70/V71 Family True Random Number Generator (TRNG) 56.6.4 TRNG Interrupt Mask Register Name: Offset: Reset: Property: Bit TRNG_IMR 0x18 0x00000000 Read-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATRDY R 0 Access Reset Bit Access Reset Bit Access Reset Bit Access Reset Bit 0 – DATRDY Data Ready Interrupt Mask Value Description 0 The corresponding interrupt is not enabled.
PAGE 1784
SAM E70/S70/V70/V71 Family True Random Number Generator (TRNG) 56.6.5 TRNG Interrupt Status Register Name: Offset: Reset: Property: Bit TRNG_ISR 0x1C 0x00000000 Read-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATRDY R 0 Access Reset Bit Access Reset Bit Access Reset Bit Access Reset Bit 0 – DATRDY Data Ready (cleared on read) Value Description 0 Output data is not valid or TRNG is disabled.
PAGE 1785
SAM E70/S70/V70/V71 Family True Random Number Generator (TRNG) 56.6.
PAGE 1786
SAM E70/S70/V70/V71 Family Advanced Encryption Standard (AES) 57. Advanced Encryption Standard (AES) 57.1 Description The Advanced Encryption Standard (AES) is compliant with the American FIPS (Federal Information Processing Standard) Publication 197 specification.
PAGE 1787
SAM E70/S70/V70/V71 Family Advanced Encryption Standard (AES) 57.4 Functional Description The Advanced Encryption Standard (AES) specifies a FIPS-approved cryptographic algorithm that can be used to protect electronic data. The AES algorithm is a symmetric block cipher that can encrypt (encipher) and decrypt (decipher) information. Encryption converts data to an unintelligible form called ciphertext. Decrypting the ciphertext converts the data back into its original form, called plaintext.
PAGE 1788
SAM E70/S70/V70/V71 Family Advanced Encryption Standard (AES) 57.4.3 Last Output Data Mode (CBC_MAC) This mode is used to generate cryptographic checksums on data (MAC) by means of cipher block chaining encryption algorithm (CBC-MAC algorithm for example). The CMAC algorithm is a variant of CBC-MAC with post-processing requiring one-block encryption in ECB mode. Thus CBC-MAC is useful to accelerate CMAC.
PAGE 1789
SAM E70/S70/V70/V71 Family Advanced Encryption Standard (AES) The end of the encryption/decryption is indicated by the end of DMA transfer associated to AES_ODATARx (see the figure below). Two DMA channels are required: one for writing message blocks to AES_IDATARx and one to obtain the result from AES_ODATARx. Figure 57-3. DMA Transfer with AES_MR.
PAGE 1790
SAM E70/S70/V70/V71 Family Advanced Encryption Standard (AES) Note: 1. Depending on the mode, there are other ways of clearing the DATRDY flag. See AES Interrupt Status Register. WARNING 57.4.4 In DMA mode, reading AES_ODATARx before the last data transfer may lead to unpredictable results. Galois/Counter Mode (GCM) 57.4.4.
PAGE 1791
SAM E70/S70/V70/V71 Family Advanced Encryption Standard (AES) Figure 57-5.
PAGE 1792
SAM E70/S70/V70/V71 Family Advanced Encryption Standard (AES) 3. Generating the Tag using length of AAD, length of C and J0 (refer to NIST documentation for details). The Tag generation can be done either automatically, after the end of AAD/C processing if AES_MR.GTAGEN is set, or manually using AES_GHASHRx.GHASH (see subsections Processing a Complete Message with Tag Generation and Manual GCM Tag Generation for details). 57.4.4.3.
PAGE 1793
SAM E70/S70/V70/V71 Family Advanced Encryption Standard (AES) To process a message by fragments, the sequence is as follows: • 1. 2. 3. 4. 5. 6. 7. • 1. 2. 3. 4. 5. 6. 7. First fragment: Set AES_MR.OPMOD to GCM and AES_MR.GTAGEN to ‘0’. Set the AES Key Register and wait for AES_ISR.DATRDY to be set (GCM hash subkey generation complete); use interrupt if needed. After the GCM hash subkey generation is complete the GCM hash subkey can be read or overwritten with specific value in AES_GCMHRx.
PAGE 1794
SAM E70/S70/V70/V71 Family Advanced Encryption Standard (AES) Processing S = GHASHH (AAD || 0v || C || 0u || [len(AAD)]64 || [len(C)]64): 1. 2. 3. 4. 5. 6. Set AES_MR.OPMOD to GCM and AES_MR.GTAGEN to ‘0’. Set the AES Key Register and wait for AES_ISR.DATRDY to be set (GCM hash subkey generation complete); use interrupt if needed. After the GCM hash subkey generation is complete the GCM hash subkey can be read or overwritten with specific value in AES_GCMHRx.
PAGE 1795
SAM E70/S70/V70/V71 Family Advanced Encryption Standard (AES) To run a GF128 multiplication (A x B), the sequence is as follows: 1. Set AES_MR.OPMOD to GCM and AES_MR.GTAGEN to ‘0’. 1. 2. 3. 4. Configure AES_AADLENR.AADLEN with 0x10 (16 bytes) and AES_CLENR.CLEN to ‘0’. This will allow running a single GHASHH. Fill AES_GCMHRx.H with B value. Fill AES_IDATARx.IDATA with the A value according to the SMOD configuration used.
PAGE 1796
SAM E70/S70/V70/V71 Family Advanced Encryption Standard (AES) Note: 1. In 64-bit CFB mode, writing to AES_IDATAR2 and AES_IDATAR3 is not allowed and may lead to errors in processing. 2. In 32, 16, and 8-bit CFB modes, writing to AES_IDATAR1, AES_IDATAR2 and AES_IDATAR3 is not allowed and may lead to errors in processing. 57.4.6.
PAGE 1797
SAM E70/S70/V70/V71 Family Advanced Encryption Standard (AES) AES_ISR.URAD and AES_ISR.URAT can only be reset by AES_CR.SWRST. © 2019 Microchip Technology Inc.
PAGE 1798
SAM E70/S70/V70/V71 Family Advanced Encryption Standard (AES) 57.5 Register Summary Offset Name 0x00 AES_CR 0x04 AES_MR 0x08 ... 0x0F Reserved 0x10 0x14 0x18 0x1C AES_IER AES_IDR AES_IMR AES_ISR 0x20 AES_KEYWR0 0x24 AES_KEYWR1 0x28 AES_KEYWR2 0x2C AES_KEYWR3 0x30 AES_KEYWR4 0x34 AES_KEYWR5 0x38 AES_KEYWR6 Bit Pos.
PAGE 1799
SAM E70/S70/V70/V71 Family Advanced Encryption Standard (AES) ...........continued Offset Name 0x3C AES_KEYWR7 0x40 AES_IDATAR0 0x44 AES_IDATAR1 0x48 AES_IDATAR2 0x4C AES_IDATAR3 0x50 AES_ODATAR0 0x54 AES_ODATAR1 0x58 AES_ODATAR2 0x5C AES_ODATAR3 0x60 AES_IVR0 0x64 AES_IVR1 0x68 AES_IVR2 0x6C AES_IVR3 0x70 AES_AADLENR Bit Pos.
PAGE 1800
SAM E70/S70/V70/V71 Family Advanced Encryption Standard (AES) ...........continued Offset Name 0x74 AES_CLENR 0x78 AES_GHASHR0 0x7C AES_GHASHR1 0x80 AES_GHASHR2 0x84 AES_GHASHR3 0x88 AES_TAGR0 0x8C AES_TAGR1 0x90 AES_TAGR2 0x94 AES_TAGR3 0x98 AES_CTRR 0x9C AES_GCMHR0 0xA0 AES_GCMHR1 0xA4 AES_GCMHR2 0xA8 AES_GCMHR3 Bit Pos.
PAGE 1801
SAM E70/S70/V70/V71 Family Advanced Encryption Standard (AES) 57.5.1 AES Control Register Name: Offset: Reset: Property: Bit AES_CR 0x00 – Write-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 SWRST W – 7 6 5 4 3 2 1 0 START W – Access Reset Bit Access Reset Bit Access Reset Bit Access Reset Bit 8 – SWRST Software Reset Value Description 0 No effect. 1 Resets the AES. A software-triggered hardware reset of the AES interface is performed.
PAGE 1802
SAM E70/S70/V70/V71 Family Advanced Encryption Standard (AES) 57.5.
PAGE 1803
SAM E70/S70/V70/V71 Family Advanced Encryption Standard (AES) Value 1 Description The DATRDY flag is cleared when at least one of the Input Data Registers is written. No more Output Data Register reads are necessary between consecutive encryptions/decryptions (see Last Output Data Mode). Bits 14:12 – OPMOD[2:0] Operating Mode For CBC-MAC operating mode, set OPMOD to CBC and LOD to 1.
PAGE 1804
SAM E70/S70/V70/V71 Family Advanced Encryption Standard (AES) 57.5.3 AES Interrupt Enable Register Name: Offset: Reset: Property: AES_IER 0x10 – Write-only The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Enables the corresponding interrupt.
PAGE 1805
SAM E70/S70/V70/V71 Family Advanced Encryption Standard (AES) 57.5.4 AES Interrupt Disable Register Name: Offset: Reset: Property: AES_IDR 0x14 – Write-only The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Disables the corresponding interrupt.
PAGE 1806
SAM E70/S70/V70/V71 Family Advanced Encryption Standard (AES) 57.5.5 AES Interrupt Mask Register Name: Offset: Reset: Property: AES_IMR 0x18 0x00000000 Read-only The following configuration values are valid for all listed bit names of this register: 0: The corresponding interrupt is not enabled. 1: The corresponding interrupt is enabled.
PAGE 1807
SAM E70/S70/V70/V71 Family Advanced Encryption Standard (AES) 57.5.6 AES Interrupt Status Register Name: Offset: Reset: Property: Bit AES_ISR 0x1C 0x00000000 Read-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TAGRDY R 0 15 14 13 12 11 10 9 8 URAD R 0 3 2 1 0 DATRDY R 0 Access Reset Bit Access Reset Bit URAT[3:0] Access Reset R 0 R 0 R 0 R 0 Bit 7 6 5 4 Access Reset Bit 16 – TAGRDY GCM Tag Ready Value Description 0 GCM Tag is not valid.
PAGE 1808
SAM E70/S70/V70/V71 Family Advanced Encryption Standard (AES) 57.5.7 AES Key Word Register x Name: Offset: Reset: Property: Bit 31 AES_KEYWRx 0x20 + x*0x04 [x=0..
PAGE 1809
SAM E70/S70/V70/V71 Family Advanced Encryption Standard (AES) 57.5.8 AES Input Data Register x Name: Offset: Reset: Property: Bit 31 AES_IDATARx 0x40 + x*0x04 [x=0..
PAGE 1810
SAM E70/S70/V70/V71 Family Advanced Encryption Standard (AES) 57.5.9 AES Output Data Register x Name: Offset: Reset: Property: AES_ODATARx 0x50 + x*0x04 [x=0..
PAGE 1811
SAM E70/S70/V70/V71 Family Advanced Encryption Standard (AES) 57.5.10 AES Initialization Vector Register x Name: Offset: Reset: Property: Bit 31 AES_IVRx 0x60 + x*0x04 [x=0..
PAGE 1812
SAM E70/S70/V70/V71 Family Advanced Encryption Standard (AES) 57.5.
PAGE 1813
SAM E70/S70/V70/V71 Family Advanced Encryption Standard (AES) 57.5.
PAGE 1814
SAM E70/S70/V70/V71 Family Advanced Encryption Standard (AES) 57.5.13 AES GCM Intermediate Hash Word Register x Name: Offset: Reset: Property: Bit Access Reset Bit Access Reset Bit Access Reset Bit Access Reset AES_GHASHRx 0x78 + x*0x04 [x=0..
PAGE 1815
SAM E70/S70/V70/V71 Family Advanced Encryption Standard (AES) 57.5.14 AES GCM Authentication Tag Word Register x Name: Offset: Reset: Property: Bit 31 AES_TAGRx 0x88 + x*0x04 [x=0..
PAGE 1816
SAM E70/S70/V70/V71 Family Advanced Encryption Standard (AES) 57.5.
PAGE 1817
SAM E70/S70/V70/V71 Family Advanced Encryption Standard (AES) 57.5.16 AES GCM H Word Register x Name: Offset: Reset: Property: Bit 31 AES_GCMHRx 0x9C + x*0x04 [x=0..
PAGE 1818
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM ... 58. Electrical Characteristics for SAM V70/V71 58.1 Absolute Maximum Ratings Table 58-1. Absolute Maximum Ratings(1) Storage Temperature -60°C to + 150°C Voltage on Input Pins with Respect to Ground -0.3V to + 4.0V Maximum Operating Voltage VDDPLL, VDDUTMIC, VDDCORE 1.4V Maximum Operating Voltage VDDIO, VDDUTMII, VDDPLLUSB, VDDIN 4.0V Note: 1.
PAGE 1819
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM ... ...........continued Symbol Power Dissipation PD 58.2 Parameter Conditions Min. Typ. Max. Unit At TA = 85°C, LQFP64 ¯ ¯ 833 mW At TA = 105°C, LQFP64 ¯ ¯ 417 mW DC Characteristics The following characteristics are applicable to the operating temperature range: TA [-40°C : +105°C], unless otherwise specified. Table 58-3. DC Characteristics Symbol Parameter DC Supply Core VDDCORE DC Supply I/Os, Backup Typ. Max.
PAGE 1820
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM ... ...........continued Symbol VDDUTMII Parameter Conditions Min. Typ. Max. Unit DC Supply UDPHS and UHPHS UTMI + Interface – 3.0 3.3 3.6 V – – 20 mV 3.0 3.3 3.6 V – – 10 mV Allowable rms value 10 Voltage Ripple kHz to 10 MHz VDDPLLUSB DC Supply UTMI PLL – Allowable rms value 10 Voltage Ripple kHz to 10 MHz Note: 1. VDDIO voltage must be equal to VDDIN voltage. Table 58-4.
PAGE 1821
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM ... ...........continued Symbol Parameter Conditions Min. Typ. Max. Unit IIH Pulldown OFF -1 – 1 µA Pulldown ON 10 – 55 GPIO_MLB – 9 – GPIO_AD, GPIO_CLK – 14 – GPIO, CLOCK, RST, TEST – 26 – High-level Input Current RSERIAL Serial Resistor Ohm Table 58-5.
PAGE 1822
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM ... Table 58-7. VDDCORE Power-on Reset Characteristics Symbol Parameter Conditions Min. Typ. Max. Unit VT+ Threshold Voltage Rising – 0.79 0.95 1.07 V VT- Threshold Voltage Falling – 0.66 0.89 – V Vhys Hysteresis Voltage – 10 60 115 mV tRES Reset Timeout Period – 240 350 800 µs Figure 58-2. VDDCORE Power-On Reset Characteristics VDDCORE VT+ VT- Reset Table 58-8.
PAGE 1823
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM ... Table 58-9. Threshold Selection Symbol VT Parameter Supply Monitor Threshold Digital Code Min. Typ. Max. 0 – 1.6 – 1 – 1.72 – 10 – 1.84 – 11 – 1.96 – 100 – 2.08 – 101 – 2.2 – 110 – 2.32 – 111 – 2.44 – 1000 – 2.56 – 1001 – 2.68 – 1010 – 2.8 – 1011 – 2.92 – 1100 – 3.04 – 1101 – 3.16 – 1110 – 3.28 – 1111 – 3.4 – Unit V Figure 58-3.
PAGE 1824
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM ... Figure 58-4. VDDIO Power-On Reset Characteristics VDDIO VT+ VT- Reset 58.3 Power Consumption • • • 58.3.1 Power consumption of the device depending on the different low-power modes (Backup, Wait, Sleep) and Active mode.
PAGE 1825
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM ... VDDIO = 3.3V 8 39 61 µA VDDIO = 3.0V 7.6 38 59 µA Table 58-12. Worst Case Power Consumption for Backup Mode with 1 Kbyte BACKUP SRAM Off Total Consumption 58.3.2 Worst Case Value Unit at 25°C at 85°C at 105°C Conditions AMP1 AMP1 AMP1 VDDIO = 3.6V 5.1 16.4 24 µA VDDIO = 3.3V 3.7 14.8 23 µA VDDIO = 3.0V 3.4 13.
PAGE 1826
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM ... Table 58-13. Typical Sleep Mode Current Consumption vs. Master Clock (MCK) Variation with PLLA Core Clock/MCK (MHz) VDDCORE Consumption (AMP1) 300/150 20 24 0.85 250/125 17 20 1.05 150/150 20 24 0.9 96/96 12.5 15 1.4 96/48 7.5 10 2.5 48/48 7 9.5 2.8 24/24 3.5 5 24/12 2 3 10 12/12 2 3 11.2 8/8 1.5 2 16.8 4/4 1.0 1.5 32.9 4/2 0.9 1 60 4/1 0.8 1 112.
PAGE 1827
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM ... Figure 58-7. Measurement Setup for Wait Mode AMP2 3.3V VDDIO VDDIN AMP1 Voltage Regulator VDDOUT VDDCORE VDDPLL The following tables give current consumption and wakeup time(1) in Wait mode. Table 58-15. Typical Current Consumption in Wait Mode Typical Value Wait Mode Consumption at 25°C at 85°C at 105°C VDDIO = 3.3V VDDIO = 3.3V VDDIO = 3.
PAGE 1828
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM ... Figure 58-8. Active Mode Measurement Setup AMP2 3.3V VDDIO VDDIN Voltage Regulator VDDOUT AMP1 VDDCORE VDDPLL The following table gives current consumption in Active mode in typical conditions. Table 58-17. Typical Total Active Power Consumption with VDDCORE at 1.2V Running from Embedded Memory (AMP2) Core Clock/MCK (MHz) Cortex-M7 Running CoreMark Unit Flash Cache Enable (CE) CoreMark = 4.9/MHz TCM Cache Disable (CD) CoreMark = 1.
PAGE 1829
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM ... ...........continued 58.4.2 Symbol Parameter tSTART Startup Time IDDON Current Consumption Conditions Min. Typ. Max. Unit – – 120 µs – 540 – nA – After startup time 4/8/12 MHz RC Oscillator The 4/8/12 MHz RC oscillator is calibrated in production. This calibration can be read through the Get CALIB bit command (refer to the 22.
PAGE 1830
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM ... where CPCB is the capacitance of the printed circuit board (PCB) track layout from the crystal to the pin. 58.4.4 32.768 kHz Crystal Characteristics Table 58-21. 32.768 kHz Crystal Characteristics 58.4.5 Symbol Parameter Conditions Min. Typ. Max. Unit ESR Equivalent Series Resistor Crystal at 32.768 kHz – 50 100 kOhm CM Motional Capacitance Crystal at 32.768 kHz 2 – 4 fF CSHUNT Shunt Capacitance Crystal at 32.
PAGE 1831
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM ... Figure 58-10. 3 to 20 MHz Crystal Oscillator Schematics Microchip MCU CL XOUT XIN R = 1K if crystal frequency is lower than 8 MHz CLEXT CCRYSTAL CLEXT CLEXT = 2 × (CCRYSTAL – CL – CPCB) where, CPCB is the capacitance of the printed circuit board (PCB) track layout from the crystal to the pin. 58.4.7 3 to 20 MHz Crystal Characteristics Table 58-24. 3 to 20 MHz Crystal Characteristics Symbol ESR CM 58.4.
PAGE 1832
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM ... 58.4.9 Crystal Oscillator Design Considerations 58.4.9.1 Choosing a Crystal When choosing a crystal for the 32768 Hz Slow Clock Oscillator or for the 3 MHz–20 MHz oscillator, users need to consider several parameters.
PAGE 1833
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM ... 58.7 USB Transceiver Characteristics The device conforms to all voltage, power, and timing characteristics and specifications as set forth in the USB 2.0 specification. Refer to the USB 2.0 specification for additional information. Table 58-28.
PAGE 1834
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM ... Figure 58-11. Single-ended Mode AFE Reception module AFE_AD0–5 MX0 AFE DAC0 S/H0 + PGA0 MUX AFE_AD6–11 MX1 S/H1 + - ADC12 12b PGA1 DAC1 Reception module Averager AFE Digital Controller Figure 58-12. Differential Mode AFE Reception module AFE_AD0–1 AFE_AD2–3 AFE_AD4–5 MX0 AFE VREFP/2 S/H0 + PGA0 MUX AFE_AD6–7 AFE_AD8–9 AFE_AD10–11 MX1 S/H1 Reception module + - ADC12 PGA1 VREFP/2 AFE Digital Controller 58.8.
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SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM ... Note: 1. Current consumption is measured with AFEC_ACR.IBCTL=10. 2. In Sleep mode, the AFE core, the Sample and Hold and the internal reference operational amplifier are off. 3. In Fast Wake-up mode, only the AFE core is off. 58.8.1.2 ADC Bias Current AFEC_ACR.IBCTL controls the ADC bias current with the nominal setting IBCTL = 10. IBCTL = 10 is the mandatory configuration suitable for a sampling frequency of up to 1 MHz.
PAGE 1836
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM ... In Differential mode, the Sample-and-Hold common mode voltage is equal to VDAC = VVREFP/2 (set by software DAC0 and DAC1 to code 512). In Single-ended mode, VDAC is the common mode voltage. VDAC is the output of DAC0 or DAC1 voltage. All operations after the Sample-and-Hold are differential, including those in Single-ended mode. For the formula example, the internal DAC0 or DAC1 is set for the code 512.
PAGE 1837
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM ... • – Gain = 2, LSB = (1.5V / 4096) = 366 μV – Gain = 4, LSB = (750 mV / 4096) = 183 μV Differential (DIFF) (ex: VVREFP = 3.0V) – Gain = 1, LSB = (6.0V / 4096) = 1465 μV – Gain = 2, LSB = (3.0V / 4096) = 732 μV – Gain = 4, LSB = (1.5V / 4096) = 366 μV The data include the AFE performances, as the PGA and AFE core cannot be separated. The temperature and voltage dependency are given as separate parameters. 58.8.4.
PAGE 1838
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM ... Figure 58-14.
PAGE 1839
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM ... ...........continued Symbol Parameter Conditions Min. Typ. Gain = 1 INL Integral Non-Linearity Gain = 2 Differential Non-Linearity Unit 12 LSB 6 LSB ±2 -12 ±2.6 Gain = 4 DNL Max. ±2.7 – -6 ±2 Note: INL/DNL given inside the linear range of the AFE: 2% to 98% of VREFP. Table 58-36. AFE Offset and Gain Error, VVREFP = 1.7V to 3.3V Symbol Parameter Conditions Min. Typ(1). Max. Unit Gain=1 -20 – 35 LSB Gain=1 -0.
PAGE 1840
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM ... where: • fS is the sampling frequency of the AFE channel • Typ values are used to compute AFE input impedance ZIN Table 58-37. Input Capacitance (CIN) Values Gain Selection Single-ended Differential Unit 1 2 2 pF 2 4 4 4 8 8 Table 58-38. ZIN Input Impedance fS (MHz) 1 0.5 0.25 0.125 0.0625 0.03125 0.015625 0.007813 0.5 1 2 4 8 16 32 64 0.25 0.5 1 2 4 8 16 32 0.125 0.25 0.
PAGE 1841
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM ... 58.8.6.2 AFE DAC Offset Compensation Table 58-40. DAC Static Performances (see Note 1) Symbol Parameter Conditions Min. Typ. Max. Unit N Resolution (see Note 2) – – 9 10 LSB INL Integral Non Linearity – -2.5 ±0.7 2 LSB DNL Differential Non Linearity – -3 ±0.5 1.8 LSB Note: 1. DAC Offset is included in the AFE EO performances. 2. 10 bits LSB relative to VREFP scale, LSB = VVREFP / 210 = 2.93 mV, with VVREFP = 3V.
PAGE 1842
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM ... ...........continued Symbol Parameter Conditions Min. Typ. Max.
PAGE 1843
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM ... Table 58-45. Voltage Reference Symbol Parameter Conditions Min. Typ. Max. Unit VVREFP Positive Voltage Reference Externally decoupled 1 µF 1.7 – VDDIN V IVREFP DC Current on VREFP – – 2.5 – µA Note: VREFP is the positive reference shared with AFE and may have a different value for AFE. Refer to the AFE electrical characteristics if AFE is used. The VREFN pin must be connected to ground. Table 58-46.
PAGE 1844
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM ... Table 58-49. Analog Outputs 58.12 Symbol Parameter Conditions Min. Typ. Max. RLOAD Output Resistor Load Output load resistor 5 – – kOhm CLOAD Output Capacitor Load Output load capacitor – – 50 pF VDACx_MIN Minimum Output Voltage on DACx Code = 0x000 No RLOAD, CLOAD = 50 pF, DACC_ACR.IBCTLCHx =3 – 0.1 0.5 %. VVREFP VDACx_MAX Maximum Output Voltage on DACx Code = 0xFFF No RLOAD CLOAD = 50 pF, DACC_ACR.
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SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM ... ...........continued Parameter Conditions Min. Typ. Max. Flash Active Current Random 128-bit read at maximum frequency at 25°C on VDDCORE =1.2V – 16 20 on VDDIO – 2 10 Program at 25°C on VDDCORE =1.2V – 2 3 on VDDIO – 8 12 on VDDCORE =1.2V – 2 2 on VDDIO – 8 12 Erase at 25°C Unit mA Note: 1. Cycling over full temperature range.
PAGE 1846
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM ... • • • Output duty cycle (40%-60%) Minimum output swing: 100 mV to VDDIO - 100 mV Addition of rising and falling time inferior to 75% of the period Table 58-54. I/O Characteristics Symbol FreqMax1 Parameter Conditions Pin Group 1(1) Maximum output frequency Min. Max. Unit MHz Load VDDIO Drive Level 10 pF 3.0V Low – 65 High – 115 Low – 28 High – 55 25 pF PulseminH1 Pin Group 1(1) High Level Pulse Width 10 pF 3.
PAGE 1847
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM ... 58.13.1.5 QSPI Characteristics Figure 58-17. QSPI Master Mode with (CPOL= NCPHA = 0) or (CPOL= NCPHA= 1) QSCK QSPI0 QSPI1 QIOx_DIN QSPI2 QIOx_DOUT Figure 58-18. QSPI Master Mode with (CPOL = 0 and NCPHA=1) or (CPOL=1 and NCPHA= 0) QSCK QSPI3 QSPI4 QIOx_DIN QSPI5 QIOx_DOUT 58.13.1.5.1 Maximum QSPI Frequency The following sections provide maximum QSPI frequency in master read and write modes.
PAGE 1848
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM ... ...........continued Symbol Parameter Conditions Min Max Unit QSPI4 QIOx data in to QSCK falling edge(input hold time) 3.3V domain 0 – ns QSPI5 QSCK falling edge to QIOx data out valid 3.3V domain -1.6 1.8 ns Timings are given for the 3.3V domain, with VDDIO from 2.85V to 3.6V, maximum external capacitor = 40 pF. 58.13.1.
PAGE 1849
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM ... Figure 58-22. SPI Slave Mode with (CPOL=0 and NCPHA=1) or (CPOL=1 and NCPHA=0) NPCSS SPI13 SPI12 SPCK SPI6 MISO SPI7 SPI8 MOSI Figure 58-23. SPI Slave Mode with (CPOL = NCPHA = 0) or (CPOL= NCPHA= 1) NPCS0 SPI15 SPI14 SPCK SPI9 MISO SPI10 SPI11 MOSI 58.13.1.6.1 Maximum SPI Frequency The following formulas provide maximum SPI frequency in master read and write modes and in slave read and write modes.
PAGE 1850
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM ... Slave Write Mode �SPCKmax = 1 2� �PI6max or SPI9max + �setup tsetup is the setup time from the master before sampling data. 58.13.1.6.2 SPI Timings Timings are given for the 3.3V domain, with VDDIO from 2.85V to 3.6V, maximum external capacitor = 40 pF. Table 58-56. SPI Timings Symbol Parameter Conditions Min Max Unit SPI0 MISO Setup time before SPCK rises (master) 3.3V domain 12.
PAGE 1851
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM ... 58.13.1.9.1 Read Timings Table 58-57. SMC Read Signals - NRD Controlled (READ_MODE = 1) Symbol Parameter Min Max Unit NO HOLD Settings (NRD_HOLD = 0) SMC1 Data Setup before NRD High SMC2 Data Hold after NRD High 14.3 – ns 0 – ns 12.1 – ns 0 – ns (NRD_SETUP + NRD_PULSE) × tCPMCK - 4.3 – ns (NRD_SETUP + NRD_PULSE - NCS_RD_SETUP) × tCPMCK - 2.4 – ns NRD_PULSE × tCPMCK - 0.
PAGE 1852
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM ... ...........continued Symbol Parameter Min Max Unit HOLD Settings (NWE_HOLD ≠ 0) SMC19 NWE High to Data OUT, NBS0/A0 NBS1, NBS2/A1, NBS3, A2–A25 change SMC20 NWE High to NCS Inactive (1) NWE_HOLD × tCPMCK - 3.9 – ns (NWE_HOLD - NCS_WR_HOLD) × tCPMCK - 3.6 – ns – ns NO HOLD Settings (NWE_HOLD = 0) SMC21 NWE High to Data OUT, NBS0/A0 NBS1, NBS2/A1, NBS3, A2–A25, NCS change(1) 1.
PAGE 1853
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM ... Figure 58-25. SMC Timings - NRD Controlled Read and NWE Controlled Write SMC21 SMC17 SMC5 SMC5 SMC17 SMC19 A0-A23 SMC6 SMC21 SMC6 SMC18 SMC18 SMC20 NCS NRD SMC7 SMC7 SMC1 SMC2 SMC15 SMC21 SMC3 SMC15 SMC4 SMC19 DATA NWE SMC16 NRD Controlled READ with NO HOLD SMC16 NWE Controlled WRITE with NO HOLD NRD Controlled READ with HOLD NWE Controlled WRITE with HOLD 58.13.1.
PAGE 1854
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM ... Figure 58-27. USART SPI Slave Mode (Mode 1 or 2) • The MOSI line drives the input pin RXD • The MISO line is driven by the output pin TXD • The SCK line drives the input pin SCK • The NSS line drives the input pin CTS NSS SPI13 SPI12 SCK SPI6 MISO SPI7 SPI8 MOSI Figure 58-28. USART SPI Slave Mode (Mode 0 or 3) NSS SPI14 SPI15 SCK SPI9 MISO SPI10 SPI11 MOSI 58.13.1.11.1 USART SPI Timings Timings are given for the 3.
PAGE 1855
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM ... ...........continued Symbol Parameter Min Max Unit SPI6 SCK falling to MISO 2.9 13.9 ns SPI7 MOSI Setup time before SCK rises 2.0 – ns SPI8 MOSI Hold time after SCK rises 0.2 – ns SPI9 SCK rising to MISO 3.0 13.5 ns SPI10 MOSI Setup time before SCK falls 2.1 – ns SPI11 MOSI Hold time after SCK falls 0.4 – ns SPI12 NPCS0 setup to SCK rising 0.6 – ns SPI13 NPCS0 hold after SCK falling 0.
PAGE 1856
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM ... ...........continued Symbol Parameter Condition Min. Max. tHD;DAT fTWCK ≤ 100 kHz 0 3 × tCPMCK(5) μs fTWCK > 100 kHz 0 3 ×tCPMCK(5) μs fTWCK ≤ 100 kHz tLOW - 3 × tCPMCK(5) – ns fTWCK > 100 kHz tLOW - 3 × tCPMCK(5) – ns fTWCK ≤ 100 kHz tHIGH – μs fTWCK > 100 kHz tHIGH – μs fTWCK ≤ 100 kHz tHIGH – μs fTWCK > 100 kHz tHIGH – μs tSU;DAT tSU;STO tHD;STA Note: 1. 2. 3. 4. 5.
PAGE 1857
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM ... Note: 1. For GMAC output signals, min and max access time are defined. The min access time is the time between the GMDC falling edge and the signal change. The max access timing is the time between the GMDC falling edge and the signal stabilizes. The figure below illustrates min and max accesses for GMAC3. Figure 58-30. Min and Max Access Time of GMAC Output Signals GMDC GMAC1 GMAC3 max GMAC2 GMDIO GMAC4 GMAC5 GMAC3 min 58.13.1.13.
PAGE 1858
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM ... Figure 58-31. GMAC MII Mode Signals EMDC GMAC1 GMAC3 GMAC2 EMDIO GMAC4 GMAC5 GMAC6 GMAC7 ECOL ECRS ETXCK GMAC8 ETXER GMAC9 ETXEN GMAC10 ETX[3:0] ERXCK GMAC11 GMAC12 ERX[3:0] GMAC13 GMAC14 GMAC15 GMAC16 ERXER ERXDV 58.13.1.13.4 RMII Mode Table 58-66.
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SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM ... Figure 58-32. GMAC RMII Mode Signals EREFCK GMAC21 ETXEN GMAC22 ETX[1:0] GMAC23 GMAC24 ERX[1:0] GMAC25 GMAC26 GMAC27 GMAC28 ERXER ECRSDV 58.13.1.14 SSC Timings 58.13.1.14.1 Timing Conditions Timings are given assuming the load capacitance as shown in the following table. Table 58-67. Load Capacitance Supply CL Max. 3.3V 30 pF 58.13.1.14.2 Timing Extraction Figure 58-33.
PAGE 1860
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM ... Figure 58-35. SSC Transmitter, TK in Output and TF in Input TK (CKI=0) TK (CKI=1) SSC2 SSC3 TF SSC4 TD Figure 58-36. SSC Transmitter, TK and TF in Input TK (CKI=0) TK (CKI=1) SSC5 SSC6 TF SSC7 TD Figure 58-37. SSC Receiver RK and RF in Input RK (CKI=0) RK (CKI=1) SSC8 SSC9 RF/RD Figure 58-38. SSC Receiver, RK in Input and RF in Output RK (CKI=0) RK (CKI=1) SSC8 SSC9 RD SSC10 RF © 2019 Microchip Technology Inc.
PAGE 1861
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM ... Figure 58-39. SSC Receiver, RK and RF in Output RK (CKI=0) RK (CKI=1) SSC11 SSC12 RD SSC13 RF Figure 58-40. SSC Receiver, RK in Output and RF in Input RK (CKI=0) RK (CKI=1) SSC11 SSC12 RF/RD Table 58-68. SSC Timings with 3.3V Peripheral Supply Symbol Parameter Condition Min. Max. Unit Transmitter SSC0 TK edge to TF/TD (TK output, TF output) – -3.9(1) 4.0 (1) ns SSC1 TK edge to TF/TD (TK input, TF output) – 3.1(1) 12.
PAGE 1862
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM ... ...........continued Symbol Parameter SSC12 SSC13 Condition RF/RD hold time after RK edge (RK output) – RK edge to RF (RK output) – Min. Max. Unit tCPMCK - 2.8 – ns -2.1(1) 1.9(1) ns Note: For output signals (TF, TD, RF), minimum and maximum access times are defined. The minimum access time is the time between the TK (or RK) edge and the signal change.
PAGE 1863
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM E70/S70 59. Electrical Characteristics for SAM E70/S70 59.1 Absolute Maximum Ratings Table 59-1. Absolute Maximum Ratings(1) Storage Temperature -60°C to + 150°C Voltage on Input Pins with Respect to Ground -0.3V to + 4.0V Maximum Operating Voltage VDDPLL, VDDUTMIC, VDDCORE 1.4V Maximum Operating Voltage VDDIO, VDDUTMII, VDDPLLUSB, VDDIN 4.0V Note: 1.
PAGE 1864
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM E70/S70 ...........continued Symbol Power Dissipation PD 59.2 Parameter Conditions Min. Typ. Max. Unit At TA = 85°C, LQFP64 ¯ ¯ 833 mW At TA = 105°C, LQFP64 ¯ ¯ 417 mW DC Characteristics The following characteristics are applicable to the operating temperature range: TA [-40°C : +105°C], unless otherwise specified. Table 59-3. DC Characteristics Symbol Parameter DC Supply Core VDDCORE DC Supply I/Os, Backup Typ. Max.
PAGE 1865
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM E70/S70 ...........continued Symbol VDDUTMII Parameter Conditions Min. Typ. Max. Unit DC Supply UDPHS and UHPHS UTMI + Interface – 3.0 3.3 3.6 V – – 20 mV 3.0 3.3 3.6 V – – 10 mV Allowable rms value 10 Voltage Ripple kHz to 10 MHz VDDPLLUSB DC Supply UTMI PLL – Allowable rms value 10 Voltage Ripple kHz to 10 MHz Note: 1. VDDIO voltage must be equal to VDDIN voltage. Table 59-4.
PAGE 1866
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM E70/S70 ...........continued Symbol Parameter Conditions Min. Typ. Max. Unit IIH Pulldown OFF -1 – 1 µA Pulldown ON 10 – 55 GPIO_MLB – 9 – GPIO_AD, GPIO_CLK – 14 – GPIO, CLOCK, RST, TEST – 26 – High-level Input Current RSERIAL Serial Resistor Ohm Table 59-5.
PAGE 1867
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM E70/S70 Table 59-7. VDDCORE Power-on Reset (POR) Characteristics Symbol Parameter Conditions Min. Typ. Max. Unit VT+ Threshold Voltage Rising – 0.79 0.95 1.07 V VT- Threshold Voltage Falling – 0.66 0.89 – V Vhys Hysteresis Voltage – 10 60 115 mV tRES Reset Timeout Period – 240 350 800 µs Figure 59-2. VDDCORE Power-On Reset Characteristics VDDCORE VT+ VT- Reset Table 59-8.
PAGE 1868
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM E70/S70 Table 59-9. Threshold Selection Symbol VT Parameter Supply Monitor Threshold Digital Code Min. Typ. Max. 0 – 1.6 – 1 – 1.72 – 10 – 1.84 – 11 – 1.96 – 100 – 2.08 – 101 – 2.2 – 110 – 2.32 – 111 – 2.44 – 1000 – 2.56 – 1001 – 2.68 – 1010 – 2.8 – 1011 – 2.92 – 1100 – 3.04 – 1101 – 3.16 – 1110 – 3.28 – 1111 – 3.4 – Unit V Figure 59-3.
PAGE 1869
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM E70/S70 Figure 59-4. VDDIO Power-On Reset Characteristics VDDIO VT+ VT- Reset 59.3 Power Consumption • • • 59.3.1 Power consumption of the device depending on the different low-power modes (Backup, Wait, Sleep) and Active mode.
PAGE 1870
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM E70/S70 ...........continued Total Consumption Worst Case Value Unit at 25°C at 85°C at 105°C Conditions AMP1 AMP1 AMP1 VDDIO = 3.3V 8 39 61 µA VDDIO = 3.0V 7.6 38 59 µA VDDIO = 2.5V 5.2 37 58 µA VDDIO = 1.7V 3.8 35 56 µA Table 59-12. Worst Case Power Consumption for Backup Mode with 1 Kbyte BACKUP SRAM Off Total Consumption 59.3.
PAGE 1871
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM E70/S70 Table 59-13. Typical Sleep Mode Current Consumption vs. Master Clock (MCK) Variation with PLLA Core Clock/MCK (MHz) VDDCORE Consumption (AMP1) 300/150 20 24 0.85 250/125 17 20 1.05 150/150 20 24 0.9 96/96 12.5 15 1.4 96/48 7.5 10 2.5 48/48 7 9.5 2.8 24/24 3.5 5 24/12 2 3 10 12/12 2 3 11.2 8/8 1.5 2 16.8 4/4 1.0 1.5 32.9 4/2 0.9 1 60 4/1 0.8 1 112.
PAGE 1872
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM E70/S70 Figure 59-7. Measurement Setup for Wait Mode AMP2 3.3V VDDIO VDDIN AMP1 Voltage Regulator VDDOUT VDDCORE VDDPLL The following tables give current consumption and wakeup time(1) in Wait mode. Table 59-15. Typical Current Consumption in Wait Mode Typical Value Wait Mode Consumption at 25°C at 85°C at 105°C VDDIO = 3.3V VDDIO = 3.3V VDDIO = 3.
PAGE 1873
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM E70/S70 Figure 59-8. Active Mode Measurement Setup AMP2 3.3V VDDIO VDDIN Voltage Regulator VDDOUT AMP1 VDDCORE VDDPLL The following table gives current consumption in Active mode in typical conditions. Table 59-17. Typical Total Active Power Consumption with VDDCORE at 1.2V Running from Embedded Memory (AMP2) Core Clock/MCK (MHz) Cortex-M7 Running CoreMark Unit Flash Cache Enable (CE) CoreMark = 4.
PAGE 1874
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM E70/S70 ...........continued 59.4.2 Symbol Parameter tSTART Startup Time IDDON Current Consumption Conditions Min. Typ. Max. Unit – – 120 µs – 540 – nA – After startup time 4/8/12 MHz RC Oscillator The 4/8/12 MHz RC oscillator is calibrated in production. This calibration can be read through the Get CALIB bit command (refer to the 22.
PAGE 1875
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM E70/S70 where CPCB is the capacitance of the printed circuit board (PCB) track layout from the crystal to the pin. 59.4.4 32.768 kHz Crystal Characteristics Table 59-21. 32.768 kHz Crystal Characteristics 59.4.5 Symbol Parameter Conditions Min. Typ. Max. Unit ESR Equivalent Series Resistor Crystal at 32.768 kHz – 50 100 kOhm CM Motional Capacitance Crystal at 32.768 kHz 2 – 4 fF CSHUNT Shunt Capacitance Crystal at 32.
PAGE 1876
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM E70/S70 Figure 59-10. 3 to 20 MHz Crystal Oscillator Schematics Microchip MCU CL XOUT XIN R = 1K if crystal frequency is lower than 8 MHz CLEXT CCRYSTAL CLEXT CLEXT = 2 × (CCRYSTAL – CL – CPCB) where, CPCB is the capacitance of the printed circuit board (PCB) track layout from the crystal to the pin. 59.4.7 3 to 20 MHz Crystal Characteristics Table 59-24. 3 to 20 MHz Crystal Characteristics Symbol ESR CM 59.4.
PAGE 1877
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM E70/S70 59.4.9 Crystal Oscillator Design Considerations 59.4.9.1 Choosing a Crystal When choosing a crystal for the 32768 Hz Slow Clock Oscillator or for the 3 MHz–20 MHz oscillator, users need to consider several parameters.
PAGE 1878
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM E70/S70 59.7 USB Transceiver Characteristics The device conforms to all voltage, power, and timing characteristics and specifications as set forth in the USB 2.0 specification. Refer to the USB 2.0 specification for additional information. Table 59-28.
PAGE 1879
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM E70/S70 Figure 59-11. Single-ended Mode AFE Reception module AFE_AD0–5 MX0 AFE DAC0 S/H0 + PGA0 MUX AFE_AD6–11 MX1 S/H1 + - ADC12 12b PGA1 DAC1 Reception module Averager AFE Digital Controller Figure 59-12. Differential Mode AFE Reception module AFE_AD0–1 AFE_AD2–3 AFE_AD4–5 MX0 AFE VREFP/2 S/H0 + PGA0 MUX AFE_AD6–7 AFE_AD8–9 AFE_AD10–11 MX1 S/H1 Reception module + - ADC12 PGA1 VREFP/2 AFE Digital Controller 59.
PAGE 1880
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM E70/S70 Note: 1. Current consumption is measured with AFEC_ACR.IBCTL=10. 2. In Sleep mode, the AFE core, the Sample and Hold and the internal reference operational amplifier are off. 3. In Fast Wake-up mode, only the AFE core is off. 59.8.1.2 ADC Bias Current AFEC_ACR.IBCTL controls the ADC bias current with the nominal setting IBCTL = 10. IBCTL = 10 is the mandatory configuration suitable for a sampling frequency of up to 1 MHz.
PAGE 1881
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM E70/S70 In Differential mode, the Sample-and-Hold common mode voltage is equal to VDAC = VVREFP/2 (set by software DAC0 and DAC1 to code 512). In Single-ended mode, VDAC is the common mode voltage. VDAC is the output of DAC0 or DAC1 voltage. All operations after the Sample-and-Hold are differential, including those in Single-ended mode. For the formula example, the internal DAC0 or DAC1 is set for the code 512.
PAGE 1882
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM E70/S70 • – Gain = 2, LSB = (1.5V / 4096) = 366 μV – Gain = 4, LSB = (750 mV / 4096) = 183 μV Differential (DIFF) (ex: VVREFP = 3.0V) – Gain = 1, LSB = (6.0V / 4096) = 1465 μV – Gain = 2, LSB = (3.0V / 4096) = 732 μV – Gain = 4, LSB = (1.5V / 4096) = 366 μV The data include the AFE performances, as the PGA and AFE core cannot be separated. The temperature and voltage dependency are given as separate parameters. 59.8.4.
PAGE 1883
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM E70/S70 Figure 59-14.
PAGE 1884
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM E70/S70 ...........continued Symbol Parameter Conditions Min. Typ. Gain = 1 INL Integral Non-Linearity Gain = 2 Differential Non-Linearity Unit 12 LSB 6 LSB ±2 -12 ±2.6 Gain = 4 DNL Max. ±2.7 – -6 ±2 Note: INL/DNL given inside the linear range of the AFE: 2% to 98% of VREFP. Table 59-36. AFE Offset and Gain Error, VVREFP = 1.7V to 3.3V Symbol Parameter Conditions Min. Typ(1). Max.
PAGE 1885
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM E70/S70 where: • fS is the sampling frequency of the AFE channel • Typ values are used to compute AFE input impedance ZIN Table 59-37. Input Capacitance (CIN) Values Gain Selection Single-ended Differential Unit 1 2 2 pF 2 4 4 4 8 8 Table 59-38. ZIN Input Impedance fS (MHz) 1 0.5 0.25 0.125 0.0625 0.03125 0.015625 0.007813 0.5 1 2 4 8 16 32 64 0.25 0.5 1 2 4 8 16 32 0.125 0.25 0.
PAGE 1886
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM E70/S70 59.8.6.2 AFE DAC Offset Compensation Table 59-40. DAC Static Performances (see Note 1) Symbol Parameter Conditions Min. Typ. Max. Unit N Resolution (see Note 2) – – 9 10 LSB INL Integral Non Linearity – -2.5 ±0.7 2 LSB DNL Differential Non Linearity – -3 ±0.5 1.8 LSB Note: 1. DAC Offset is included in the AFE EO performances. 2. 10 bits LSB relative to VREFP scale, LSB = VVREFP / 210 = 2.
PAGE 1887
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM E70/S70 ...........continued Symbol Parameter Conditions Min. Typ. Max.
PAGE 1888
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM E70/S70 Table 59-45. Voltage Reference Symbol Parameter Conditions Min. Typ. Max. Unit VVREFP Positive Voltage Reference Externally decoupled 1 µF 1.7 – VDDIN V IVREFP DC Current on VREFP – – 2.5 – µA Note: VREFP is the positive reference shared with AFE and may have a different value for AFE. Refer to the AFE electrical characteristics if AFE is used. The VREFN pin must be connected to ground. Table 59-46.
PAGE 1889
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM E70/S70 Table 59-49. Analog Outputs 59.12 Symbol Parameter Conditions Min. Typ. Max. RLOAD Output Resistor Load Output load resistor 5 – – kOhm CLOAD Output Capacitor Load Output load capacitor – – 50 pF VDACx_MIN Minimum Output Voltage on DACx Code = 0x000 No RLOAD, CLOAD = 50 pF, DACC_ACR.IBCTLCHx =3 – 0.1 0.5 %. VVREFP VDACx_MAX Maximum Output Voltage on DACx Code = 0xFFF No RLOAD CLOAD = 50 pF, DACC_ACR.
PAGE 1890
SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM E70/S70 ...........continued Parameter Conditions Min. Typ. Max. Flash Active Current Random 128-bit read at maximum frequency at 25°C on VDDCORE =1.2V – 16 20 on VDDIO – 2 10 Program at 25°C on VDDCORE =1.2V – 2 3 on VDDIO – 8 12 on VDDCORE =1.2V – 2 2 on VDDIO – 8 12 Erase at 25°C Unit mA Note: 1. Cycling over full temperature range.
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SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM E70/S70 • • • Output duty cycle (40%-60%) Minimum output swing: 100 mV to VDDIO - 100 mV Addition of rising and falling time inferior to 75% of the period Table 59-54. I/O Characteristics Symbol FreqMax1 Parameter Conditions Pin Group 1 (1) Maximum output frequency PulseminL1 Pin Group 1 Low Level Pulse Width FreqMax2 Pin Group 2 (3)Maximum output frequency MHz Drive Level 10 pF 1.
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SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM E70/S70 59.13.1.5 QSPI Characteristics Figure 59-17. QSPI Master Mode with (CPOL= NCPHA = 0) or (CPOL= NCPHA= 1) QSCK QSPI0 QSPI1 QIOx_DIN QSPI2 QIOx_DOUT Figure 59-18. QSPI Master Mode with (CPOL = 0 and NCPHA=1) or (CPOL=1 and NCPHA= 0) QSCK QSPI3 QSPI4 QIOx_DIN QSPI5 QIOx_DOUT 59.13.1.5.1 Maximum QSPI Frequency The following sections provide maximum QSPI frequency in master read and write modes.
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SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM E70/S70 ...........continued Symbol Parameter Conditions Min Max Unit QSPI1 QIOx data in to QSCK rising edge (input hold time) 3.3V domain 0 – ns 1.8V domain 0 – ns 3.3V domain -1.3 1.9 ns 1.8V domain -2.5 3.0 ns 3.3V domain 2.9 – ns 1.8V domain 3.2 – ns 3.3V domain 0 – ns 1.8V domain 0 – ns 3.3V domain -1.6 1.8 ns 1.8V domain -2.7 3.
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SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM E70/S70 Figure 59-21. SPI Master Mode with (CPOL = 0 and NCPHA=1) or (CPOL=1 and NCPHA= 0) SPCK SPI4 SPI3 MISO SPI5 MOSI Figure 59-22. SPI Slave Mode with (CPOL=0 and NCPHA=1) or (CPOL=1 and NCPHA=0) NPCSS SPI13 SPI12 SPCK SPI6 MISO SPI7 SPI8 MOSI Figure 59-23. SPI Slave Mode with (CPOL = NCPHA = 0) or (CPOL= NCPHA= 1) NPCS0 SPI15 SPI14 SPCK SPI9 MISO SPI10 SPI11 MOSI 59.13.1.6.
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SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM E70/S70 Master Write Mode The SPI sends data to a slave device only, for example, an LCD. The limit is given by SPI2 (or SPI5) timing because it gives a maximum frequency above the maximum pad speed, refer to I/O Characteristics), the max SPI frequency is the one from the pad. Master Read Mode �SPCKmax = 1 SPI0 or SPI3 + �valid tvalid is the slave time response to output data after detecting an SPCK edge.
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SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM E70/S70 ...........continued Symbol Parameter Conditions Min Max Unit SPI9 SPCK rising to MISO Delay (slave) 3.3V domain 3.0 12.0 ns 1.8V domain 3.4 13.7 ns 3.3V domain 1.2 – ns 1.8V domain 1.5 – ns 3.3V domain 0.6 – ns 1.8V domain 0.8 – ns 3.3V domain 3.9 – ns 1.8V domain 4.4 – ns 3.3V domain 0 – ns 1.8V domain 0 – ns 3.3V domain 4.0 – ns 1.8V domain 4.1 – ns 3.3V domain 0 – ns 1.
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SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM E70/S70 ...........continued Symbol VDDIO Supply 1.8V Domain 3.3V Domain 1.8V Domain 3.3V Domain Unit Parameter Min Max SMC3 Data Setup before NRD High 15.2 12.1 – – ns SMC4 Data Hold after NRD High 0 0 – – ns HOLD or NO HOLD Settings (NRD_HOLD ≠ 0, NRD_HOLD = 0) SMC5 A0–A22 Valid before NRD High (NRD_SETUP + (NRD_SETUP + – NRD_PULSE) × tCPMCK - NRD_PULSE) × tCPMCK 5.1 4.
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SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM E70/S70 59.13.1.9.2 Write Timings Table 59-59. SMC Write Signals - NWE Controlled (WRITE_MODE = 1) Symbol VDDIO Supply Parameter 1.8V Domain 3.3V Domain Min 1.8V Domain 3.3V Domain Unit Max HOLD or NO HOLD Settings (NWE_HOLD ≠ 0, NWE_HOLD = 0) SMC15 Data Out Valid before NWE High NWE_PULSE × tCPMCK - NWE_PULSE × tCPMCK - – 5.4 4.6 – ns SMC16 NWE Pulse Width NWE_PULSE × tCPMCK - NWE_PULSE × tCPMCK - – 0.7 0.
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SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM E70/S70 Note: Hold length = total cycle duration - setup duration - pulse duration. “hold length” is for “NCS_WR_HOLD length” or “NWE_HOLD length” Table 59-60. SMC Write NCS Controlled (WRITE_MODE = 0) Symbol VDDIO Supply 1.8V Domain 3.3V Domain 1.8V Domain 3.3V Domain Unit Parameter Min Max SMC22 Data Out Valid before NCS High NCS_WR_PULSE × tCPMCK - 2.8 NCS_WR_PULSE × tCPMCK - 3.
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SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM E70/S70 Figure 59-25. USART SPI Slave Mode (Mode 1 or 2) • The MOSI line drives the input pin RXD • The MISO line is driven by the output pin TXD • The SCK line drives the input pin SCK • The NSS line drives the input pin CTS NSS SPI13 SPI12 SCK SPI6 MISO SPI7 SPI8 MOSI Figure 59-26. USART SPI Slave Mode (Mode 0 or 3) NSS SPI14 SPI15 SCK SPI9 MISO SPI10 SPI11 MOSI 59.13.1.11.
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SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM E70/S70 ...........continued Symbol Parameter SPI2 Input Data Hold Time SPI3 Chip Select Active to Serial Clock SPI4 Output Data Setup Time SPI5 Serial Clock to Chip Select Inactive Conditions Min Max 1.7V domain 0.5 – 3.3V domain 0.2 – 1.7V domain -1.1 – 3.3V domain -0.9 – 1.7V domain -1.9 10.9 3.3V domain -1.9 10.4 1.7V domain -2.4 -1.9 3.3V domain -2.4 -1.9 1.7V domain 3.6 16.8 3.3V domain 2.9 13.9 1.
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SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM E70/S70 Table 59-62. Two-wire Serial Bus Requirements Symbol Parameter Condition Min. Max. Unit VIL Low-level Input Voltage – -0.3 0.3 VDDIO V VIH High-level Input Voltage – 0.7 × VDDIO VCC + 0.3 V Vhys Hysteresis of Schmitt Trigger Inputs – 0.150 – V VOL Low-level Output Voltage 3 mA sink current – 0.4 V tR Rise Time for both TWD and TWCK 20 + 0.
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SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM E70/S70 Figure 59-27. Two-wire Serial Bus Timing tHIGH tof tLOW tr tLOW TWCK tSU;STA tHD;STA tHD;DAT tSU;DAT tSU;STO TWD tBUF 59.13.1.13 GMAC Characteristics 59.13.1.13.1 Timing Conditions Table 59-63. Load Capacitance on Data, Clock Pads Supply CL 3.3V Max. Min. 20 pF 0 pF 59.13.1.13.2 Timing Constraints The GMAC must be constrained so as to satisfy the timings of standards shown below and in 58.13.1.13.
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SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM E70/S70 59.13.1.13.3 MII Mode Table 59-65.
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SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM E70/S70 Figure 59-29. GMAC MII Mode Signals EMDC GMAC1 GMAC3 GMAC2 EMDIO GMAC4 GMAC5 GMAC6 GMAC7 ECOL ECRS ETXCK GMAC8 ETXER GMAC9 ETXEN GMAC10 ETX[3:0] ERXCK GMAC11 GMAC12 ERX[3:0] GMAC13 GMAC14 GMAC15 GMAC16 ERXER ERXDV 59.13.1.13.4 RMII Mode Table 59-66.
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SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM E70/S70 Figure 59-30. GMAC RMII Mode Signals EREFCK GMAC21 ETXEN GMAC22 ETX[1:0] GMAC23 GMAC24 ERX[1:0] GMAC25 GMAC26 GMAC27 GMAC28 ERXER ECRSDV 59.13.1.14 SSC Timings 59.13.1.14.1 Timing Conditions Timings are given assuming the load capacitance as shown in the following table. Table 59-67. Load Capacitance Supply CL Max. 3.3V 30 pF 59.13.1.14.2 Timing Extraction Figure 59-31.
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SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM E70/S70 Figure 59-33. SSC Transmitter, TK in Output and TF in Input TK (CKI=0) TK (CKI=1) SSC2 SSC3 TF SSC4 TD Figure 59-34. SSC Transmitter, TK and TF in Input TK (CKI=0) TK (CKI=1) SSC5 SSC6 TF SSC7 TD Figure 59-35. SSC Receiver RK and RF in Input RK (CKI=0) RK (CKI=1) SSC8 SSC9 RF/RD Figure 59-36. SSC Receiver, RK in Input and RF in Output RK (CKI=0) RK (CKI=1) SSC8 SSC9 RD SSC10 RF © 2019 Microchip Technology Inc.
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SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM E70/S70 Figure 59-37. SSC Receiver, RK and RF in Output RK (CKI=0) RK (CKI=1) SSC11 SSC12 RD SSC13 RF Figure 59-38. SSC Receiver, RK in Output and RF in Input RK (CKI=0) RK (CKI=1) SSC11 SSC12 RF/RD Table 59-68. SSC Timings with 3.3V Peripheral Supply Symbol Parameter Condition Min. Max. Unit Transmitter SSC0 TK edge to TF/TD (TK output, TF output) – -3.9(1) 4.0 (1) ns SSC1 TK edge to TF/TD (TK input, TF output) – 3.
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SAM E70/S70/V70/V71 Family Electrical Characteristics for SAM E70/S70 ...........continued Symbol Parameter SSC12 SSC13 Condition RF/RD hold time after RK edge (RK output) – RK edge to RF (RK output) – Min. Max. Unit tCPMCK - 2.8 – ns -2.1(1) 1.9(1) ns Note: For output signals (TF, TD, RF), minimum and maximum access times are defined. The minimum access time is the time between the TK (or RK) edge and the signal change.
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SAM E70/S70/V70/V71 Family Schematic Checklist 60. Schematic Checklist The schematic checklist provides the user with the requirements regarding the different pin connections that must be considered before starting any new board design. It also provides information on the minimum hardware resources required to quickly develop an application with the SAM E70/S70/V70/V71 device. It does not consider PCB layout constraints. This information is not intended to be exhaustive.
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SAM E70/S70/V70/V71 Family Schematic Checklist Check Signal Name Recommended Pin Connection VDDIN VDDIO Decoupling/filtering capacitors (100 nF and 4.7 μF)(1)(2) Decoupling/filtering capacitors (100 nF)(1)(2) Description Powers the voltage regulator, AFE, DAC, and Analog comparator power supply Supply ripple must not exceed 20 mVrms for 10 kHz to 20 MHz range. WARNING VDDIN and VDDIO must have the same level and must be higher than VDDCORE.
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SAM E70/S70/V70/V71 Family Schematic Checklist ...........continued Check Signal Name Recommended Pin Connection VDDCORE Decoupling capacitor (100 nF)(1)(2) Description Powers the core, embedded memories and peripherals. Decoupling/filtering capacitors must be added to improve startup stability and reduce source voltage drop. WARNING Powerup and powerdown sequences given in the “Power Considerations” chapter must be respected.
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SAM E70/S70/V70/V71 Family Schematic Checklist 60.1.2 Supplying the Device With Two Separate Supplies CAUTION The board design must comply with power-up and power-down sequence guidelines provided in the “Power Considerations” chapter. Power Supplies Schematic Example With Separate Power Supplies 60.3 Boot Program Hardware Constraints VDDUTMII 100nF GNDUTMI 2.2R 10μH - 60mA VDDPLLUSB 4.7μF GNDPLLUSB VDDIO 5 x 100nF GND VDDIN MAIN SUPPLY 4.
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SAM E70/S70/V70/V71 Family Schematic Checklist Signal Name Recommended Pin Connection Description VDDIN Powers the voltage regulator, AFE, DAC, and Analog comparator power supply Supply ripple must not exceed 20 mVrms for 10 kHz to 20 MHz range. VDDIO Decoupling/filtering capacitors (100 nF and 4.7 μF) (1, 2) Decoupling/filtering capacitors (100 nF) (1, 2) WARNING VDDIN and VDDIO must have the same level and must always be higher than VDDCORE.
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SAM E70/S70/V70/V71 Family Schematic Checklist ...........continued Signal Name Recommended Pin Connection Description VDDCORE Powers the core, embedded memories and peripherals. Decoupling/filtering capacitors must be added to improve startup stability and reduce source voltage drop. Decoupling capacitor (100 nF) (1) (2) Supply ripple must not exceed 20 mVrms for 10 kHz to 20 MHz range.
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SAM E70/S70/V70/V71 Family Schematic Checklist 100nF VDDCORE 100nF VDDCORE 100nF VDDCORE GND 60.2 General Hardware Recommendations 60.2.1 Crystal Oscillators Signal Name Recommended Pin Connection Description XIN XOUT Crystals between 3 and 20 MHz USB High/Full Speed Host/Device peripherals require a 12 or 16 MHz clock. Crystal Load Capacitance to check (CCRYSTAL).
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SAM E70/S70/V70/V71 Family Schematic Checklist ...........continued Signal Name Recommended Pin Connection Description XIN32 XOUT32 32.768 kHz Crystal Capacitors on XIN32 and XOUT32 Crystal load capacitance to check (CCRYSTAL32). Slow Clock Oscillator (Crystal Load Capacitance dependent) Microchip MCU XIN32 XOUT32 GND C CRYSTAL32 CLEXT32 CLEXT32 Example: for a 32.768 kHz crystal with a load capacitance of CCRYSTAL32 = 7 pF, external capacitors are required: CLEXT32 = 11 pF. Refer to 58.
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SAM E70/S70/V70/V71 Family Schematic Checklist ...........continued Signal Name Recommended Pin Connection Description TDI Floating. If boundary mode is not required, this pin can be used as GPIO. Test Data In (Boundary scan mode only) This pin is a Schmitt trigger input. TRACESWO/TD O Floating. If boundary mode is not required, this pin can be used as GPIO.
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SAM E70/S70/V70/V71 Family Schematic Checklist 60.2.4 Reset and Test Pins Signal Name Recommended Pin Connection Description NRST Application dependent. Can be connected to a push button for hardware reset. NRST is a bidirectional pin (Schmitt trigger input). It is handled by the on-chip reset controller and can be driven low to provide a reset signal to the external components or asserted low externally to reset the microcontroller.
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SAM E70/S70/V70/V71 Family Schematic Checklist 60.2.7 Analog Reference, Analog Front-End and DAC Signal Name Recommended Pin Connection Description Analog Voltage References VREFP 1.7V to VDDIN LC Filter is required. Positive reference voltage. VREFP is a pure analog input. VREFP is the voltage reference for the AFEC (ADC, PGA DAC and Analog Comparator). To reduce power consumption, if analog features are not used, connect VREFP to GND.
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SAM E70/S70/V70/V71 Family Schematic Checklist Note: 1. The following schematic shows an example of USB High Speed host connection. For more information, refer to 39. USB High-Speed Interface (USBHS) PIO (VBUS ENABLE) "A" Receptacle 1 = VBUS 2 = D3 = D+ 4 = GND +5V HSDM 3 4 Shell = Shield 1 2 HSDP 5K62 ± 1% VBG 10 pF GNDUTMI 2. The following schematic shows a typical USB High Speed device connection: For more information, refer to 39. USB High-Speed Interface (USBHS).
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SAM E70/S70/V70/V71 Family Schematic Checklist ...........continued Signal Name Recommended Pin Connection Description Static Memory Controller NCS0-NCS3 Application dependent. (Pullup at VDDIO) Chip Select Lines All are pulled-up inputs (100 kOhm) to VDDIO at reset. NRD Application dependent. Read Signal Pulled-up input (100 kOhm) to VDDIO at reset. NWE Application dependent. Write Enable All are pulled-up inputs (100 kOhm) to VDDIO at reset. NWR0–NWR1 Application dependent.
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1 2 rotatethispage90 3 4 5 6 ATSAME70Q21B-ANT U400 PA20 BA0 R459 22R 22R 22R B PE00 PE01 PE02 PE03 PE04 PE05 R476 R477 R478 R479 R480 R481 D8 D9 D10 D11 D12 D13 C 22R 22R 22R 22R 22R 22R 4 6 7 10 27 28 PB00 PB01 PB02 PB03 PB04 PB05 PB06 PB07 PB08 PB09 PB12 PB13 PD00 PD01 PD02 PD03 PD04 PD05 PD06 PD07 PD08 PD09 PD10 PD11 PD12 PD13 PD14 PD15 PD16 PD17 PD18 PD19 PD20 PD21 PD22 PD23 PD24 PD25 PD26 PD27 PD28 PD29 PD30 PD31 PE00 PE01 PE02 PE03 PE04 PE05 137 HSDP 136 HSDM 83 NRST 85 TST 104
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SAM E70/S70/V70/V71 Family Schematic Checklist Figure 60-4. Schematic Example with a 2 Gb/8-bit NAND Flash VDDIO VDDIO NFC RE WE CE NFC CLE ALE R/B PC9 R 47k R 47k NAND FLASH NANDOE PC10 NANDWE WE PC12 NCS3/NANDCS (or Any PIO) CE PC17 NANDCLE CLE PC16 NANDALE Pxx ALE (Any PIO) EBI D7 D6 D5 D4 D3 D2 D1 D0 I/O-7 I/O-6 I/O-5 I/O-4 I/O-3 I/O-2 I/O-1 I/O-0 RE PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 D7 D6 D5 D4 D3 D2 D1 D0 EBI VDDIO R/B VCC VCC WP C 100n NC0 NC1 NC2 NC3 NC4 .... ....
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SAM E70/S70/V70/V71 Family Schematic Checklist Figure 60-6. Schematic Example with QSPI Data Flash VDDIO QSPI QSPI IO0 IO1 IO2 IO3 CLK CS PA13 PA12 PA17 PD31 PA14 PA11 5 2 3 7 6 1 QIO0 QIO1 QIO2 QIO3 QSCK QCS R605 100k VDDIO SI/IO0 VCC SO/IO1 W P/IO2 HOLD/IO3 SCK VSS CS PAD (NC) 8 C 100n 4 0 PAD GND 60.2.12 Other Interfaces Signal Name Recommended Pin Connection Description Universal Synchronous Asynchronous Receiver Transmitter SCKx Application dependent.
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SAM E70/S70/V70/V71 Family Schematic Checklist ...........continued Signal Name Recommended Pin Connection Description TF Application dependent. SSC Transmit Frame Sync Pulled-up input (100 kOhm) to VDDIO at reset. RF Application dependent. SSC Receive Frame Sync Pulled-up input (100 kOhm) to VDDIO at reset. Image Sensor Interface ISI_D0–ISI_D11 Application dependent. Image Sensor Data (Signal can be level-shifted Pulled-up inputs (100 kOhm) to VDDIO at reset.
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SAM E70/S70/V70/V71 Family Schematic Checklist ...........continued Signal Name Recommended Pin Connection PWMC0_PWMEXTRG0 Application dependent. PWMC0_PWMEXTRG1 Description External Trigger Inputs Pulled-up inputs (100 kOhm) to VDDIO at reset. PWMC1_PWMEXTRG0 PWMC1_PWMEXTRG1 Serial Peripheral Interface SPIx_MISO Application dependent. Master In Slave Out Pulled-up inputs (100 kOhm) to VDDIO at reset. SPIx_MOSI Application dependent.
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SAM E70/S70/V70/V71 Family Schematic Checklist 60.3.1 Boot Program Supported Crystals (MHz) A 12 MHz or a 16 MHz crystal or external clock (in Bypass mode) is mandatory in order to generate USB and PLL clocks correctly for the following boots. 60.3.
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SAM E70/S70/V70/V71 Family Marking 61. Marking All devices are marked with the Atmel logo and the ordering code. Additional marking is as follows: YYWW V XXXXXXXXX ARM where, • • • • “YY”: Manufacturing year “WW”: Manufacturing week “V”: Revision “XXXXXXXXX”: Lot number © 2019 Microchip Technology Inc.
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SAM E70/S70/V70/V71 Family Packaging Information 62. Packaging Information 62.1 LQFP144, 144-lead LQFP LQFP144, 144-lead LQFP, 20x20 mm, pitch 0.5 mm © 2019 Microchip Technology Inc.
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SAM E70/S70/V70/V71 Family Packaging Information Table 62-1. Device and LQFP Package Maximum Weight 1365 mg Table 62-2. LQFP Package Reference JEDEC Drawing Reference JEDEC J-STD-609 Classification e3 Table 62-3. LQFP Package Characteristics Moisture Sensitivity Level 3 This package respects the recommendations of the NEMI user group. For up-to-date packaging information, visit www.microchip.com/packaging. 62.2 LFBGA144, 144-ball LFBGA LFBGA144, 144-ball LFBGA, 10x10 mm, pitch 0.
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SAM E70/S70/V70/V71 Family Packaging Information Table 62-4. Device and LFBGA Package Maximum Weight 220 mg Table 62-5. LFBGA Package Reference JEDEC Drawing Reference JEDEC JESD97 Classification e8 Table 62-6. LFBGA Package Characteristics Moisture Sensitivity Level 3 This package respects the recommendations of the NEMI user group. For up-to-date packaging information, visit www.microchip.com/packaging. © 2019 Microchip Technology Inc.
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SAM E70/S70/V70/V71 Family Packaging Information 62.3 TFBGA144, 144-ball TFBGA TFBGA144, 144-ball TFBGA, 10x10mm, pitch 0.8 mm TOP VIEW lclddd le� -=-11- � I//I bbb le PIN A1 CORNER \ 1 I � 0 3 4 5 7 6 8 9 10 11 12 EB 00000000000 -EB 00000000000 [d 0 2 000000000000 000000000000 000000000000 000000000000 000000000000 000000000000 000000000000 000000000000 000000000000 000000000 $ T. � � E1 Al lcl aaa(4X) '- T.
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SAM E70/S70/V70/V71 Family Packaging Information Table 62-7. Device and TFBGA Package Maximum Weight 220 mg Table 62-8. TFBGA Package Reference JEDEC Drawing Reference JEDEC J-STD-609 Classification e8 Table 62-9. TFBGA Package Characteristics Moisture Sensitivity Level 3 This package respects the recommendations of the NEMI user group. For up-to-date packaging information, visit www.microchip.com/packaging. © 2019 Microchip Technology Inc.
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SAM E70/S70/V70/V71 Family Packaging Information 62.4 UFBGA144, 144-ball UFBGA UFBGA144, 144-ball UFBGA, 6x6 mm, pitch 0.4 mm Table 62-10. Device and UFBGA Package Maximum Weight 36.300 © 2019 Microchip Technology Inc.
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SAM E70/S70/V70/V71 Family Packaging Information Table 62-11. UFBGA Package Reference JEDEC Drawing Reference JEDEC JESD97 Classification e8 Table 62-12. UFBGA Package Characteristics Moisture Sensitivity Level 3 This package respects the recommendations of the NEMI user group. For up-to-date packaging information, visit www.microchip.com/packaging. © 2019 Microchip Technology Inc.
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SAM E70/S70/V70/V71 Family Packaging Information 62.5 LQFP100, 100-lead LQFP LQFP100, 100-lead LQFP, 14x14 mm, pitch 0.5 mm Table 62-13. Device and LQFP Package Maximum Weight 680 mg Table 62-14. LQFP Package Reference JEDEC Drawing Reference JEDEC J-STD-609 Classification e3 Table 62-15. LQFP Package Characteristics Moisture Sensitivity Level 3 This package respects the recommendations of the NEMI user group. For up-to-date packaging information, visit www.microchip.com/packaging.
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SAM E70/S70/V70/V71 Family Packaging Information 62.6 TFBGA100, 100-ball TFBGA TFBGA100, 100-ball TFBGA, 9x9 mm, pitch 0.8 mm BOTTOM VIEW TOP VIEW A1 CORNER 1 2 3 4 5 6 A1 CORNER @C T 910.15 @ C A B ____l'.6__ 7 8 9 10 10 A 910.08 910.35~910.
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SAM E70/S70/V70/V71 Family Packaging Information Table 62-18. TFBGA Package Characteristics Moisture Sensitivity Level 3 This package respects the recommendations of the NEMI user group. For up-to-date packaging information, visit www.microchip.com/packaging. © 2019 Microchip Technology Inc.
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SAM E70/S70/V70/V71 Family Packaging Information 62.7 VFBGA100, 100-ball VFBGA VFBGA100, 100-ball VFBGA, 7x7 mm, pitch 0.65 mm Table 62-19. Device and VFBGA Package Maximum Weight 76 © 2019 Microchip Technology Inc.
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SAM E70/S70/V70/V71 Family Packaging Information Table 62-20. VFBGA Package Reference JEDEC Drawing Reference JEDEC JESD97 Classification e8 Table 62-21. VFBGA Package Characteristics Moisture Sensitivity Level 3 This package respects the recommendations of the NEMI user group. For up-to-date packaging information, visit www.microchip.com/packaging. 62.8 LQFP64, 64-lead LQFP LQFP64, 64-lead LQFP, 10x10 mm, pitch 0.5 mm Table 62-22.
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SAM E70/S70/V70/V71 Family Packaging Information Table 62-23. LQFP Package Reference JEDEC Drawing Reference JEDEC J-STD-609 Classification e3 Table 62-24. LQFP Package Characteristics Moisture Sensitivity Level 3 This package respects the recommendations of the NEMI user group. For up-to-date packaging information, visit www.microchip.com/packaging. 62.9 QFN64, 64-pad QFN QFN64, 64-pad QFN 9x9 mm, pitch 0.
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SAM E70/S70/V70/V71 Family Packaging Information Table 62-27. QFN Package Characteristics Moisture Sensitivity Level 1 This package respects the recommendations of the NEMI user group. For up-to-date packaging information, visit www.microchip.com/packaging. 62.10 Soldering Profile The following table provides the recommended soldering profile from J-STD-020C. Table 62-28. Soldering Profile Profile Feature Green Package Average Ramp-Up Rate (217°C to Peak) 3°C/sec. max.
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SAM E70/S70/V70/V71 Family Revision History 63. Revision History Table 63-1. Rev. D - 02/2019 Section Name or Type Update Description Signal Description Updated the Signal Description List. Input/Output Lines Updated text in ERASE Pin. Memories Updated text in Embedded Flash Overview. Peripherals Updated the table Peripheral Identifiers.
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SAM E70/S70/V70/V71 Family Revision History Table 63-2. Rev. C - 10/2018 Section Name or Type Update Description General Updates • • • Package Drawings PMC - Added missing PCKRDY7, which is missing in the PMC_IER, PMC_IDR and PMC_SR registers. MCAN - Changed reset value for the MCAN_CREL register. AFE - Changed CHNB bit field offset in the AFEC_LCDR register Added the following package mechanical drawings: • LQFP144, 144-lead LQFP, 20x20 mm, pitch 0.5 mm • LFBGA144, 144-ball LFBGA, 10x10 mm, pitch 0.
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SAM E70/S70/V70/V71 Family Revision History ...........continued Date Changes Restructured Section 1. ”Description”. Table 2-1 “Configuration Summary” : Added Note (3) on USART/UART functionality. Reorganized table notes. Table 6-3 “64-lead LQFP Package Pinout” : deleted signal names for pins 50, 51, 53 and 54 for PIO Peripheral D. (now unassigned) Table 14-1 “Peripheral Identifiers” : TWIHS0/1 instances read now as I2C-compatible. Section 15.
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SAM E70/S70/V70/V71 Family Revision History ...........continued Date Changes Section 34. ”SDRAM Controller (SDRAMC)” Section 34.7.3 ”SDRAMC Configuration Register”: in TWO_CS description, added “This feature is not supported when SDR-SDRAM device embeds two internal banks.” Updated description tables for NC and NR fields. Section 36.
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SAM E70/S70/V70/V71 Family Revision History ...........continued Date Changes - Added new instruction: “Read QSPI_SR (dummy read) to clear QSPI_SR.INSTRE and QSPI_SR.CSR“. Updated Figure 42-8 “Instruction Frame”, Figure 42-10 “Continuous Read Mode”, Figure 42-16 “Instruction Transmission Waveform 6”, Figure 42-17 “Instruction Transmission Waveform 7” and Figure 42-19 “Instruction Transmission Waveform 9”. Section 46. ”Universal Synchronous Asynchronous Receiver Transceiver (USART)” Section 46.
PAGE 1950
SAM E70/S70/V70/V71 Family Revision History ...........continued Date Changes Section 52.7.2 ”AFEC Mode Register”: updated TRACKTIM description. Section 53. ”Digital-to-Analog Converter Controller (DACC)” Table 53-1 “DACC Signal Description” : corrected pin names to VREFP and VREFN (were ADVREFP and ADVREFN). Section 54. ”Analog Comparator Controller (ACC)” Table 54-1 “ACC Signal Description” : modified Description for DAC0, DAC1 signals. Section 54.7.
PAGE 1951
SAM E70/S70/V70/V71 Family Revision History Table 63-6. SAM E70/S70/V70/V71 Datasheet Rev. 44003D – Revision History Date Comments 01-June-16 “Introduction” AFE maximum sampling frequency now 1.7 Msps. “Features” Main RC oscillator default frequency changed to 12 MHz. AFE maximum sampling frequency now 1.7 Msps. Section 2. “Configuration Summary” Table 2-1 “Configuration Summary”: on QFN64 package, HS USB now supported.
PAGE 1952
SAM E70/S70/V70/V71 Family Revision History ...........continued Date Comments Section 24.5.1 “Watchdog Timer Control Register”: LOCKMR bit now at index 4 (was ‘reserved’). Section 24.5.2 “Watchdog Timer Mode Register”: modified access and updated Note (1). Section 25. “Reinforced Safety Watchdog Timer (RSWDT)” Updated Figure 25-1 “Reinforced Safety Watchdog Timer Block Diagram”. Section 26. “Reset Controller (RSTC)” ‘Slow crystal’ changed to ‘32.768 kHz’ throughout.
PAGE 1953
SAM E70/S70/V70/V71 Family Revision History ...........continued Date Comments Section 31.5.2 “Main RC Oscillator Frequency Adjustment”: updated 1st and last paragraphs. Deleted some redundant content. Section 31.5.3 “Main Crystal Oscillator”: updated information on programming startup time. Section 31.5.4 “Main Clock Source Selection”: updated list of selectable main clock sources. Section 31.5.6 “Main Frequency Counter” renamed section (was “Main Clock Frequency Counter”). Updated 1st paragraph.
PAGE 1954
SAM E70/S70/V70/V71 Family Revision History ...........continued Date Comments Section 37. “Image Sensor Interface (ISI)” Updated “12-bit Grayscale Mode” . Section 37.6.1 “ISI Configuration 1 Register”: added bit GRAYLE at index 5 and bit description. Section 37.6.12 “ISI Interrupt Enable Register”, Section 37.6.13 “ISI Interrupt Disable Register”: changed access from “Read/Write” to “Write-only”. Section 37.6.14 “ISI Interrupt Mask Register”: changed access from “Read/Write” to “Read-only”. Section 38.
PAGE 1955
SAM E70/S70/V70/V71 Family Revision History ...........continued Date Comments Section 41. “Serial Peripheral Interface (SPI)” Modified transmission condition description in Section 41.7.3 “Master Mode Operations”. Removed TXFCLR, RXFCLR, FIFOEN and FIFODIS bits in Section 41.8.1 “SPI Control Register”. cont’d 01-June-16 Section 42. “Quad SPI Interface (QSPI)” Section 42.2 “Embedded Characteristics”: added bullet on Single Data Rate and Double Data Rate modes. Figure 42-2 “QSPI Transfer Format (QSPI_SCR.
PAGE 1956
SAM E70/S70/V70/V71 Family Revision History ...........continued Date Comments Section 46. “Universal Synchronous Asynchronous Receiver Transceiver (USART)” Section 46.2 “Embedded Characteristics”: added bullet “Optimal for Node-to-Node Communication (no embedded digital line filter)” to LON Mode features. Section 46.6.3.11 “Receiver Timeout”: deleted redundant paragraphs on STTTO and RETTO. Section 46.6.4 “ISO7816 Mode”: corrected USART_MODE value for prototcol T = 1. Section 46.6.
PAGE 1957
SAM E70/S70/V70/V71 Family Revision History ...........continued Date Comments 01-June-16 Section 52. “Analog Front-End Controller (AFEC)” Section 52.2 “Embedded Characteristics”: deleted bullet on conversion rate (redundant with Electrical Characteristics) Section 52.6.1 “Analog Front-End Conversion”: updated and changed clock frequency range. Updated formula to calculate AFE conversion time. Section 52.6.3 “Conversion Resolution”: added Note. Section 52.6.
PAGE 1958
SAM E70/S70/V70/V71 Family Revision History ...........continued Date Comments Section 63. “Errata” Added - Section 63.1.1 “AFE Controller (AFEC)”: “AFE max sampling frequency is 1.74 Msps” and “Changing AFEC_COCR.AOFF during conversions is not safe” . - Section 63.1.5 “Boundary Scan Mode”: “Boundary Scan Mode” - Section 63.1.8 “Ethernet MAC (GMAC)”: “Error in number of queues” - Section 63.1.10 “Master CAN-FD Controller (MCAN)”: “Timestamping issue with external clock” - Section 63.1.
PAGE 1959
SAM E70/S70/V70/V71 Family Revision History ...........continued Date Changes Section 7. “Power Considerations” Updated Table 7-1 “Power Supplies”. Section 7.2 ”Power Constraints”: removed bullet on USB. Section 7.2.1 ”Power-up”: added constraint regarding overcurrent. Section 7.2.2 ”Power-down”: added constraint regarding overcurrent. Updated Table 7-2 “Low-power Mode Configuration Summary”. Section 8. “Input/Output Lines” Removed redundant Section 6.3. TST Pin (already in Section 16.
PAGE 1960
SAM E70/S70/V70/V71 Family Revision History ...........continued Date Changes Section 22. “Enhanced Embedded Flash Controller (EEFC)” Updated Section 22.2 “Embedded Characteristics”. Added Figure 22-1, “Flash Memory Areas”. Section 22.4.3.6 “Calibration Bit”: updated oscillators that are calibrated in production. Section 22.4.3.7 “Security Bit Protection”: added detail on ETM. Section 23.
PAGE 1961
SAM E70/S70/V70/V71 Family Revision History ...........continued Date Changes Updated Section 31.5.6 “Main Clock Frequency Counter”. Updated Section 31.5.7 “Switching Main Clock between the RC Oscillator and Crystal Oscillator”. Updated Section 31.6.1 “Divider and Phase Lock Loop Programming” with paragraph on correct programming of the multiplication factor of the PLL. Section 31.7 ”UTMI Phase Lock Loop Programming”: deleted sentence on crystal requirements for USB. Section 32.
PAGE 1962
SAM E70/S70/V70/V71 Family Revision History ...........continued Date Changes 08-Feb-16 Section 35. “Static Memory Controller (SMC)” Section 35.7.3 “NAND Flash Support”: removed reference to NCS3. Updated Figure 35-5, “NAND Flash Signal Multiplexing on SMC Pins” and added Note 1 below the figure. Section 35.10 “Scrambling/Unscrambling Function”: added details on access for SMC_KEY1 and SMC_KEY2 registers.
PAGE 1963
SAM E70/S70/V70/V71 Family Revision History ...........continued Date Changes Section 38. “USB High-Speed Interface (USBHS)” Table 38-1 “Description of USB Pipes/Endpoints”: corrected value in ‘High Bandwidth’ column for Pipe/ Endpoint 1. Added Section 38.4.1 “I/O Lines”. Updated Figure 38-2, “General States”. Updated Section 38.5.3.3 “Device Detection” and added Note on VBUS supply. Section 38.6.1 “General Control Register”: added bit 8, VBUSHWC. Section 38.6.
PAGE 1964
SAM E70/S70/V70/V71 Family Revision History ...........continued Date Changes Section 42. “Quad SPI Interface (QSPI)” Section 42.7.2 “QSPI Mode Register”: updated equations and NBBITS description. Section 42.7.5 “QSPI Status Register”: updated RDRF, TDRE, TXEMPTY, and OVRES field descriptions. Section 42.7.9 “QSPI Serial Clock Register”: updated equations. Section 42.7.12 “QSPI Instruction Frame Register”: updated INSTEN bit description. Section 43. “Two-wire Interface (TWIHS)” Section 43.6.3.
PAGE 1965
SAM E70/S70/V70/V71 Family Revision History ...........continued Date Changes Section 46.7.17 “USART Channel Status Register”: added bits ITER, NACK, RIIC, DSRIC, DCDIC, DSR, and DCD. Section 46.7.23 “USART Baud Rate Generator Register”: updated CD field description. Added Section 46.7.27 “USART FI DI RATIO Register” and Section 46.7.29 “USART Number of Errors Register”. Section 49. “Controller Area Network (MCAN)” Replaced ‘HCLK’ and ‘m_can_hclk’ by ‘peripheral clock’.
PAGE 1966
SAM E70/S70/V70/V71 Family Revision History ...........continued Date Changes Section 52. “Analog Front-End Controller (AFEC)” Updated Section 52.6 “Functional Description”. Section 52.6.11 “Input Gain and Offset” changed AOFF configuration value. Corrected formula for offset values. Updated Section 52.6.12 “AFE Timings”. Section 52.6.18 “Register Write Protection”: added “AFEC Channel Differential Register” to the list of write-protected registers. Section 52.7.
PAGE 1967
SAM E70/S70/V70/V71 Family Revision History ...........continued Date Changes Removed bits ENDTX0, ENDTX1, TXBUFE0 and TXBUFE1 from Section 53.7.8 “DACC Interrupt Enable Register”, Section 53.7.9 “DACC Interrupt Disable Register”, Section 53.7.10 “DACC Interrupt Mask Register” and Section 53.7.11 “DACC Interrupt Status Register”. Section 55. “Integrity Check Monitor (ICM)” Section 55.5.2.2 “ICM Region Configuration Structure Member”: removed MRPROT field. Section 55.6.
PAGE 1968
SAM E70/S70/V70/V71 Family Revision History ...........continued Date Changes Section 7. “Input/Output Lines” Section 7.1 “General-Purpose I/O Lines”: changed ODT to RSERIAL in text and figure. Section 7.2.2 “Embedded Trace Module (ETM) Pins”; removed TRACECTL Section 7.5 “ERASE Pin”: added details on in-situ reprogrammability. Section 10. “Memories” Table 10-1 “TCM Configurations in Kbytes“: corrected column GPNVM Bit [8:7] by inverting values (0 first, 3 last).
PAGE 1969
SAM E70/S70/V70/V71 Family Revision History ...........continued Date Changes Section 18. “Bus Matrix (MATRIX)” Table 18-3 “Master to Slave Access”: changed Master 4/Slave 4 access from possible (“x”) to not possble (‘-”) Table 18-4 “Register Mapping”: changed reset value for CCFG_SYSIO register. Section 18.12.7 “System I/O and CAN1 Configuration Register”: corrected typo in CAN1DMABA bit name. Section 18.
PAGE 1970
SAM E70/S70/V70/V71 Family Revision History ...........continued Date Changes Section 40. “Quad SPI Interface (QSPI)” Section 40.5.4 “Direct Memory Access Controller (DMA)”: added Note on 32-bit aligned DMA write accesses. Figure 40-9 “Instruction Transmission Flow Diagram”: modified text if TFRTYP = 0 Section 40.6.7 “Register Write Protection”: added Scrambling Mode Register and Scrambling Key Register to the list of registers that can be write-protected. Section 40.7.
PAGE 1971
SAM E70/S70/V70/V71 Family Revision History ...........continued Date Changes Section 51.1 “Description”: removed information on refresh feature. Figure 51-1 “Block Diagram”: added VDDANA, VREFP and VREFN. Table 51-1 “DACC Signal Description”: added VREFP and VREFN to table. Section 51.2 “Embedded Characteristics”: removed bullet on refresh period. Added Section 51.5.1 “I/O Lines”. Section 51.6.3 “Analog Output Mode Selection”: corrected bit name for output modeselection to ‘DIFF’ from ‘ANA_MODE_SEL’ .
PAGE 1972
SAM E70/S70/V70/V71 Family Revision History ...........continued Date Changes Table 56-4 “Core Power Supply Brownout Detector Characteristics”: updated all values. Changed Note 1. Table 56-6 “VDDIO Supply Monitor”: updated values for TACCURACY Table 56-9. “DC Flash Characteristics” moved to Table 56-2 “DC Characteristics”. Section 56.3.2.1 “Sleep Mode Conditions”: corrected number of WKUP pins. Added Section 56.3.6 “I/O Switching Power Consumption”.
PAGE 1973
SAM E70/S70/V70/V71 Family Revision History ...........continued Date Changes Section 56.14 “Timings for STH Conditions” - Table 56-92 “I/O Characteristics”: new conditions and the corresponding max values added. - Section 56.14.2 “Embedded Flash Characteristics”: replaced two “Embedded Flash Wait State” tables with single Table 56-112 “Embedded Flash Wait State at 105°C“ Section 57. “Mechanical Characteristics” Deleted Section 57.6 “64-lead QFN Wettable Flanks Package”. Section 59.
PAGE 1974
SAM E70/S70/V70/V71 Family The Microchip Website Microchip provides online support via our website at http://www.microchip.com/. This website is used to make files and information easily available to customers.
PAGE 1975
SAM E70/S70/V70/V71 Family your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use.
PAGE 1976
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