Datasheet

 2013-2014 Microchip Technology Inc. DS70000689D-page 229
dsPIC33EPXXXGM3XX/6XX/7XX
16.0 HIGH-SPEED PWM MODULE
The dsPIC33EPXXXGM3XX/6XX/7XX devices support
a dedicated Pulse-Width Modulation (PWM) module
with up to 12 outputs.
The high-speed PWMx module consists of the
following major features:
• Six PWM generators
• Two PWM outputs per PWM generator
• Individual period and duty cycle for each PWM pair
• Duty cycle, dead time, phase shift and a
frequency resolution of 7.14 ns
• Independent Fault and current-limit inputs for
six PWM outputs
• Redundant output
• Center-Aligned PWM mode
• Output override control
• Chop mode (also known as Gated mode)
• Special Event Trigger
• Prescaler for input clock
• PWMxL and PWMxH output pin swapping
• Independent PWM frequency, duty cycle and
phase-shift changes for each PWM generator
• Dead-time compensation
• Enhanced Leading-Edge Blanking (LEB)
functionality
• Frequency resolution enhancement
• PWM capture functionality
The high-speed PWMx module contains up to six PWM
generators. Each PWMx generator provides two PWM
outputs: PWMxH and PWMxL
. The master time base
generator provides a synchronous signal as a common
time base to synchronize the various PWM outputs.
The individual PWM outputs are available on the output
pins of the device. The input Fault signals and current-
limit signals, when enabled, can monitor and protect
the system by placing the PWM outputs into a known
“safe” state.
Each PWMx can generate a trigger to the ADCx
module to sample the analog signal at a specific
instance during the PWM period. In addition, the high-
speed PWMx module also generates a Special Event
Trigger to the ADCx module, based on either of the two
master time bases.
The high-speed PWMx module can synchronize itself
with an external signal or can act as a synchronizing
source to any external device. The SYNCI1 and
SYNCI2 input pins that utilize PPS, can synchronize
the high-speed PWMx module with an external signal.
The SYNCO1 and SYNCO2 pins are output pins that
provides a synchronous signal to an external device.
Figure 16-1 illustrates an architectural overview of the
high-speed PWMx module and its interconnection with
the CPU and other peripherals.
16.1 PWM Faults
The PWMx module incorporates multiple external Fault
inputs, which include FLT1 and FLT2. The inputs are
remappable using the PPS feature. FLT3 is available on
44-pin, 64-pin and 100-pin packages; FLT4 through FLT8
are available on specific pins on 64-pin and 100-pin
packages, and FLT32, which has been implemented with
Class B safety features, and is available on a fixed pin on
all devices.
These Faults provide a safe and reliable way to safely
shut down the PWM outputs when the Fault input is
asserted.
16.1.1 PWM FAULTS AT RESET
During any Reset event, the PWMx module maintains
ownership of the Class B Fault, FLT32. At Reset, this
Fault is enabled in Latched mode to ensure the fail-safe
power-up of the application. The application software
must clear the PWM Fault before enabling the high-
speed motor control PWMx module. To clear the Fault
condition, the FLT32 pin must first be pulled high
externally or the internal pull-up resistor in the CNPUx
register can be enabled.
Note 1: This data sheet summarizes the features
of the dsPIC33EPXXXGM3XX/6XX/7XX
family of devices. It is not intended to be a
comprehensive reference source. To com-
plement the information in this data sheet,
refer to the “dsPIC33/PIC24 Family
Reference Manual”, “High-Speed PWM”
(DS70645), which is available from the
Microchip web site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
Note: In Edge-Aligned PWM mode, the duty
cycle, dead time, phase shift and
frequency resolution are 7.14 ns.
Note: The Fault mode may be changed using
the FLTMOD<1:0> bits (FCLCONx<1:0>),
regardless of the state of FLT32.