Datasheet

dsPIC33EPXXXGM3XX/6XX/7XX
DS70000689D-page 238  2013-2014 Microchip Technology Inc.
bit 3-0 SEVTPS<3:0>: PWMx Special Event Trigger Output Postscaler Select bits
(1)
1111 = 1:16 Postscaler generates the Special Event Trigger on every sixteenth compare match event
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•
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0001 = 1:2 Postscaler generates the Special Event Trigger on every second compare match event
0000 = 1:1 Postscaler generates the Special Event Trigger on every compare match event
REGISTER 16-5: STCON: PWMx SECONDARY TIME BASE CONTROL REGISTER (CONTINUED)
Note 1: These bits should be changed only when PTEN = 0. In addition, when using the SYNCI1 feature, the user
application must program the Period register with a value that is slightly larger than the expected period of
the external synchronization input signal.
2: See Section 25.0 “Peripheral Trigger Generator (PTG) Module” for information on this selection.