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KS8721BL/SL

3.3V Single Power Supply 10/100BASE-TX/FX

MII Physical Layer Transceiver

Rev. 1.3

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com

June 2009

M9999-062509-1.3

General Description

Operating with a 2.5V core to meet low-voltage and low-

power requirements, the KS8721BL and KS8721SL are

10BASE-T/100BASE-TX/FX Physical Layer Transceivers

that use MII and RMII interfaces to transmit and receive

data. They contain 10BASE-T Physical Medium

Attachment (PMA), Physical Medium Dependent (PMD),

and Physical Coding Sub-layer (PCS) functions. The

KS8721BL/SL also have on-chip 10BASE-T output

ﬁltering. This eliminates the need for external ﬁlters and

allows a single set of line magnetics to be used to meet

requirements for both 100BASE-TX and 10BASE-T.

The KS8721BL/SL automatically configure themselves

for 100 or 10Mbps and full- or half-duplex operation,

using an on-chip auto-negotiation algorithm. They are the

ideal physical layer transceiver for 100BASE-TX/

10BASE-T applications.

Features

• Single chip 100BASE-TX/100BASE-FX/10BASE-T

physical layer solution

• 2.5V CMOS design; 2.5/3.3V tolerance on I/O

• 3.3V single power supply with built-in voltage

regulator; Power consumption <340mW (including

output driver current)

• Fully compliant to IEEE 802.3u standard

• Supports MII and Reduced MII (RMII)

• Supports 10BASE-T, 100BASE-TX, and 100BASE-FX

with Far_End_Fault Detection

• Supports power-down and power-saving modes

• Conﬁgurable through MII serial management ports or

via external control pins

Functional Diagram

Summary of content (35 pages)

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KS8721BL/SL 3.3V Single Power Supply 10/100BASE-TX/FX MII Physical Layer Transceiver Rev. 1.3 General Description Features Operating with a 2.5V core to meet low-voltage and lowpower requirements, the KS8721BL and KS8721SL are 10BASE-T/100BASE-TX/FX Physical Layer Transceivers that use MII and RMII interfaces to transmit and receive data. They contain 10BASE-T Physical Medium Attachment (PMA), Physical Medium Dependent (PMD), and Physical Coding Sub-layer (PCS) functions.
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Micrel, Inc.
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Micrel, Inc. KS8721BL/SL Revision History Revision Date 0.9 01/12/04 Data sheet created. 1.0 03/06/04 Initial release. Change to new format. Added part-ordering information. Editorial changes on pin description, RMII, and media converter operation. Update circuit design, reset timing, thermal resistance, electrical characteristics, and strapping option circuit. 1.1 05/17/04 Added BLI product information. 1.2 01/21/05 MDIO Pull-up resistor value changed to 4.7kΩ.
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Micrel, Inc. KS8721BL/SL Contents Pin Configuration .............................................................................................................................................................. 6 Pin Description .................................................................................................................................................................. 7 Strapping Options(1) ...............................................................................................
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Micrel, Inc. KS8721BL/SL Timing Diagrams ............................................................................................................................................................. 26 Selection of Isolation Transformers(1) ........................................................................................................................... 33 Selection of Reference Crystal ...............................................................................................................
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Micrel, Inc.
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Micrel, Inc. KS8721BL/SL Pin Description Pin Number Pin Name Type(1) 1 MDIO I/O 2 MDC I 3 RXD3/ PHYAD Ipd/O MII Receive Data Output. RXD [3..0], these bits are synchronous with RXCLK. When RXDV is asserted, RXD [3..0] presents valid data to MAC through the MII. RXD [3..0] is invalid when RXDV is de-asserted. During reset, the pull-up/pull-down value is latched as PHYADDR [1]. See “Strapping Options” section for details. 4 RXD2/ PHYAD2 Ipd/O MII Receive Data Output.
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Micrel, Inc. KS8721BL/SL Pin Number Pin Name Type(1) 24 VDDIO P Digital IO 2.5/3.3V tolerant power supply. 3.3V power input of voltage regulator. See “Circuit Design Ref. for Power Supply” section for details. 25 INT#/ PHYAD0 Ipu/O Management Interface (MII) Interrupt Out. Interrupt level set by Register 1f, bit 9. During reset, latched as PHYAD[0]. See “Strapping Options” section for details. 26 LED0/ TEST Ipu/O Link/Activity LED Output.
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Micrel, Inc. KS8721BL/SL Pin Number Pin Name Type(1) 44 GND Gnd 45 XO O XTAL feedback: Used with XI for Xtal application. 46 XI I Crystal Oscillator Input: Input for a crystal or an external 25MHz clock. If an oscillator is used, XI connects to a 3.3V tolerant oscillator, and X2 is a no-connect. 47 VDDPLL P Analog PLL 2.5V power supply. See “Circuit Design Ref. for Power Supply” section for details. 48 RST# Ipu Pin Function Ground. Chip Reset.
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Micrel, Inc. KS8721BL/SL Strapping Options(1) Pin Number Pin Name Type(2) 6, 5, 4, 3 PHYAD[4:1]/ RXD[0:3] Ipd/O 25 PHYAD0/ INT# Ipu/O 9(3) PCS_LPBK/ RXDV Ipd/O 11(3) ISO/RXER Ipd/O Enables ISOLATE mode at power-up/reset. PD (default) = Disable, PU = Enable. 21(3) RMII/COL Ipd/O Enables RMII mode at power-up/reset. PD (default) = Disable, PU = Enable. 22(3) RMII_BTB CRS Ipd/O Enable RMII back-to-back mode at power-up/reset. PD (default) = Disable, PU = Enable.
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Micrel, Inc. KS8721BL/SL Functional Description 100BASE-TX Transmit The 100BASE-TX transmit function performs parallel to serial conversion, NRZ-to-NRZI conversion, and MLT-3 encoding and transmission. The circuitry starts with a parallel to serial conversion that converts the 25MHz, 4-bit nibbles into a 125MHz serial bit stream. The incoming data is clocked in at the positive edge of the TXC signal.
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Micrel, Inc. KS8721BL/SL SQE and Jabber Function (10BASE-T only) In 10BASE-T operation, a short pulse is put out on the COL pin after each packet is transmitted. This is required as a test of the 10BASE-T transmit/receive path and is called an SQE test. The 10BASE-T transmitter is disabled and COL goes high if TXEN is high for more than 20ms (Jabbering). If TXEN then goes low for more than 250ms, the 10BASE-T transmitter is re-enabled and COL goes low.
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Micrel, Inc. KS8721BL/SL receive clock is recovered from the line while carrier is active, and operates from the master input clock when the line is idle. The KS8721BL/SL synchronizes the receive data and control signals on the falling edge of RXC in order to stabilize the signals at the rising edge of the clock with 10ns setup and hold times. Transmit Enable The MAC must assert TXEN at the same time as the first nibble of the preamble, and de-assert TXEN after the last bit of the packet.
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Micrel, Inc. KS8721BL/SL Reference Clock (REF_CLK) REF_CLK is a continuous 50MHz clock that provides the timing reference for CRS_DV, RXD[1:0], TX_EN, TXD[1:0], and RX_E. REF_CLK is sourced by the MAC or an external source. Switch implementations may choose to provide REF_CLK as an input or an output depending on whether they provide a REF_CLK output or rely on an external clock distribution device.
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Micrel, Inc. KS8721BL/SL RMII AC Characteristics Symbol Parameter Min Typ REF_CLK Frequency Max 50 Units MHz REF_CLK Duty Cycle 35 65 % tSU TXD[1:0], TX_EN, RXD[1:0], CRS_DV, RXER 4 ns tH TXD[1:0], TX_EN, RXD[1:0], CRS_DV, RXER Data Hold from REF_CLK Rising Edge 2 ns Unused RMII Pins Input Pins TXD[2:3] and TXER are pull-down to GND. Output Pins RXD[2:3] and RXC are no connect. Note that the RMII pin needs to be pulled up to enable RMII mode.
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Micrel, Inc. KS8721BL/SL 10/100 BASE-T Media Dependent Interface 10/100 BASE-T Media Dependent Interface Receive Pair Receive Pair Transmit Pair Transmit Pair Modular Connector (RJ45) Modular Connector (RJ45) HUB (Repeater or Switch) HUB (Repeater or Switch) Figure 2. Crossover Cable Power Management The KS8721BL/SL offers the following modes for power management: • Power-Down Mode: This mode can be achieved by writing to Register 0.11 or pulling pin 30 PD# low.
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Micrel, Inc. KS8721BL/SL still sends out its normal transmit pattern from MAC. FEF can be disabled by strapping pin 27 low. Refer to the “Strapping Options” section. Media Converter Operation The KS8721BL/SL is capable of performing media conversion with two parts in a back-to-back RMII loop-back mode as indicated in the diagram. Both parts are in RMII mode and with RMII BTB asserted (pins 21 and 22 strapped high). One part is operating in TX mode and the other is operating in FX mode.
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Micrel, Inc. KS8721BL/SL Circuit Design Reference for Power Supply Micrel’s integrated built-in, voltage regulator technology and thoughtful implementation allows the user to save BOM cost on both existing and future designs with the use of the new KS8721BL/SL single supply, single port 10/100 Ethernet PHY. Ferrite Bead Ferrite Bead 10F 10F 13 10F 10F 47 VDDC 42 31 VDDPLL 10F 38 VDDRCV 10F 7 +2.5VA +2.5VPLL VDDRX +2.5V VDDTX +3.
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Micrel, Inc. KS8721BL/SL Register Map Register No.
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Micrel, Inc. KS8721BL/SL Address Name Description Default(1) Mode 1.13 100BASE-TX Half-Duplex 1 = capable of 100BASE-X half-duplex 0 = not capable of 100BASE-X half-duplex RO 1 1.12 10BASE-T Full-Duplex 1 = 10Mbps with full-duplex 0 = no 10Mbps with full-duplex capability RO 1 1.11 10BASE-T Half-Duplex 1 = 10Mbps with half-duplex 0 = no 10Mbps with half-duplex capability RO 1 1.10:7 Reserved RO 0 1.6 No Preamble 1 = preamble suppression 0 = normal preamble RO 1 1.
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Micrel, Inc. KS8721BL/SL Address Name Description Default(1) Mode 4.5 10BASE-T 1 = 10Mbps capable 0 = no 10Mbps capability RW 1 4.4:0 Selector Field [00001] = IEEE 802.3 RW 00001 Register 5h - Auto-Negotiation Link Partner Ability 5.15 Next Page 1 = next page capable 0 = no next page capability RO 0 5.14 Acknowledge 1 = link code word received from partner 0 = link code word not yet received RO 0 5.13 Remote Fault 1 = remote fault detected; 0 = no remote fault 5.
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Micrel, Inc. KS8721BL/SL Address Name Description Default(1) Mode 7.12 Acknowledge 2 1 = will comply with message 0 = cannot comply with message RW 0 7.11 Toggle 1 = previous value of the transmitted link code word equaled logic One 0 = logic Zero RO 0 7.10:0 Message Field 11-bit wide field to encode 2048 messages RW 001 Register 8h - Link Partner Next Page Ability 8.15 Next Page 1 = additional next page(s) will follow 0 = last page RO 0 8.
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Micrel, Inc. KS8721BL/SL Address Name Description Default(1) Mode 1b.3 Link Partner Acknowledge Interrupt 1 = Link partner acknowledge occurred 0 = Link partner acknowledge has not occurred RO/SC 0 1b.2 Link Down Interrupt 1 = Link down occurred 0 = Link down has not occurred RO/SC 0 1b.1 Remote Fault Interrupt 1 = Remote fault occurred 0 = Remote fault has not occurred RO/SC 0 1b.
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Micrel, Inc. KS8721BL/SL Absolute Maximum Ratings(1) Operating Ratings(2) Storage Temperature (Ts) .........................–55°C to +150°C Supply Referenced to GND.......................... –0.5V to +4.0V All Pins ......................................................... –0.5V to +4.0V Supply Voltage (VDD_PLL, VDD_TX, VDD_RXC, VDD_RCV, VDDC) ......... +2.5V (VDDIO) .............................................................. +3.3V Ambient Temperature (TA) Commercial .................................
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Micrel, Inc. KS8721BL/SL 10Base-TX Receive RIN RX+/RX– Differential Input Resistance VSQ Squelch Threshold 5MHz square wave 8 kW 400 mV 10Base-TX Transmit (measured differentially after 1:1 transformer) VP tr, tf Peak Differential Output Voltage 50W from each output to VDD Jitters Added 50W from each output to VDD Rise/Fall Time 2.2 2.8 V ±3.5 ns 25 ns Clock Outputs X1, X2 Crystal Oscillator 25 MHz RXC100 Receive Clock, 100TX 25 MHz RXC10 Receive Clock, 10T 2.
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Micrel, Inc. KS8721BL/SL Timing Diagrams Figure 4. 10BASE-T MII Transmit Timing Symbol Parameter Min Typ Max Units tSU1 TXD [3:0] Set-Up to TXC High 10 ns tSU2 TXEN Set-Up to TXC High 10 ns tHD1 TXD [3:0] Hold After TXC High 0 ns tHD2 TXEN Hold After TXC High 0 ns tCRS1 TXEN High to CRS Asserted Latency 4 BT(1) tCRS2 TXEN Low to CRS De-Asserted Latency 8 BT tLAT TXEN High to TXP/TXM Output (TX Latency) 4 BT tSQE COL (SQE) Delay After TXEN De-Asserted 2.
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Micrel, Inc. KS8721BL/SL Figure 5. 100BASE-T MII Transmit Timing Symbol Parameter tSU1 TXD [3:0] Set-Up to TXC High Min 10 Typ ns tSU2 TXEN Set-Up to TXC High 10 ns tHD1 TXD [3:0] Hold After TXC High 0 ns tHD2 TXER Hold After TXC High 0 ns tHD3 TXEN Hold After TXC High 0 ns tCRS1 TXEN High to CRS Asserted Latency 4 Max Units BT(1) tCRS2 TXEN Low to CRS De-Asserted Latency 4 BT tLAT TXEN High to TXP/TXM Output (TX Latency) 9 BT Table 4.
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Micrel, Inc. KS8721BL/SL Start of Stream End of Stream Figure 6.
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Micrel, Inc. KS8721BL/SL Figure 7. Auto-Negotiation/Fast Link Pulse Timing Symbol Parameter tBTB FLP Burst to FLP Burst tFLPW FLP Burst Width Min Typ Max Units 8 16 24 ms 2 ms tPW Clock/Data Pulse Width 100 ns tCTD Clock Pulse to Data Pulse 69 µs tCTC Clock Pulse to Clock Pulse Number of Clock/Data Pulses per Burst 136 17 33 µs µs Table 6. Auto-Negotiation/Fast Link Pulse Timing Parameters June 2009 29 M9999-062509-1.
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Micrel, Inc. KS8721BL/SL Figure 8. Serial Management Interface Timing Symbol Parameter tP MDC Period Min tMD1 MDIO Set-Up to MDC (MDIO as Input) 10 tMD2 MDIO Hold After MDC (MDIO as Input) 10 tMD3 MDC to MDIO Valid (MDIO as Output) Typ 400 Max Units ns ns ns 222 ns Table 7. Serial Management Interface Timing Parameters June 2009 30 M9999-062509-1.
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Micrel, Inc. KS8721BL/SL Figure 9. Reset Timing Symbol Parameter Min tsr Stable Supply Voltages to Reset High 50 Typ Max Units µs Table 8. Reset Timing Parameters Reset Circuit Diagram Micrel recommends the following discrete reset circuit as shown in Figure 10 when powering up the KS8721BL/SL device. For the application where the reset circuit signal comes from another device (e.g., CPU, FPGA, etc), we recommend the reset circuit as shown in Figure 11.
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Micrel, Inc. KS8721BL/SL VCC D1: 1N4148 R 10k D1 KS8721BL/SL RST C 10µF Figure 11. Recommended Circuit for Interfacing with CPU/FPGA Reset At power-on-reset, R, C, and D1 provide the necessary ramp rise time to reset the Micrel device. The reset out from CPU/FPGA provides warm reset after power up. It is also recommended to power up the VDD core voltage earlier than VDDIO voltage. At worst case, the both VDD core and VDDIO voltages should come up at the same time.
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Micrel, Inc. KS8721BL/SL Selection of Isolation Transformers(1) One simple 1:1 isolation transformer is needed at the line interface. An isolation transformer with integrated commonmode choke is recommended for exceeding FCC requirements. The following table gives recommended transformer characteristics. Parameter Value Turns ratio 1 CT : 1 CT Open-circuit inductance (min) 350μH 100mV, 100kHz, 8mA Leakage inductance (max) 0.4μH 1MHz (min) Inter-winding capacitance (max) 12pF D.C.
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Micrel, Inc. KS8721BL/SL Package Information 48-Pin SSOP (SM) June 2009 34 M9999-062509-1.
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Micrel, Inc. KS8721BL/SL 48-Pin LQFP (LQ) MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.