Datasheet

Micrel, Inc. KS8721BL/SL
June 2009
13
M9999-062509-1.3
receive clock is recovered from the line while carrier is active, and operates from the master input clock when the line is
idle. The KS8721BL/SL synchronizes the receive data and control signals on the falling edge of RXC in order to
stabilize the signals at the rising edge of the clock with 10ns setup and hold times.
Transmit Enable
The MAC must assert TXEN at the same time as the first nibble of the preamble, and de-assert TXEN after the last bit
of the packet.
Receive Data Valid
The KS8721BL/SL asserts RXDV when it receives a valid packet. Line operating speed and MII mode will determine
timing changes in the following way:
• For 100BASE-TX links with the MII in 4B mode, RXDV is asserted from the first nibble of the preamble to the
last nibble of the data packet.
• For 10BASE-T links, the entire preamble is truncated. RXDV is asserted with the first nibble of the SFD “5D”
and remains asserted until the end of the packet.
Error Signals
Whenever the KS8721BL/SL receives an error symbol from the network, it asserts RXER and drives “1110” (4B) on the
RXD pins. When the MAC asserts TXER, the KS8721BL/SL will drive “H” symbols (a Transmit Error defined in the IEEE
802.3 4B/5B code group) out on the line to force signaling errors.
Carrier Sense (CRS)
For 100BASE-TX links, a start-of-stream delimiter, or /J/K symbol pair causes assertion of Carrier Sense (CRS). An
end-of-stream delimiter, or /T/R symbol pair, causes de-assertion of CRS. The PMA layer will also de-assert CRS if
IDLE symbols are received without /T/R, yet in this case RXER will be asserted for one clock cycle when CRS is de-
asserted. For 10BASE-T links, CRS assertion is based on reception of valid preamble, and de-assertion on reception of
an end-of-frame (EOF) marker.
Collision
Whenever the line state is half-duplex and the transmitter and receiver are active at the same time, the KS8721BL/SL
asserts its collision signal, which is asynchronous to any clock.
RMII (Reduced MII) Data Interface
RMII interface specifies a low-pin count, Reduced Media Independent Interface (RMII) intended for use between
Ethernet PHYs and Switch or Repeater ASICs. It is fully compliant with IEEE 802.3u [2].
This interface has the following characteristics:
• It is capable of supporting 10Mbps and 100Mbps data rates.
• A single clock reference is sourced from the MAC to PHY (or from an external source).
• It provides independent 2-bit wide (di-bit) transmit and receive data paths.
• It uses TTL signal levels compatible with common digital CMOS ASIC processes.
RMII Signal Definition
Signal Name
Direction
(w/respect to the PHY)
Direction
(w/respect to the MAC) Use
REF_CLK Input Input or Output
Synchronous clock reference for receive, transmit and
control interface
CRS_DV Output Input Carrier Sense/Receive Data Valid
RXD[1:0] Output Input Receive Data
TX_EN Input Output Transmit Enable
TXD[1:0] Input Output Transmit Data
RX_ER Output Input (Not Required) Receive Error