KSZ8863MLL/FLL/RLL Integrated 3-Port 10/100 Managed Switch with PHYs Features • Advanced Switch Features - IEEE 802.1q VLAN Support for Up to 16 Groups (Full Range of VLAN IDs) - VLAN ID Tag/Untag Options, Per Port Basis - IEEE 802.1p/q Tag Insertion or Removal on a Per Port Basis (Egress) - Programmable Rate Limiting at the Ingress and Egress on a Per Port Basis - Broadcast Storm Protection with Percent Control (Global and Per Port Basis) - IEEE 802.
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KSZ8863MLL/FLL/RLL Table of Contents 1.0 Introduction ..................................................................................................................................................................................... 4 2.0 Pin Description and Configuration .................................................................................................................................................. 5 3.0 Functional Description ............................................................
KSZ8863MLL/FLL/RLL 1.0 INTRODUCTION 1.1 General Description KSZ8863MLL, KSZ8863FLL, and KSZ8863RLL are highly integrated 3-port switch-on-a-chip ICs in the industry’s smallest footprint. They are designed to enable a new generation of low port count, cost-sensitive, and power-efficient 10/ 100 Mbps switch systems.
KSZ8863MLL/FLL/RLL 2.0 PIN DESCRIPTION AND CONFIGURATION 48-PIN 7 MM X 7 MM LQFP ASSIGNMENT, (TOP VIEW) FXSD1 RSTN P2LED0 P2LED1 P1LED0 P1LED1 VDDCO GND VDDIO SPISN SPIQ SDA_MDIO FIGURE 2-1: 48 47 46 45 44 43 42 41 40 39 38 37 RXM1 RXP1 TXM1 TXP1 VDDA_3.3 ISET VDDA_1.
KSZ8863MLL/FLL/RLL TABLE 2-1: SIGNALS Pin Number Pin Name Type Note 2-1 1 RXM1 I/O Physical receive or transmit signal (– differential) 2 RXP1 I/O Physical receive or transmit signal (+ differential) 3 TXM1 I/O Physical transmit or receive signal (– differential) 4 TXP1 I/O Physical transmit or receive signal (+ differential) 5 VDDA_3.3 P 3.3V analog VDD 6 ISET O Set physical transmit output current. Pull down this pin with an 11.8 kΩ 1% resistor to ground. 7 VDDA_1.8 P 1.
KSZ8863MLL/FLL/RLL TABLE 2-1: Pin Number 25 26 27 28 SIGNALS (CONTINUED) Pin Name SMRXDV3 SMRXD33/ REFCLKO_3 SMRXD32 SMRXD31 Type Note 2-1 Description Ipu/O Switch MII/RMII receive data valid Strap option: Force duplex mode (P1DPX) PU = Port 1 default to full-duplex mode if P1ANEN = 1 and auto-negotiation fails. Force port 1 in full-duplex mode if P1ANEN = 0. PD = Port 1 default to half-duplex mode if P1ANEN = 1 and auto-negotiation fails. Force port 1 in half-duplex mode if P1ANEN = 0.
KSZ8863MLL/FLL/RLL TABLE 2-1: Pin Number SIGNALS (CONTINUED) Pin Name Type Note 2-1 Description 39 SPISN Ipd SPI Slave mode: chip select (active-low) When SPISN is high, KSZ8863MLL/FLL/RLL is deselected and SPIQ is held in a high impedance state. A high-to-low transition is used to initiate SPI data transfer. Note: An external pull-up is needed on this pin when using SPI or MDC/ MDIO-MIIM/SMI mode. 40 VDDIO P 3.3V, 2.5V, or 1.
KSZ8863MLL/FLL/RLL TABLE 2-1: Pin Number SIGNALS (CONTINUED) Pin Name Type Note 2-1 Description Port 2 LED Indicators: Default: Speed (refer to register 195 bit [5:4]) Strap option: Serial bus configuration Port 2 LED Indicators: Default: Link/Act. (refer to register 195 bit [5:4]) Strap option: Serial bus configuration Serial bus configuration pins to select mode of access to KSZ8863MLL/ FLL/RLL internal registers.
KSZ8863MLL/FLL/RLL Note 2-1 P = power supply GND = Ground I = Input O = Output I/O = Bi-directional Ipu/O = Input with internal pull-up during reset; output pin otherwise. Ipu = Input with internal pull-up. Ipd = Input with internal pull-down. Opu = Output with internal pull-up. Opd = Output with internal pull-down.
KSZ8863MLL/FLL/RLL 3.0 FUNCTIONAL DESCRIPTION KSZ8863MLL/FLL/RLL contains two 10/100 physical layer transceivers and three MAC units with an integrated layer 2 managed switch. KSZ8863MLL/FLL/RLL has the flexibility to reside in either a managed or unmanaged design. In a managed design, the host processor has complete control of KSZ8863MLL/FLL/RLL via the SMI interface, MIIM interface, SPI bus, or I2C bus. An unmanaged design is achieved through I/O strapping and/or EEPROM programming at system reset time.
KSZ8863MLL/FLL/RLL 3.1.6 100BASE-FX SIGNAL DETECTION In 100BASE-FX operation, FXSD (fiber signal detect), input pin 48, is usually connected to the fiber transceiver SD (signal detect) output pin. The fiber signal threshold can be selected by register 192 bit 6 for port 1. When FXSD is less than the threshold, no fiber signal is detected and a far-end fault (FEF) is generated. When FXSD is over the threshold, the fiber signal is detected.
KSZ8863MLL/FLL/RLL 3.1.10.1 Straight Cable A straight cable connects an MDI device to an MDI-X device, or an MDI-X device to an MDI device. Figure 3-1 depicts a typical straight cable connection between a NIC card (MDI) and a switch, or hub (MDI-X).
KSZ8863MLL/FLL/RLL 3.1.10.2 Crossover Cable A crossover cable connects an MDI device to another MDI device, or an MDI-X device to another MDI-X device. Figure 3-2 shows a typical crossover cable connection between two switches or hubs (two MDI-X devices).
KSZ8863MLL/FLL/RLL FIGURE 3-3: AUTO-NEGOTIATION AND PARALLEL OPERATION START AUTO-NEGOTIATION FORCE LINK SETTING NO PARALLEL OPERATION YES BYPASS AUTO-NEGOTIATION AND SET LINK MODE ATTEMPT AUTONEGOTIATION LISTEN FOR 100BASE-TX IDLES LISTEN FOR 10BASE-T LINK PULSES NO JOIN FLOW LINK MODE SET? YES LINK MODE SET 3.1.12 LINKMD® CABLE DIAGNOSTICS KSZ8863MLL/FLL/RLL supports LinkMD.
KSZ8863MLL/FLL/RLL 2. 3. 4. Start cable diagnostic test by writing a ‘1’ to register 42, bit [4]. This enable bit is self-clearing. Wait (poll) for register 42, bit [4] to return a ‘0’, indicating cable diagnostic test is complete. Read cable diagnostic test results in register 42, bits [6:5].
KSZ8863MLL/FLL/RLL During the normal operation mode, the host CPU can set the bit [1:0] in register 195 to transit the current normal operation mode to any one of the other three power management operation modes. 3.2.2 POWER SAVING MODE The power saving mode is entered when auto-negotiation mode is enabled, cable is disconnected, and bit [1:0] = 11 in register 195 is set.
KSZ8863MLL/FLL/RLL The lookup engine inserts the qualified SA into the table, along with the port number and time stamp. If the table is full, the last entry of the table is deleted to make room for the new entry. 3.3.3 MIGRATION The internal lookup engine also monitors whether a station has moved. If a station has moved, it updates the table accordingly.
KSZ8863MLL/FLL/RLL FIGURE 3-5: DESTINATION ADDRESS RESOLUTION FLOW CHART, STAGE 2 PTF1 Spanning Tree Process - Check receiving port's receive enable bit - Check destination port's transmit enable bit - Check whether packets are special (BPDU or specified) IGMP Process - Applied to MAC #1 and MAC #2 - MAC #3 is reserved for microprocessor - IGMP will be forwarded to port 3 Port Mirror Process - RX Mirror - TX Mirror - RX or TX Mirror - RX and TX Mirror Port VLAN Membership Check PTF2 KSZ8863MLL/FL
KSZ8863MLL/FLL/RLL 3.3.7.3 Late Collision If a transmit packet experiences collisions after 512 bit times of the transmission, the packet is dropped. 3.3.7.4 Illegal Frames KSZ8863MLL/FLL/RLL discards frames less than 64 bytes and can be programmed to accept frames up to 1518 bytes, 1536 bytes, or 1916 bytes. These maximum frame size settings are programmed in register 4 (0x04). Since KSZ8863MLL/FLL/RLL supports VLAN tags, the maximum sizing is adjusted when these tags are present. 3.3.7.
KSZ8863MLL/FLL/RLL 3.3.7.8 Port Individual MAC Address and Source Port Filtering KSZ8863MLL/FLL/RLL provides individual MAC address for port 1 and port 2. They can be set at registers 142-147 and 148-153. The packet is filtered if its source address matches the MAC address of port 1 or port 2 when register 21 and 37 bit 6 is set to 1, respectively. For example, the packet is dropped after it completes the loop of a ring network. 3.3.
KSZ8863MLL/FLL/RLL • Provides independent 2-bit wide (di-bit) transmit and receive data paths • Contains two distinct groups of signals: one for transmission and the other for reception When EN_REFCLKO_3 is high, KSZ8863RLL outputs a 50 MHz in REFCLKO_3. Register 198 bit [3] is used to select the internal or external reference clock. Internal reference clock means that the clock for the RMII of KSZ8863RLL is provided by KSZ8863RLL internally and the REFCLKI_3 pin is unconnected.
KSZ8863MLL/FLL/RLL TABLE 3-6: RMII SIGNAL DESCRIPTION (CONTINUED) RMII Signal Name Direction (with respect to PHY) Direction (with respect to MAC) RMII Signal Description KSZ8863RLL RMII Signal Direction TXD0 Input Output Transmit data bit 0 SMTXD30 (input) RX_ER Output Input (not required) Receive error (not used) — SMTXER3 (input) Connects to RX_ER signal of RMII PHY device — — — KSZ8863RLL filters error frames and, thus, does not implement the RX_ER output signal.
KSZ8863MLL/FLL/RLL TABLE 3-8: MII MANAGEMENT FRAME FORMAT Preamble Start of Frame Read/ Write OP Code PHY REG Address Address Bits [4:0] Bits [4:0] TA Data Bits[15:0] Idle Read 32 1’s 01 10 AAAAA RRRRR Z0 DDDDDDDD_DDDDDDDD Z Write 32 1’s 01 01 AAAAA RRRRR 10 DDDDDDDD_DDDDDDDD Z 3.3.11 SERIAL MANAGEMENT INTERFACE (SMI) The SMI is the KSZ8863MLL/FLL/RLL non-standard MIIM interface that provides access to all KSZ8863MLL/FLL/RLL configuration registers.
KSZ8863MLL/FLL/RLL 3.4.2 IEEE 802.1Q VLAN SUPPORT KSZ8863MLL/FLL/RLL supports 16 active VLANs out of the 4096 possible VLANs specified in the IEEE 802.1Q specification. KSZ8863MLL/FLL/RLL provides a 16-entries VLAN table that converts the 12-bits VLAN ID (VID) to the 4-bits Filter ID (FID) for address lookup. If a non-tagged or null-VID-tagged packet is received, the ingress port default VID is used for lookup.
KSZ8863MLL/FLL/RLL Figure 3-6 illustrates how the 802.1p priority field is embedded in the 802.1Q VLAN tag. FIGURE 3-6: 8 6 6 2 2 2 Preamble DA SA VPID TCI length Bits 802.1q VLAN Tag 16 Tagged Packet Type (8100 for Ethernet) 3 1 802.1p CFI Bytes 802.1P PRIORITY FIELD FORMAT 46-1500 LLC Data 4 FCS 12 VLAN ID The 802.1p-based priority is enabled with bit [5] of registers 16, 32, and 48 for ports 1, 2, and 3, respectively.
KSZ8863MLL/FLL/RLL TABLE 3-12: SPANNING TREE STATES Disable State The port should not forward or receive any packets. Learning is disabled. Blocking State Only packets to the processor are forwarded. Learning is disabled. Listening State Only packets to and from the processor are forwarded. Learning is disabled. Learning State Only packets to and from the processor are forwarded. Learning is enabled. Forwarding State Packets are forwarded and received normally. Learning is enabled. 3.
KSZ8863MLL/FLL/RLL Software action: The processor should program the static MAC table with the entries that it needs to receive (for example, BPDU packets). The “overriding” bit should be set so that the switch forwards those specific packets to the processor. The processor may send packets to the port(s) in this state, see Section 3.7, "Tail Tagging Mode" for details. Address learning is enabled on the port in this state.
KSZ8863MLL/FLL/RLL 3.8 IGMP Support For Internet Group Management Protocol (IGMP) support in layer 2, KSZ8863MLL/FLL/RLL provides two components: 3.8.1 IGMP SNOOPING KSZ8863MLL/FLL/RLL traps IGMP packets and forwards them only to the processor (port 3). The IGMP packets are identified as IP packets (either Ethernet IP packets, or IEEE 802.3 SNAP IP packets) with IP version = 0x4 and protocol version number = 0x2. 3.8.
KSZ8863MLL/FLL/RLL If any egress queue receives more traffic than the specified egress rate throughput, packets may be accumulated in the output queue and packet memory. After the memory of the queue or the port is used up, packet dropping or flow control is triggered. As a result of congestion, the actual egress rate may be dominated by flow control or dropping at the ingress end, and may be therefore slightly less than the specified egress rate.
KSZ8863MLL/FLL/RLL 6. Assert an active-low reset to the RSTN pin of KSZ8863MLL/FLL/RLL. After reset is deasserted, KSZ8863MLL/ FLL/RLL begins reading the configuration data from the EEPROM. KSZ8863MLL/FLL/RLL checks that the first byte read from the EEPROM is “88”. If this value is correct, EEPROM configuration continues. If not, EEPROM configuration access is denied and all other data sent from the EEPROM is ignored by KSZ8863MLL/FLL/RLL. 3.12.
KSZ8863MLL/FLL/RLL TABLE 3-14: SPI CONNECTIONS Signal Name External Processor Signal Description 39 SPISN SPI Slave Select 36 SCL (SPIC) SPI Clock 37 SDA (SPID) SPI Data (Master output Slave input) 38 SPIQ SPI Data (Master input; Slave output) Pin Number 2. 3. 4. 5. Enable SPI Slave mode by setting the KSZ8863MLL/FLL/RLL strap-in pins P2LED [1:0] to “10”. Power up the board and assert reset to KSZ8863MLL/FLL/RLL.
KSZ8863MLL/FLL/RLL FIGURE 3-11: SPI MULTIPLE WRITE SPIS_N SPIC SPID X 0 0 0 0 0 0 1 0 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D2 D1 D0 SPIQ WRITE COMMAND WRITE ADDRESS Byte 1 SPIS_N SPIC SPID D7 D6 D5 D4 D4 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D7 D0 D6 D5 D4 D3 SPIQ Byte 2 FIGURE 3-12: Byte 3 ...
KSZ8863MLL/FLL/RLL 3.13.1 FAR-END LOOPBACK Far-end loopback is conducted between KSZ8863MLL/FLL/RLL’s two PHY ports. The loopback is limited to few packages a time for diagnostic purpose and cannot support large traffic. The loopback path starts at the “Originating” PHY port’s receive inputs (RXP/RXM), wraps around at the “loopback” PHY port’s PMD/PMA, and ends at the “Originating” PHY port’s transmit outputs (TXP/TXM).
KSZ8863MLL/FLL/RLL FIGURE 3-14: NEAR-END (REMOTE) LOOPBACK PATH RXP1/ RXM1 PHY Port 1 TXP1/ TXM1 PMD/PMA PCS MAC Switch MAC PCS PMD/PMA RXP2/ RXM2 2017 Microchip Technology Inc.
KSZ8863MLL/FLL/RLL 4.0 REGISTER DESCRIPTIONS 4.1 MII Management (MIIM) Registers The MIIM interface is used to access the MII PHY registers defined in this section. The SPI, I2C, and SMI interfaces can also be used to access some of these registers. The latter three interfaces use a different mapping mechanism than the MIIM interface. The “PHYADs” by default are assigned “0x1” for PHY1 (port 1) and “0x2” for PHY2 (port 2).
KSZ8863MLL/FLL/RLL 4.2 Register Descriptions TABLE 4-2: Bit REGISTER DESCRIPTIONS Name R/W Description Default Reference PHY1 Register 0 (PHYAD = 0x1, REGAD = 0x0): MII Basic Control PHY2 Register 0 (PHYAD = 0x2, REGAD = 0x0): MII Basic Control 15 Soft Reset RO Not Supported 0 — 0 Reg. 29, bit 0 Reg. 45, bit 0 14 Loopback R/W 1 = Perform loopback, as indicated: Port 1 Loopback (reg.
KSZ8863MLL/FLL/RLL TABLE 4-2: Bit REGISTER DESCRIPTIONS (CONTINUED) Name R/W Description Default Reference 1 Always 1 0000 — 11 10 Half Capable RO 1 = 10BASE-T half-duplex capable 0 = Not 10BASE-T half-duplex capable 10-7 Reserved RO — 6 Preamble Suppressed RO Not Supported 0 — 5 AN Complete RO 1 = Auto-negotiation complete 0 = Auto-negotiation not completed 0 Reg. 30, bit 6 Reg. 46, bit 6 4 Far-End Fault RO 1 = Far-end fault detected 0 = No far-end fault detected 0 Reg.
KSZ8863MLL/FLL/RLL TABLE 4-2: Bit REGISTER DESCRIPTIONS (CONTINUED) Name R/W Description Default Reference 10 Pause RO Link partner pause capability 0 Reg. 30, bit 4 Reg. 46, bit 4 9 Reserved RO — 0 — 8 Adv 100 Full RO Link partner 100 full-duplex capability 0 Reg. 30, bit 3 Reg. 46, bit 3 7 Adv 100 Half RO Link partner 100 half-duplex capability 0 Reg. 30, bit 2 Reg. 46, bit 2 6 Adv 10 Full RO Link partner 10 full-duplex capability 0 Reg. 30, bit 1 Reg.
KSZ8863MLL/FLL/RLL TABLE 4-2: REGISTER DESCRIPTIONS (CONTINUED) Bit 4.3 Name R/W Description 1 Remote Loopback R/W 1 = Perform Remote loopback, as follows: Port 1 (reg. 26, bit 1 = ‘1’) Start: RXP1/RXM1 (port 1) Loopback: PMD/PMA of port 1’s PHY End: TXP1/TXM1 (port 1) Port 2 (reg. 42, bit 1 = ‘1’) Start: RXP2/RXM2 (port 2) Loopback: PMD/PMA of port 2’s PHY End: TXP2/TXM2 (port 2) 0 = Normal Operation 0 Reserved R/W Reserved Do not change the default value. Default Reference 0 Reg.
KSZ8863MLL/FLL/RLL TABLE 4-5: ADVANCED CONTROL REGISTERS (CONTINUED) Register (Decimal) Register (Hex) 192 0xC0 4.
KSZ8863MLL/FLL/RLL TABLE 4-6: Bit GLOBAL REGISTERS (0-15) (CONTINUED) Name R/W Description Default R/W 1 = will enable receive direction flow control feature. 0 = will not enable receive direction flow control feature. Switch will not react to any flow control (PAUSE) frame it receives. 1 0 4 IEEE 802.3x Receive Direction Flow Control Enable 3 Frame Length Field Check R/W 1 = will check frame length field in the IEEE packets.
KSZ8863MLL/FLL/RLL TABLE 4-6: Bit 0 GLOBAL REGISTERS (0-15) (CONTINUED) Name R/W Description Default Reserved R/W Reserved Do not change the default value. 0 Register 5 (0x05): Global Control 3 7 802.1Q VLAN Enable R/W 1 = 802.1Q VLAN mode is turned on. VLAN table needs to set up before the operation. 0 = 802.1Q VLAN is disabled. 0 6 IGMP Snoop Enable on Switch MII Interface R/w 1 = IGMP snoop is enabled. All IGMP packets will be forwarded to the Switch MII port.
KSZ8863MLL/FLL/RLL TABLE 4-6: Bit GLOBAL REGISTERS (0-15) (CONTINUED) Name R/W Description Default Register 7 (0x07): Global Control 5 7-0 Broadcast Storm Protection Rate Bit [7:0] R/W This register along with the previous register determines how many “64 byte blocks” of packet data are allowed on an input port in a preset period. The period is 67 ms for 100BT or 500 ms for 10BT. The default is 1%. Note: 100BT Rate: 148,800 frames/sec * 67 ms/interval * 1% = 99 frames/interval (approx.
KSZ8863MLL/FLL/RLL TABLE 4-6: GLOBAL REGISTERS (0-15) (CONTINUED) Bit Name R/W Description Default 3-2 Tag_0x5 R/W IEEE 802.1p mapping. The value in this field is used as the frame’s priority when its IEEE 802.1p tag has a value of 0x5. 10 1-0 Tag_0x4 R/W IEEE 802.1p mapping. The value in this field is used as the frame’s priority when its IEEE 802.1p tag has a value of 0x4.
KSZ8863MLL/FLL/RLL The following registers are used to enable features that are assigned on a per-port basis. The register bit assignments are the same for all ports, but the address for each port is different, as indicated.
KSZ8863MLL/FLL/RLL TABLE 4-7: Bit 6 5 4 3 2-0 PORT REGISTERS (REGISTERS 16 - 95) (CONTINUED) Name Receive Sniff Transmit Sniff Double Tag User Priority Ceiling Port VLAN Membership R/W Description Default R/W 1 = All packets received on the port will be marked as “monitored packets” and forwarded to the designated “sniffer port” 0 = no receive monitoring 0 R/W 1 = All packets transmitted on the port will be marked as “monitored packets” and forwarded to the designated “sniffer port” 0 =
KSZ8863MLL/FLL/RLL TABLE 4-7: Bit PORT REGISTERS (REGISTERS 16 - 95) (CONTINUED) Name R/W Description Default 2 Transmit Enable R/W 1 = enable packet transmission on the port 0 = disable packet transmission on the port Note: This bit is used for spanning tree support. 1 1 Receive Enable R/W 1 = enable packet reception on the port 0 = disable packet reception on the port Note: This bit is used for spanning tree support.
KSZ8863MLL/FLL/RLL TABLE 4-7: Bit 0 PORT REGISTERS (REGISTERS 16 - 95) (CONTINUED) Name Count Pre R/W Description Default R/W Count Preamble bytes 1 = each frame’s preamble bytes (8 per frame) are included in Ingress and Egress rate limiting calculations. 0 = preamble bytes are not counted.
KSZ8863MLL/FLL/RLL TABLE 4-7: Bit PORT REGISTERS (REGISTERS 16 - 95) (CONTINUED) Name R/W Description Default 4 Vct_en R/W (SC) 1 = Enable cable diagnostic test. After VCT test has completed, this bit will be self-cleared. 0 = Indicate cable diagnostic test (if enabled) has completed and the status information is valid for read. 0 3 Force_lnk R/W 1 = Force link pass 0 = Normal Operation 0 2 Reserved RO Reserved Do not change the default value.
KSZ8863MLL/FLL/RLL TABLE 4-7: Bit PORT REGISTERS (REGISTERS 16 - 95) (CONTINUED) Name R/W Description Default 1 For port 1, SMRXDV3 pin value during reset. For port 2, SMRXD31 pin value during reset. 5 Force Duplex R/W 1 = forced full-duplex if (1) AN is disabled or (2) AN is enabled but failed. 0 = forced half-duplex if (1) AN is disabled or (2) AN is enabled but failed.
KSZ8863MLL/FLL/RLL TABLE 4-7: Bit 0 PORT REGISTERS (REGISTERS 16 - 95) (CONTINUED) Name Loopback R/W Description R/W 1 = perform loopback, as indicated: Port 1 Loopback (reg. 29, bit 0 = ‘1’) Start: RXP2/RXM2 (port 2) Loopback: PMD/PMA of port 1’s PHY End: TXP2/TXM2 (port 2) Port 2 Loopback (reg.
KSZ8863MLL/FLL/RLL TABLE 4-7: Bit PORT REGISTERS (REGISTERS 16 - 95) (CONTINUED) Name R/W Description 2 Operation Speed RO 1 = link speed is 100 Mbps 0 = link speed is 10 Mbps 0 1 Operation Duplex RO 1 = link duplex is full 0 = link duplex is half 0 RO 1 = far-end fault status detected 0 = no far-end fault status detected R/W 1 = Software reset 0 = Clear Note: Software reset will reset all registers to the initial values of the power-on reset or warm reset (keep the strap values).
KSZ8863MLL/FLL/RLL 4.5 Advanced Control Registers (Registers 96-198) The IPv4/IPv6 TOS Priority Control Registers implement a fully decoded, 128-bit Differentiated Services Code Point (DSCP) register set that is used to determine the priority from the Type of Service (TOS) field in the IP header. The most significant 6 bits of the TOS field are fully decoded into 64 possibilities, and the singular code that results is compared against the corresponding bits in the DSCP register to determine the priority.
KSZ8863MLL/FLL/RLL TABLE 4-9: ADVANCED CONTROL REGISTERS (REGISTERS 96-198) (CONTINUED) Bit Name R/W Description Default 5-4 DSCP[29:28] R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x0E. 00 3-2 DSCP[27:26] R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x0D.
KSZ8863MLL/FLL/RLL TABLE 4-9: Bit ADVANCED CONTROL REGISTERS (REGISTERS 96-198) (CONTINUED) Name R/W Description Default Register 103 (0x67): TOS Priority Control Register 7 7-6 DSCP[63:62] R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x1F. 00 5-4 DSCP[61:60] R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x1E.
KSZ8863MLL/FLL/RLL TABLE 4-9: ADVANCED CONTROL REGISTERS (REGISTERS 96-198) (CONTINUED) Bit Name R/W Description Default 1-0 DSCP[81:80] R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x28. 00 Register 107 (0x6B): TOS Priority Control Register 11 7-6 DSCP[95:94] R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x2F.
KSZ8863MLL/FLL/RLL TABLE 4-9: ADVANCED CONTROL REGISTERS (REGISTERS 96-198) (CONTINUED) Bit Name R/W Description Default 3-2 DSCP[115:114] R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x39. 00 1-0 DSCP[113:112] R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x38.
KSZ8863MLL/FLL/RLL TABLE 4-9: Bit ADVANCED CONTROL REGISTERS (REGISTERS 96-198) (CONTINUED) Name R/W Description 00 00 3-2 Table Select R/W 00 = static MAC address table selected 01 = VLAN table selected 10 = dynamic MAC address table selected 11 = MIB counter selected 1-0 Indirect Address High R/W Bits [9:8] of indirect address Default Register 122 (0x7A): Indirect Access Control 1 7-0 Indirect Address Low R/W Bits [7:0] of indirect address.
KSZ8863MLL/FLL/RLL TABLE 4-9: ADVANCED CONTROL REGISTERS (REGISTERS 96-198) (CONTINUED) Bit Name R/W Description Default 6-0 Q0 Egress Data Rate Limit R/W Egress data rate limit for priority 0 frames Egress traffic from this priority queue is shaped according to the Data Rate Limit Selected Table.
KSZ8863MLL/FLL/RLL TABLE 4-9: Bit ADVANCED CONTROL REGISTERS (REGISTERS 96-198) (CONTINUED) Name R/W Description Default 6 Reserved RO Reserved Do not change the default values. 0 5-0 Reserved RO Reserved Do not change the default values. 0x18 Register 172 (0xAC): PM Usage Flow Control Select Mode 2 7-6 Reserved RO Reserved Do not change the default values. 0 5-0 Reserved RO Reserved Do not change the default values.
KSZ8863MLL/FLL/RLL TABLE 4-9: Bit ADVANCED CONTROL REGISTERS (REGISTERS 96-198) (CONTINUED) Name R/W Description Default Register 179 (0xB3): TXQ Split for Q3 in Port 2 7 6-0 Priority Select R/W 0 = enable straight priority with Reg 180/181/182 bits[7]=0 and Reg 5 bit[3]=0 for higher priority first 1 = priority ratio is 8:4:2:1 for 4 queues and 2:1 for 2 queues with Reg 180/181/182 bits[7]=1. Reserved RO Reserved Do not change the default values.
KSZ8863MLL/FLL/RLL TABLE 4-9: Bit ADVANCED CONTROL REGISTERS (REGISTERS 96-198) (CONTINUED) Name R/W Description Default Register 186 (0xBA): TXQ Split for Q0 in Port 3 7 6-0 Priority Select R/W 0 = enable straight priority with Reg 183/184/185 bits[7]=0 and Reg 5 bit[3]=0 for higher priority first 1 = priority ratio is 8:4:2:1 for 4 queues and 2:1 for 2 queues with Reg 183/184/185 bits[7]=1. Reserved RO Reserved Do not change the default values.
KSZ8863MLL/FLL/RLL TABLE 4-9: Bit ADVANCED CONTROL REGISTERS (REGISTERS 96-198) (CONTINUED) Name R/W Description Default 3 Insert SRC Port 2 PVID at Port 1 R/W 1= insert SRC port 2 PVID for untagged frame at egress port 1 0 2 Insert SRC Port 2 PVID at Port 3 R/W 1= insert SRC port 2 PVID for untagged frame at egress port 3 0 1 Insert SRC Port 3 PVID at Port 1 R/W 1= insert SRC port 3 PVID for untagged frame at egress port 1 0 0 Insert SRC Port 3 PVID at Port 2 R/W 1= insert SRC port
KSZ8863MLL/FLL/RLL TABLE 4-9: ADVANCED CONTROL REGISTERS (REGISTERS 96-198) (CONTINUED) Bit Name R/W Description 6-4 Forward Invid VID Frame R/W Forwarding ports for frame with invalid VID 3 P3 RMII Clock Selection R/W 1 = Internal 0 = External 0 2 P1 RMII Clock Selection R/W 1 = Internal 0 = External 0 R/W 00 = I2C master mode 01 = I2C slave mode 10 = SPI slave mode 11 = SMI mode 1-0 4.6 Host Interface Mode Default 3b’0 Strapped value of P2LED1, P2LED0.
KSZ8863MLL/FLL/RLL Read reg. 128 (0x80), static table bits [31:24] Read reg. 129 (0x81), static table bits [23:16] Read reg. 130 (0x82), static table bits [15:8] Read reg. 131 (0x83), static table bits [7:0] 2. Static Address Table Write (Write the 8th Entry) Write to reg. 124 (0x7C), static table bits [57:56] Write to reg. 125 (0x7D), static table bits [55:48] Write to reg. 126 (0x7E), static table bits [47:40] Write to reg. 127 (0x7F), static table bits [39:32] Write to reg.
KSZ8863MLL/FLL/RLL Read reg. 131 (0x83), VLAN table bits [7:0] 2. VLAN Table Write (write the 7th entry) Write to reg. 129 (0x81), VLAN table bits [19:16] Write to reg. 130 (0x82), VLAN table bits [15:8] Write to reg. 131 (0x83), VLAN table bits [7:0] Write to reg. 121 (0x79) with 0x04 // Write VLAN table selected Write to reg. 122 (0x7A) with 0x06 // Trigger the write operation 4.8 Dynamic MAC Address Table KSZ8863 maintains the dynamic MAC address table. Only read access is allowed.
KSZ8863MLL/FLL/RLL 4.9 Management Information Base (MIB) Counters KSZ8863 provides 34 MIB counters per port. These counters are used to monitor the port activity for network management. The MIB counters have two format groups: “Per Port” and “All Port Dropped Packet.
KSZ8863MLL/FLL/RLL TABLE 4-14: Offset PORT 1’S “PER PORT” MIB COUNTERS INDIRECT MEMORY OFFSETS Counter Name Description 0x12 Rx512to1023Octets Total Rx packets (bad packets included) that are between 512 and 1023 octets in length 0x13 Rx1024to1522Octets Total Rx packets (bad packets included) that are between 1024 and 1522 octets in length (upper limit depends on max packet size setting) 0x14 TxLoPriorityByte Tx lo-priority good octet count, including PAUSE packets 0x15 TxHiPriorityByte Tx hi-
KSZ8863MLL/FLL/RLL Examples: 1. MIB Counter Read (Read port 1 “Rx64Octets” Counter) Write to reg. 121 (0x79) with 0x1c // Read MIB counters selected Write to reg. 122 (0x7A) with 0x0e // Trigger the read operation Then Read reg. 128 (0x80), overflow bit [31] // If bit 31 = 1, there was a counter overflow valid bit [30] // If bit 30 = 0, restart (reread) from this register counter bits [29:24] Read reg. 129 (0x81), counter bits [23:16] Read reg. 130 (0x82), counter bits [15:8] Read reg.
KSZ8863MLL/FLL/RLL 5.0 OPERATIONAL CHARACTERISTICS 5.1 Absolute Maximum Ratings* Supply Voltage (VIN) (VDDA_1.8, VDDC) ....................................................................................................................................... –0.5V to +2.4V (VDDA_3.3, VDDIO) ...................................................................................................................................... –0.5V to +4.0V Input Voltage ........................................................
KSZ8863MLL/FLL/RLL 6.0 ELECTRICAL CHARACTERISTICS TA = 25°C. Specification is for packaged product only. Current consumption is for the single 3.3V supply device only and includes the 1.8V supply voltages (VDDA, VDDC) that are provided via power output pin 42 (VDDCO). Each PHY port’s transformer consumes an additional 45 mA at 3.3V for 100BASE-TX and 70 mA at 3.3V for 10BASET at full traffic. TABLE 6-1: ELECTRICAL CHARACTERISTICS Parameters Symbol Min. Typ. Max. Units Note mA VDDA_3.
KSZ8863MLL/FLL/RLL TABLE 6-1: ELECTRICAL CHARACTERISTICS (CONTINUED) Parameters Symbol Min. Typ. Max. Units Note VSQ — 400 — mV 5 MHz square wave 10BASE-T Receive Squelch Threshold 10BASE-T Transmit (measured differentially after 1:1 transformer) Peak Differential Output Voltage VP — 2.4 — V 100Ω termination across differential output Output Jitter — — 1.4 11 ns Peak-to-peak 2017 Microchip Technology Inc.
KSZ8863MLL/FLL/RLL 7.0 TIMING SPECIFICATIONS 7.1 EEPROM Timing FIGURE 7-1: EEPROM INTERFACE INPUT TIMING DIAGRAM ts1 tcyc1 th1 Receive Timing SCL SDA FIGURE 7-2: EEPROM INTERFACE OUTPUT TIMING DIAGRAM tcyc1 Transmit Timing SCL tov1 SDA TABLE 7-1: EEPROM TIMING PARAMETERS Symbol Parameter Min. Typ. Max.
KSZ8863MLL/FLL/RLL 7.2 MAC Mode MII Timing FIGURE 7-3: MAC MODE MII TIMING - DATA RECEIVED FROM MII FIGURE 7-4: MAC MODE MII TIMING - DATA TRANSMITTED TO MII TABLE 7-2: MAC MODE MII TIMING PARAMETERS Parameter Description Min. Typ. Max. Units tcyc3 Clock cycle — 400/40 — ns ts3 Setup time 4 — — ns th3 Hold time 2 — — ns tov3 Output valid 7 11 16 ns 2017 Microchip Technology Inc.
KSZ8863MLL/FLL/RLL 7.3 PHY Mode MII Timing FIGURE 7-5: PHY MODE MII TIMING - DATA RECEIVED FROM MII FIGURE 7-6: PHY MODE MII TIMING - DATA TRANSMITTED TO MII TABLE 7-3: PHY MODE MII TIMING PARAMETERS Parameter Description Min. Typ. Max. Units tcyc4 Clock cycle — 400/40 — ns ts4 Setup time 10 — — ns th4 Hold time 0 — — ns tov4 Output valid 18 — 19 ns DS00002335B-page 76 2017 Microchip Technology Inc.
KSZ8863MLL/FLL/RLL 7.4 RMII Timing FIGURE 7-7: RMII TIMING - DATA RECEIVED FROM RMII tcyc Transmit Timing REFCLK t1 t2 MTXD [1 :0 ] MTXEN FIGURE 7-8: RMII TIMING - DATA TRANSMITTED TO RMII Receive Timing tcyc REFCLK MRXD [1: 0] MRXDV t od TABLE 7-4: RMII TIMING PARAMETERS Parameter Description Min. Typ. Max. Units tcyc Clock cycle — 20 — ns t1 Setup time 4 — — ns t2 Hold time 2 — — ns tod Output delay 6 — 16 ns 2017 Microchip Technology Inc.
KSZ8863MLL/FLL/RLL 7.5 I2C Slave Mode Timing FIGURE 7-9: I2C INPUT TIMING FIGURE 7-10: I2C START BIT TIMING FIGURE 7-11: I2C STOP BIT TIMING FIGURE 7-12: I2C OUTPUT TIMING DS00002335B-page 78 2017 Microchip Technology Inc.
KSZ8863MLL/FLL/RLL TABLE 7-5: I2C TIMING PARAMETERS Parameter Description Min. Typ. Max. Units tcyc Clock cycle 400 — — ns ts Setup time 33 — HalfCycle ns th Hold time 0 — — ns ttbs Start bit setup time 33 — — ns ttbh Start bit hold time 33 — — ns tsbs Stop bit setup time 2 — — ns tsbh Stop bit hold time 33 — — ns tov Output valid 64 — 96 ns Note that data is only allowed to change during SCL low-time, except the start and stop bits.
KSZ8863MLL/FLL/RLL 7.6 SPI Timing FIGURE 7-13: SPI INPUT TIMING FIGURE 7-14: SPI OUTPUT TIMING TABLE 7-6: SPI TIMING PARAMETERS Parameter Description Min. Typ. Max.
KSZ8863MLL/FLL/RLL 7.7 Auto-Negotiation Timing FIGURE 7-15: AUTO-NEGOTIATION TIMING Auto-Negotiation - Fast Link Pulse Timing FLP Burst FLP Burst TX+/TX- t FLPW t BTB Clock Pulse Data Pulse t PW t PW TX+/TX- Data Pulse Clock Pulse t CTD t CTC TABLE 7-7: AUTO-NEGOTIATION TIMING PARAMETERS Parameter Description Min. Typ. Max.
KSZ8863MLL/FLL/RLL 7.8 MDC/MDIO Timing FIGURE 7-16: TABLE 7-8: MDC/MDIO TIMING MDC/MDIO TIMING PARAMETERS Parameter Description Min. Typ. Max. Units tP MDC period — 400 — ns tMD1 MDIO (PHY Input) setup to rising edge of MDC 10 — — ns tMD2 MDIO (PHY Input) hold from rising edge of MDC 4 — — ns tMD3 MDIO (PHY Output) delay from rising edge of MDC — 222 — ns DS00002335B-page 82 2017 Microchip Technology Inc.
KSZ8863MLL/FLL/RLL 7.9 Reset Timing The KSZ8863MLL/FLL/RLL reset timing requirement is summarized in Figure 7-17 and Table 7-9. FIGURE 7-17: RESET TIMING SUPPLY VOLTAGES tVR tSR RST# tCS tCH STRAP-IN VALUE tRC STRAP-IN / OUTPUT PIN TABLE 7-9: RESET TIMING PARAMETERS Parameter Description tSR Min. Typ. Max.
KSZ8863MLL/FLL/RLL 8.0 RESET CIRCUIT Figure 8-1 shows a reset circuit recommended for powering up the KSZ8863MLL/FLL/RLL if reset is triggered only by the power supply. FIGURE 8-1: RECOMMENDED RESET CIRCUIT VCC D1: 1N4148 R 10k D1 KSZ8863 RST C 10μF Figure 8-2 shows a reset circuit recommended for applications where reset is driven by another device (for example, the CPU or an FPGA). At power-on-reset, R, C, and D1 provide the necessary ramp rise time to reset the KSZ8863MLL/ FLL/RLL device.
KSZ8863MLL/FLL/RLL 9.0 SELECTION OF ISOLATION TRANSFORMERS A 1:1 isolation transformer is required at the line interface. Use one with integrated common-mode chokes for designs exceeding FCC requirements. Table 9-1 lists recommended transformer characteristics. TABLE 9-1: TRANSFORMER SELECTION CRITERIA Parameter Value Test Conditions Turns Ratio 1 CT : 1 CT — Open-Circuit Inductance (min.) 350 µH 100 mV, 100 kHz, 8 mA Leakage Inductance (max.) 0.4 µH 1 MHz (min.
KSZ8863MLL/FLL/RLL 10.0 PACKAGE OUTLINE FIGURE 10-1: Note: 48-LEAD LQFP 7 MM X 7 MM PACKAGE For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging. DS00002335B-page 86 2017 Microchip Technology Inc.
KSZ8863MLL/FLL/RLL APPENDIX A: TABLE A-1: DATA SHEET REVISION HISTORY REVISION HISTORY Revision DS00002335A (1-10-17) Section/Figure/Entry — Converted Micrel data sheet KSZ8863MLL/FLL/ RLL to Microchip DS00002335A. Minor text changes throughout. Table 3-5 Updated with a note of RMII interface operation. Operating Ratings** Update added VDDA_3.3 data. Updated junction thermal resistance. Table 4-2 Changed PHY1 Register 29 (PHYAD = 0x1, REGAD = 0x1D) from “Not support” to “LinkMD Control/Status”.
KSZ8863MLL/FLL/RLL THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
KSZ8863MLL/FLL/RLL PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Examples: XX PART NO. X X X X a) KSZ8863MLL Device Interface Package Supply Temperature Media Type Voltage Device: KSZ8863 Interface: M = MII R = RMII F = Fibre Package: L = 48-lead LQFP Supply Voltage: L = Single 3.
KSZ8863MLL/FLL/RLL NOTES: DS00002335B-page 90 2017 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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