Datasheet

ManualsBrandsMicrochip ManualsIntegrated Circuits (ICs)5-Port Ethernet Switch MII / RMII PQFP

 2016 Microchip Technology Inc. DS00002246A-page 1

Features

Advanced Switch Features

• IEEE 802.1q VLAN Support for up to 128 Active

VLAN Groups (Full-Range 4096 of VLAN IDs)

• Static MAC Table Supports up to 32 Entries

• VLAN ID Tag/Untagged Options, Per Port Basis

• IEEE 802.1p/q Tag Insertion or Removal on a Per

Port Basis Based on Ingress Port (Egress)

• Programmable Rate Limiting at the Ingress and

Egress on a Per Port Basis

• Jitter-Free Per Packet Based Rate Limiting Sup-

port

• Broadcast Storm Protection with Percentage Con-

trol (Global and Per Port Basis)

• IEEE 802.1d Rapid Spanning Tree Protocol RSTP

Support

• Tail Tag Mode (1 Byte Added Before FCS) Sup-

port at Port 5 to Inform the Processor Which

Ingress Port Receives the Packet

• 1.4 Gbps High-Performance Memory Bandwidth

and Shared Memory Based Switch Fabric with

Fully Non-Blocking Configuration

• Dual MII with MAC 5 and PHY 5 on Port 5, SW5-

MII/RMII for MAC 5 and P5-MII/RMII for PHY 5

• Enable/Disable Option for Huge Frame Size up to

2000 Bytes Per Frame

• IGMP v1/v2 Snooping (IPv4) Support for Multicast

Packet Filtering

• IPv4/IPv6 QoS Support

• Support Unknown Unicast/Multicast Address and

Unknown VID Packet Filtering

• Self-Address Filtering

Comprehensive Configuration Register Access

• Serial Management Interface (MDC/MDIO) to All

PHYs Registers and SMI Interface (MDC/MDIO)

to All Registers

• High-Speed SPI (up to 25 MHz) and I

C Master

Interface to all Internal Registers

• I/O Pins Strapping and EEPROM to Program

Selective Registers in Unmanaged Switch Mode

• Control Registers Configurable on the Fly (Port-

Priority, 802.1p/d/q, AN…)

QoS/CoS Packet Prioritization Support

• Per Port, 802.1p and DiffServ-Based

• 1/2/4-Queue QoS Prioritization Selection

• Programmable Weighted Fair Queuing for Ratio

Control

• Re-Mapping of 802.1p Priority Field Per Port

Basis

Integrated 5-Port 10/100 Ethernet Switch

• New Generation Switch with Five MACs and Five

PHYs that are Fully Compliant with the IEEE

802.3u Standard

• PHYs Designed with Patented Enhanced Mixed-

Signal Technology

• Non-Blocking Switch Fabric Ensures Fast Packet

Delivery by Utilizing a 1K MAC Address Lookup

Table and a Store-and-Forward Architecture

• On-Chip 64Kbyte Memory for Frame Buffering

(Not Shared with 1K Unicast Address Table)

• Full-Duplex IEEE 802.3x Flow Control (PAUSE)

with Force Mode Option

• Half-Duplex Back Pressure Flow Control

• HP Auto MDI/MDI-X and IEEE Auto Crossover

Support

• SW-MII Interface Supports Both MAC Mode and

PHY Mode

• 7-Wire Serial Network Interface (SNI) Support for

Legacy MAC

• Per Port LED Indicators for Link, Activity, and 10/

100 Speed

• Register Port Status Support for Link, Activity,

Full-/Half-Duplex and 10/100 Speed

• LinkMD

Cable Diagnostic Capabilities

• On-Chip Terminations and Internal Biasing Tech-

nology for Cost Down and Lowest Power Con-

sumption

Switch Monitoring Features

• Port Mirroring/Monitoring/Sniffing: Ingress and/or

Egress Traffic to Any Port or MII

• MIB Counters for Fully Compliant Statistics Gath-

ering; 34 MIB Counters Per Port

• Loopback Support for MAC, PHY, and Remote

Diagnostic of Failure

• Interrupt for the Link Change on Any Ports

Low-Power Dissipation

• Full-Chip Hardware Power-Down

• Full-Chip Software Power-Down and Per Port

Software Power-Down

• Energy-Detect Mode Support <100 mW Full-Chip

Power Consumption When All Ports Have No

KSZ8895MQX/RQX/FQX/MLX

Integrated 5-Port 10/100 Managed Ethernet

Switch with MII/RMII Interface

Summary of content (108 pages)

PAGE 1
KSZ8895MQX/RQX/FQX/MLX Integrated 5-Port 10/100 Managed Ethernet Switch with MII/RMII Interface Features Advanced Switch Features • IEEE 802.1q VLAN Support for up to 128 Active VLAN Groups (Full-Range 4096 of VLAN IDs) • Static MAC Table Supports up to 32 Entries • VLAN ID Tag/Untagged Options, Per Port Basis • IEEE 802.
PAGE 2
KSZ8895MQX/RQX/FQX/MLX Activity • Very-Low Full-Chip Power Consumption (<0.5W) in Standalone 5-Port, without Extra Power Consumption on Transformers • Dynamic Clock Tree Shutdown Feature • Voltages: Single 3.3V Supply with 3.3V VDDIO and Internal 1.2V LDO Controller Enabled, or External 1.2V LDO Solution - Analog VDDAT 3.3V Only - VDDIO Support 3.3V, 2.5V, and 1.8V - Low 1.
PAGE 3
KSZ8895MQX/RQX/FQX/MLX TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.
PAGE 4
KSZ8895MQX/RQX/FQX/MLX Table of Contents 1.0 Introduction ..................................................................................................................................................................................... 5 2.0 Pin Description and Configuration ................................................................................................................................................... 6 3.0 Functional Description .......................................................
PAGE 5
KSZ8895MQX/RQX/FQX/MLX 1.0 INTRODUCTION 1.1 General Description The KSZ8895MQX/RQX/FQX/MLX is a highly-integrated, Layer 2 managed, five-port switch with numerous features designed to reduce system cost. Intended for cost-sensitive 10/100Mbps five-port switch systems with low power consumption, on-chip termination, and internal core power controllers, it supports high-performance memory bandwidth and shared memory-based switch fabric with non-blocking configuration.
PAGE 6
KSZ8895MQX/RQX/FQX/MLX 2.
PAGE 7
KSZ8895MQX/RQX/FQX/MLX 128-LQFP PIN ASSIGNMENT (TOP VIEW) 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 LED3-2 LED4-0 LED4-1 LED4-2 LED5-0 LED5-1 LED5-2 VDDC GNDD SCONF0 SCONF1 SCRS SCOL SMRXD0 SMRXD1 SMRXD2 SMRXD3 SMRXDV SMRXC VDDIO GNDD SMTXC SMTXER SMTXD0 SMTXD1 SMTXD2 SMTXD3 SMTXEN PCOL PCRS PMRXER PMRXD0 FIGURE 2-2: 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 KSZ8895ML
PAGE 8
KSZ8895MQX/RQX/FQX/MLX TABLE 2-1: SIGNALS - KSZ8895MQX/RQX/FQX/MLX (CONTINUED) Pin Number Pin Name Type, Note 2-1 Port 3 VDDAR P — 1.2V analog VDD. 4 RXP1 I 1 Physical receive signal + (differential). 5 RXM1 I 1 Physical receive signal - (differential). 6 GNDA GND — Analog ground. 7 TXP1 O 1 Physical transmit signal + (differential). 8 TXM1 O 1 Physical transmit signal - (differential). 9 VDDAT P — 3.3V analog VDD.
PAGE 9
KSZ8895MQX/RQX/FQX/MLX TABLE 2-1: SIGNALS - KSZ8895MQX/RQX/FQX/MLX (CONTINUED) Pin Number Pin Name Type, Note 2-1 Port 33 RXM5 I 5 Physical receive signal - (differential). 34 GNDA GND — Analog ground. 35 TXP5 O 5 Physical transmit signal + (differential). 36 TXM5 O 5 Physical transmit signal - (differential). 37 VDDAT P — 3.3V analog VDD. Pin Function, Note 2-2 38 NC/FXSD3 IPD 3 FQX: This pin can be floating when port 3 is used as copper port (default).
PAGE 10
KSZ8895MQX/RQX/FQX/MLX TABLE 2-1: SIGNALS - KSZ8895MQX/RQX/FQX/MLX (CONTINUED) Pin Number Pin Name Type, Note 2-1 Port 59 VDDIO P — 3.3V, 2.5V, or 1.8V digital VDD for digital I/O circuitry. Pin Function, Note 2-2 60 PMRXC I/O 5 MQX/FQX/MLX: Output PHY [5] MII receive clock. RQX: Output PHY [5] RMII reference clock, this clock is used when opposite doesn’t provide RMII 50 MHz clock or the system doesn’t provide an external 50 MHz clock for the P5-RMII interface.
PAGE 11
KSZ8895MQX/RQX/FQX/MLX TABLE 2-1: SIGNALS - KSZ8895MQX/RQX/FQX/MLX (CONTINUED) Pin Number Pin Name Type, Note 2-1 Port 69 SMTXEN IPD — Port 5 Switch MII/RMII transmit enable. 70 SMTXD3 IPD — MQX/FQX/MLX: Port 5 Switch MII transmit bit 3. RQX: no connection for RMII. 71 SMTXD2 IPD — MQX/FQX/MLX: Port 5 Switch MII transmit bit 2. RQX: no connection for RMII. 72 SMTXD1 IPD — Port 5 Switch MII/RMII transmit bit 1. 73 SMTXD0 IPD — Port 5 Switch MII/RMII transmit bit 0.
PAGE 12
KSZ8895MQX/RQX/FQX/MLX TABLE 2-1: Pin Number 83 SIGNALS - KSZ8895MQX/RQX/FQX/MLX (CONTINUED) Pin Name SMRXD0 Type, Note 2-1 IPD/O Port — Pin Function, Note 2-2 MQX/FQX/MLX: Port 5 Switch MII receive bit 0. RQX: Port 5 Switch RMII receive bit 0 Strap option: LED mode PD (default) = mode 0; PU = mode 1. See “Register 11.
PAGE 13
KSZ8895MQX/RQX/FQX/MLX TABLE 2-1: Pin Number SIGNALS - KSZ8895MQX/RQX/FQX/MLX (CONTINUED) Type, Note 2-1 Pin Name Port Pin Function, Note 2-2 Pins 91, 86, and 87 are dual MII/RMII configuration pins for the Port 5 MAC5 MII/RMII and PHY [5] MII/RMII. SW5-MII supports both MAC mode and PHY modes. P5-MII supports PHY mode only.
PAGE 14
KSZ8895MQX/RQX/FQX/MLX TABLE 2-1: Pin Number SIGNALS - KSZ8895MQX/RQX/FQX/MLX (CONTINUED) Pin Name Type, Note 2-1 Port Pin Function, Note 2-2 95 LED4-0 IPU/O 4 LED indicator 0. Strap option: PU (default) = Normal mode. PD = Energy Detection mode (EDPD mode) Strap to Register 14 bits [4:3] 96 LED3-2 IPU/O 3 LED indicator 2. 97 LED3-1 IPU/O 3 LED indicator 1. 98 LED3-0 IPU/O 3 LED indicator 0.
PAGE 15
KSZ8895MQX/RQX/FQX/MLX TABLE 2-1: Pin Number SIGNALS - KSZ8895MQX/RQX/FQX/MLX (CONTINUED) Type, Note 2-1 Pin Name Port Pin Function, Note 2-2 PHYs MII management (MIIM registers) data I/O. Or SMI interface data I/O Note: Need an external pull-up when driven. 108 MDIO IPU/O All 109 SPIQ IPU/O All SPI serial data output in SPI slave mode. Note: Need an external pull-up when driven.
PAGE 16
KSZ8895MQX/RQX/FQX/MLX TABLE 2-1: SIGNALS - KSZ8895MQX/RQX/FQX/MLX (CONTINUED) Pin Number Pin Name Type, Note 2-1 Port 123 NC NC — No connection. Leave NC pin floating. 124 NC NC — No connection. Leave NC pin floating. Pin Function, Note 2-2 LDO_O pin connect to gate pin of MOSFET if using the internal 1.2V LDO controller. LDO_O pin will be floating if using an external 1.2V LDO. 125 LDO_O P — Note: When Pin126 voltage is greater than the internal 1.
PAGE 17
KSZ8895MQX/RQX/FQX/MLX The KSZ8895MQX/RQX/FQX/MLX can function as a managed switch or an unmanaged switch. If no EEPROM or micro-controller exists, then the KSZ8895MQX/RQX/FQX/MLX will operate from its default setting. The strap-in option pins can be configured by external pull-up/down resistors and take effect after power down reset or warm reset. The functions are described in the table below.
PAGE 18
KSZ8895MQX/RQX/FQX/MLX TABLE 2-2: Pin Number STRAP-IN OPTIONS - KSZ8895MQX/RQX/FQX/MLX (CONTINUED) Pin Name Type, Note 2-3 Description, Note 2-4 Switch MII/RMII receive bit 0. Strap option: LED mode PD (default) = mode 0; PU = mode 1. See “Register 11.” 83 SMRXD0 IPD/O — Mode 0 Mode 1 LEDx_2 Link/Activity 100Link/Activity LEDx_1 Full-Duplex/Col 10Link/Activity LEDx_0 Speed Full-Duplex Pin 91,86,87 are dual MII/RMII configuration pins for the Port 5 MAC 5 MII/RMII and PHY [5] MII/RMII.
PAGE 19
KSZ8895MQX/RQX/FQX/MLX TABLE 2-2: Pin Number 101 102 105 106 STRAP-IN OPTIONS - KSZ8895MQX/RQX/FQX/MLX (CONTINUED) Pin Name LED2-2 LED2-1 LED2-0 LED1-0 Type, Note 2-3 Description, Note 2-4 IPU/O LED2 indicator 2. Strap option for KSZ8895RQX only: PU (default) = Select the device as clock mode in RQX SW5- RMII, 25 MHz crystal to X1/X2 pins of the device and REFCLK output 50 MHz clock. PD = Select the device as normal mode in SW5-RMII. Switch MAC5 used only.
PAGE 20
KSZ8895MQX/RQX/FQX/MLX 3.0 FUNCTIONAL DESCRIPTION The KSZ8895MQX/RQX/FQX/MLX contains five 10/100 physical layer transceivers and five media access control (MAC) units with an integrated Layer 2 managed switch. The device runs in three modes. The first mode is as a fiveport integrated switch. The second is as a five-port switch with the fifth port decoupled from the physical port. In this mode, access to the fifth MAC is provided through a media independent interface (MII/RMII).
PAGE 21
KSZ8895MQX/RQX/FQX/MLX 3.1.4 SCRAMBLER/DE-SCRAMBLER (100BASE-TX ONLY) The purpose of the scrambler is to spread the power spectrum of the signal in order to reduce EMI and baseline wander. The data is scrambled through the use of an 11-bit wide linear feedback shift register (LFSR). This can generate a 2047bit non-repetitive sequence. The receiver will then descramble the incoming data stream with the same sequence at the transmitter. 3.1.
PAGE 22
KSZ8895MQX/RQX/FQX/MLX 3.1.10.1 Straight Cable A straight cable connects an MDI device to an MDI-X device, or an MDI-X device to an MDI device. Figure 3-1 depicts a typical straight cable connection between a NIC card (MDI) and a switch, or hub (MDI-X). FIGURE 3-1: 3.1.10.2 TYPICAL STRAIGHT CABLE CONNECTION Crossover Cable A crossover cable connects an MDI device to another MDI device, or an MDI-X device to another MDI-X device.
PAGE 23
KSZ8895MQX/RQX/FQX/MLX • Priority 2: 100BASE-TX, half-duplex • Priority 3: 10BASE-T, full-duplex • Priority 4: 10BASE-T, half-duplex If auto-negotiation is not supported or the KSZ8895MQX/RQX/FQX/MLX link partner is forced to bypass auto-negotiation, the KSZ8895MQX/RQX/FQX/MLX sets its operating mode by observing the signal at its receiver.
PAGE 24
KSZ8895MQX/RQX/FQX/MLX 3.1.12.2 Usage The following is a sample procedure for using LinkMD with Registers {26, 27, 28, 29} on port 1. 1. 2. 3. 4. 5. 6. Disable Auto-Negotiation by writing a ‘1’ to Register 28 (0x1c), bit [7]. Disable auto MDI/MDI-X by writing a ‘1’ to Register 29 (0x1d), bit [2] to enable manual control over the differential pair used to transmit the LinkMD® pulse. A software sequence set up to the internal registers for LinkMD only, see an example below.
PAGE 25
KSZ8895MQX/RQX/FQX/MLX Note: After testing ends, set all registers above to their default values. The default values are ‘00’ for the Register (0x37) and the Register (0x47) 3.1.13 ON-CHIP TERMINATION RESISTORS The KSZ8895MQX/RQX/FQX/MLX reduces the board cost and simplifies the board layout by using on-chip termination resistors for all ports and RX/TX differential pairs without the external termination resistors.
PAGE 26
KSZ8895MQX/RQX/FQX/MLX FIGURE 3-4: RECOMMENDED 1.2V POWER CONNECTION USING INTERNAL 1.2V LDO CONTROLLER ȍ S 3.3V D 1.2V Nȍ 47μF G Nȍ 125 126 3,15,31 VDDAR 9,18,24,37 GNDD GNDA VDDIO FB 59,77,100 VDDAT 2,6,12,16,21,27,30,34,127 3.2.2 50,89,117 VDDC 49,58,76,88,99,116 USING EXTERNAL 1.2V LDO REGULATOR The KSZ8895MQX/RQX/FQX/MLX can use an external 1.2V LDO regulator too. When use an external 1.
PAGE 27
KSZ8895MQX/RQX/FQX/MLX 3.3 Power Management The KSZ8895MQX/RQX/FQX/MLX supports a full chip hardware power down mode. When the PWRDN Pin 47 is internally activated low (pin PWRDN = 0), the entire chip is powered down. If this pin is de-asserted, the chip will be reset internally. The KSZ8895MQX/RQX/FQX/MLX can also use multiple power levels of 3.3V, 2.5V, or 1.8V for VDDIO to support different I/O voltage.
PAGE 28
KSZ8895MQX/RQX/FQX/MLX 3.3.3 SOFT POWER-DOWN MODE The soft power down mode is entered by setting bits [4:3] = 10 in Register 14. When KSZ8895MQX/RQX/FQX/MLX is in this mode, all PLL clocks are disabled, also all of PHYs and the MACs are off. Any dummy host access will wake-up this device from current soft power down mode to normal operation mode and internal reset will be issued to make all internal registers go to the default values. 3.3.
PAGE 29
KSZ8895MQX/RQX/FQX/MLX 3.4.5 FORWARDING The KSZ8895MQX/RQX/FQX/MLX will forward packets using an algorithm that is depicted in the following flowcharts. Figure 3-6 shows stage one of the forwarding algorithm where the search engine looks up the VLAN ID, static table, and dynamic table for the destination address, and comes up with “port to forward 1” (PTF1).
PAGE 30
KSZ8895MQX/RQX/FQX/MLX The KSZ8895MQX/RQX/FQX/MLX flow controls all ports if the receive queue becomes full. FIGURE 3-6: DESTINATION ADDRESS LOOK-UP FLOW CHART - STAGE 1 ' DS00002246A-page 30  2016 Microchip Technology Inc.
PAGE 31
KSZ8895MQX/RQX/FQX/MLX FIGURE 3-7: DESTINATION ADDRESS RESOLUTION FLOW CHART - STAGE 2 The KSZ8895MQX/RQX/FQX/MLX will not forward the following packets: • Error packets. These include framing errors, frame check sequence (FCS) errors, alignment errors, and illegal size packet errors. • IEEE 802.3x PAUSE frames. KSZ8895MQX/RQX/FQX/MLX intercepts these packets and performs full-duplex flow control accordingly. • “Local” packets.
PAGE 32
KSZ8895MQX/RQX/FQX/MLX • Aggressive back-off (Register 3, bit 0) • No excessive collision drop (Register 4, bit 3) • Back pressure (Register 4, bit 5) These bits are not set as the default because they are not the IEEE standard. 3.4.14 BROADCAST STORM PROTECTION The KSZ8895MQX/RQX/FQX/MLX has an intelligent option to protect the switch system from receiving too many broadcast packets.
PAGE 33
KSZ8895MQX/RQX/FQX/MLX 3.4.17 PORT 5 MAC 5 SW5-MII INTERFACE FOR THE KSZ8895MQX/FQX/MLX Table 3-5 shows two connection manners: • The first is an external MAC connects to SW5-MII PHY mode. • The second is an external PHY connects to SW5-MII MAC mode. Please see the pin [91, 86, 87] descriptions for configuration details for the MAC mode and PHY mode. SW5-MII works with 25 MHz clock for 100BASE-TX, SW5-MII works with 2.5 MHz clock for 10BASE-T.
PAGE 34
KSZ8895MQX/RQX/FQX/MLX 3.4.18 PORT 5 MAC 5 SWITCH SW5-RMII INTERFACE FOR THE KSZ8895RQX The Reduced Media Independent Interface (RMII) specifies a low pin count Media Independent Interface (MII). The KSZ8895RQX supports RMII interface at Port 5 switch side and provides a common interface at MAC5 layer in the device, and has the following key characteristics: • Supports 10 Mbps and 100 Mbps data rates.
PAGE 35
KSZ8895MQX/RQX/FQX/MLX TABLE 3-6: PORT 5 MAC5 SW5-RMII CONNECTION (CONTINUED) SW5-RMII MAC-to-MAC Connection (PHY Mode) External MAC — Note 3-1 3.4.
PAGE 36
KSZ8895MQX/RQX/FQX/MLX Please see the descriptions of Register 130 bits [7:6] for detail. 3.5.1.1 Port-Based Priority With port-based priority, each ingress port is individually classified as a priority 0-3 receiving port. All packets received at the priority 3 receiving port are marked as high priority and are sent to the high-priority transmit queue if the corresponding transmit queue is split.
PAGE 37
KSZ8895MQX/RQX/FQX/MLX 3.5.1.3 DiffServ-Based Priority DiffServ-based priority uses the ToS Registers (Registers 144 to 159) in the Advanced Control Registers section. The ToS priority control registers implement a fully decoded, 128-bit Differentiated Services Code Point (DSCP) register to determine packet priority from the 6-bit ToS field in the IP header. When the most significant six bits of the ToS field are fully decoded, 64 code points for DSCP result.
PAGE 38
KSZ8895MQX/RQX/FQX/MLX Software action: the processor should not send any packets to the port. The switch may still send specific packets to the processor (packets that match some entries in the static table with “overriding bit” set) and the processor should discard those packets. When disabling the port’s learning capability (learning disable = ‘1’), set the Register 1 bit 5 and bit 4 will flush rapidly with the port related entries in the dynamic MAC table and static MAC table.
PAGE 39
KSZ8895MQX/RQX/FQX/MLX TABLE 3-8: TAIL TAG RULES (CONTINUED) Ingress to Port 5 (Host to KSZ8895MQX/RQX/FQX/MLX) 0,0,1,1 Queue 3 is used at destination port x,1,x,x Whatever send packets to specified port in bit [3:0] 1,x,x,x Bit [6:0] will be ignored as normal (address look-up for destination) Egress from Port 5 (KSZ8895MQX/RQX/FQX/MLX to Host) Bit [1:0] 3.5.
PAGE 40
KSZ8895MQX/RQX/FQX/MLX 3.5.7 VLAN SUPPORT The KSZ8895MQX/RQX/FQX/MLX supports 128 active VLANs and 4096 possible VIDs specified in IEEE 802.1q. KSZ8895MQX/RQX/FQX/MLX provides a 128-entry VLAN table, which correspond to 4096 possible VIDs and converts to FID (7 bits) for address look-up max 128 active VLANs. If a non-tagged or null-VID-tagged packet is received, then the ingress port VID is used for look-up when 802.1q is enabled by the global Register 5 control 3 bit 7.
PAGE 41
KSZ8895MQX/RQX/FQX/MLX based, 802.1p and DiffServ-based priorities, the port-based priority is fixed priority 0-3 selection by bits [4-3] of the Register Port Control 0. The 802.1p and DiffServ-based priority can be mapped to priority 0-3 by default of the Register 128 and 129. In the ingress rate limit, set Register 135 global control 19 bit 3 to enable queue-based rate limit if using twoqueue or four-queue mode.
PAGE 42
KSZ8895MQX/RQX/FQX/MLX FIGURE 3-10: EEPROM CONFIGURATION TIMING DIAGRAM To configure the KSZ8895MQX/RQX/FQX/MLX with a pre-configured EEPROM use the following steps: 1. 2. 3. 4. 5. 6. At the board level, connect Pin 110 on the KSZ8895MQX/RQX/FQX/MLX to the SCL pin on the EEPROM. Connect Pin 111 on the KSZ8895MQX/RQX/FQX/MLX to the SDA pin on the EEPROM. A [2-0] address pins of EEPROM should be tied to ground for A [2-0] = ‘000’ to be identified by the KSZ8895MQX/ RQX/FQX/MLX.
PAGE 43
KSZ8895MQX/RQX/FQX/MLX TABLE 3-11: SPI CONNECTIONS Pin Number Signal Name Microprocessor Signal Description 110 SCL SPI Clock 111 SPID/SDA Master Out Slave Input 109 SPIQ Master In Slave Output 2. Set the input signals PS[1:0] (pins 113 and 114, respectively) to “10” to set the serial configuration to SPI slave mode. 3. Power up the board and assert a reset signal. After reset wait 100 µs, the start switch bit in Register 1 will be set to ‘0’.
PAGE 44
KSZ8895MQX/RQX/FQX/MLX FIGURE 3-13: SPI MULTIPLE WRITE FIGURE 3-14: SPI MULTIPLE READ 3.6 MII Management (MIIM) Interface The KSZ8895MQX/RQX/FQX/MLX supports the standard IEEE 802.3 MII Management Interface, also known as the Management Data Input/Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the states of the KSZ8895MQX/RQX/FQX/MLX. An external device with MDC/MDIO capability is used to read the PHY status or configure the PHY settings.
PAGE 45
KSZ8895MQX/RQX/FQX/MLX per port. The MIIM Interface can operate up to a maximum clock speed of 10 MHz MDC clock. Table 3-12 depicts the MII Management Interface frame format.
PAGE 46
KSZ8895MQX/RQX/FQX/MLX 4.0 REGISTER DESCRIPTIONS TABLE 4-1: REGISTERS DESCRIPTIONS Offset Decimal Hex Description 0-1 0x00-0x01 Chip ID Registers. 2-13 0x02-0x0D Global Control Registers. 14-15 0x0E-0x0F Power Down Management Control Registers. 16-20 0x10-0x14 Port 1 Control Registers. 21-23 0x15-0x17 Port 1 Reserved (Factory Test Registers). 24-31 0x18-0x1F Port 1 Control/Status Registers. 32-36 0x20-0x24 Port 2 Control Registers.
PAGE 47
KSZ8895MQX/RQX/FQX/MLX 4.1 Global Registers TABLE 4-2: Address GLOBAL REGISTER DESCRIPTIONS Name Description Mode Default Chip family. RO 0x95 Register 0 (0x00): Chip ID0 7-0 Family ID Register 1 (0x01): Chip ID1/Start Switch 7-4 Chip ID 0100 = KSZ8895MQX/FQX/MLX 0110 = KSZ8995RQX RO 0x4 is for MQX, FQX, and MLX 0x6 is for RQX 3-1 Revision ID Revision ID, see Register 137 (0x89) RO 0x0 R/W 0 1 = Start the chip when external pins (PS1, PS0) = (1,0) or (0,1).
PAGE 48
KSZ8895MQX/RQX/FQX/MLX TABLE 4-2: Address GLOBAL REGISTER DESCRIPTIONS (CONTINUED) Name Description Mode Default 3 Enable PHY MII/RMII 1, enable PHY P5-MII/RMII interface (default). Note: if not enabled, the switch will be tri-state all outputs. R/W 1 Pin LED[5][1] strap option. PD(0): isolate. PU(1): Enable. Note: LED[5][1] has internal pull-up (PU). 2 Reserved N/A Do not change. RO 1 UNH Mode 1, the switch will drop packets with 0x8808 in T/L field, or DA=01-80-C2-00-00-01.
PAGE 49
KSZ8895MQX/RQX/FQX/MLX TABLE 4-2: Address GLOBAL REGISTER DESCRIPTIONS (CONTINUED) Name Description Mode Default 2 Aging Enable 1, Enable age function in the chip. 0, Disable aging function. R/W 1 Pin LED[5][2] strap option. PD(0): Aging disable. PU(1): Aging enable (default). Note: LED[5][2] has internal pull up. 1 Fast Age Enable 1 = Turn on fast age (800 µs). R/W 0 R/W 0 Pin PMRXD0 strap option. PD(0): Disable aggressive back off (default). PU(1): Aggressive back off.
PAGE 50
KSZ8895MQX/RQX/FQX/MLX TABLE 4-2: Address 2 GLOBAL REGISTER DESCRIPTIONS (CONTINUED) Name Description 1, will accept packet sizes up to 1916 bytes (inclusive). This bit setting will override setting from bit 1 Huge Packet of the same register. Support 0, the max packet size will be determined by bit 1 of this register. Mode Default R/W 0 1 Legal Maximum Packet Size Check Disable 1, will accept packet sizes up to 1536 bytes (inclusive).
PAGE 51
KSZ8895MQX/RQX/FQX/MLX TABLE 4-2: Address 6 5 GLOBAL REGISTER DESCRIPTIONS (CONTINUED) Name Description Switch SW5MII/RMII 1, enable MII/RMII interface half-duplex mode. Half-Duplex 0, disable MII/RMII interface full-duplex mode. Mode Switch SW5MII/RMII Flow Control Enable 1, enable full-duplex flow control on switch MII/ RMII interface. 0, disable full-duplex flow control on switch MII/ RMII interface. Mode Default R/W 0 Pin SMRXD2 strap option. PD(0): (default) Fullduplex mode.
PAGE 52
KSZ8895MQX/RQX/FQX/MLX TABLE 4-2: Address GLOBAL REGISTER DESCRIPTIONS (CONTINUED) Name Description Mode Default 6 Port 5 SW5RMII reference clock edge select RQX: Select the data sampling edge of Switch MAC5 SW5-RMII reference clock: 1 = data sampling on negative edge of refclk 0 = data sampling on positive edge of refclk (default) Note: MQX/FQX/MLX is reserved with read-only for this bit. R/W 0 5 Reserved N/A Do not changes. RO 0 4 Reserved N/A Do not changes.
PAGE 53
KSZ8895MQX/RQX/FQX/MLX TABLE 4-2: Address GLOBAL REGISTER DESCRIPTIONS (CONTINUED) Mode Default CPU interface clock select Select the internal clock speed for SPI, MDI interface: 00 = 41.67 MHz (SPI up to 6.25 MHz, MDC up to 6 MHz) 01 = 83.33 MHz Default (SPI SCL up to 12.
PAGE 54
KSZ8895MQX/RQX/FQX/MLX 4.2 Port Registers The following registers are used to enable features that are assigned on a per port basis. The register bit assignments are the same for all ports, but the address for each port is different, as indicated.
PAGE 55
KSZ8895MQX/RQX/FQX/MLX TABLE 4-3: Address 0 PORT REGISTERS (CONTINUED) Name Description Two Queues Split Enable This bit 0 in the Register16/32/48/64/80 should be in combination with Register177/193/209/225/241 bit 1 for Port 1-5 will select the split of 1/2/4 queues: For Port 1, [Register 177 bit 1, Register 16 bit 0] = [11], Reserved [10], the port output queue is split into four priority queues or if map 802.1p to priority 0-3 mode.
PAGE 56
KSZ8895MQX/RQX/FQX/MLX TABLE 4-3: Address 4 PORT REGISTERS (CONTINUED) Name Force Flow Control Description 1, will always enable Rx and Tx flow control on the port, regardless of AN result. 0, the flow control is enabled based on AN result (Default) Mode Default R/W 0 Strap-in option LED1_1/PCOL: For port 3/port 4 LED1_1 default Pull-up (1): Not force flow control; PCOL default Pulldown (0): Not force flow control. LED1_1 Pull-down (0): Force flow control; PCOL Pull-up (1): Force flow control.
PAGE 57
KSZ8895MQX/RQX/FQX/MLX TABLE 4-3: Address 3 PORT REGISTERS (CONTINUED) Name Disable the output of port 5 SW5-RMII 50 MHz output clock on RXC pin when 50 MHz clock is not Port 5 SW5- being used by the device and the 50 MHz clock RMII 50 MHz from external oscillator or opposite device in RMII clock output mode disable 1 = Disable clock output when RXC pin is not used in RMII mode (used for 0 = Enable clock output in RMII mode KSZ8895RQX only) 2 P5-RMII 50 MHz clock output disable (used for KSZ8895RQX onl
PAGE 58
KSZ8895MQX/RQX/FQX/MLX TABLE 4-3: Address PORT REGISTERS (CONTINUED) Mode Default Vct_result 00 = Normal condition 01 = Open condition detected in cable 10 = Short condition detected in cable 11 = Cable diagnostic test has failed RO 00 4 Vct_enable 1 = Enable cable diagnostic test. After VCT test has completed, this bit will be self-cleared. 0 = Indicate cable diagnostic test (if enabled) has completed and the status information is valid for read.
PAGE 59
KSZ8895MQX/RQX/FQX/MLX TABLE 4-3: Address PORT REGISTERS (CONTINUED) Name Description Mode Default 5 Forced Duplex 1, forced full-duplex if (1) AN is disabled or (2) AN is enabled but failed. 0, forced half-duplex if (1) AN is disabled or (2) AN is enabled but failed (Default). R/W 0 For Port 3/Port 4 only. Pins LED1_0/PCRS strap option: 1). Force half-duplex mode: LED1_0 pin Pullup(1) (default) for Port 3 PCRS pin Pull-down (0) (default) for Port 4 2).
PAGE 60
KSZ8895MQX/RQX/FQX/MLX TABLE 4-3: Address PORT REGISTERS (CONTINUED) Name Description Mode Default 3 Power Down 1, power down. 0, normal operation. R/W 0 2 Disable Auto 1, disable auto MDI/MDI-X function. MDI/MDI-X 0, enable auto MDI/MDI-X function. R/W 0 1 Forced MDI 1, if auto MDI/MDI-X is disabled, force PHY into MDI mode (transmit on RX pair). 0, MDI-X mode (transmit on TX pair). R/W 0 MAC Loopback 1 = Perform MAC loopback, loop back path as follows: E.g.
PAGE 61
KSZ8895MQX/RQX/FQX/MLX TABLE 4-3: Address PORT REGISTERS (CONTINUED) Name Description Mode Default R/W 0 Register 31 (0x1F): Port 1 Control 7 and Status 2 Register 47 (0x2F): Port 2 Control 7 and Status 2 Register 63 (0x3F): Port 3 Control 7 and Status 2 Register 79 (0x4F): Port 4 Control 7 and Status 2 Register 95 (0x5F): Port 5 Control 7 and Status 2 7 PHY Loopback 1 = Perform PHY loopback, loop back path as follows: E.g. set port 1 PHY Loopback (reg.
PAGE 62
KSZ8895MQX/RQX/FQX/MLX TABLE 4-4: Address ADVANCED CONTROL REGISTER DESCRIPTIONS Name Description Mode Default R/W 0x00 R/W 0x10 R/W 0xA1 R/W 0xff R/W 0xff R/W 0xff R/W 000 R/W 0 R/W 0 R/W 00 R/W 00000000 R/W 00000 R/W 00000000 R/W 00000000 R/W 00000000 R/W 00000000 R/W 00000000 R/W 00000000 R/W 00000000 R/W 00000000 RO 000 Register 104 (0x68): MAC Address Register 0 7-0 MACA[47:40] — Register 105 (0x69): MAC Address Register 1 7-0 MACA[39:32] — Register
PAGE 63
KSZ8895MQX/RQX/FQX/MLX TABLE 4-4: Address ADVANCED CONTROL REGISTER DESCRIPTIONS (CONTINUED) Name Description Mode Default 4 Port 5 Interrupt Status 1, Port 5 interrupt request 0, normal Note: This bit is set by Port 5 link change. Write a “1” to clear this bit RO 0 3 Port 4 Interrupt Status 1, Port 4 interrupt request 0, normal Note: This bit is set by Port 4 link change.
PAGE 64
KSZ8895MQX/RQX/FQX/MLX TABLE 4-4: Address ADVANCED CONTROL REGISTER DESCRIPTIONS (CONTINUED) Name Description Mode Default 5-4 Tag_0x6 IEEE 802.1p mapping. The value in this field is used as the frame’s priority when its IEEE 802.1p tag has a value of 0x6. R/W 0x3 3-2 Tag_0x5 IEEE 802.1p mapping. The value in this field is used as the frame’s priority when its IEEE 802.1p tag has a value of 0x5. R/W 0x2 1-0 Tag_0x4 IEEE 802.1p mapping.
PAGE 65
KSZ8895MQX/RQX/FQX/MLX TABLE 4-4: Address ADVANCED CONTROL REGISTER DESCRIPTIONS (CONTINUED) Name Description Mode Default Output drive strength select[1:0] = 00 = 4 mA drive strength 01 = 8 mA drive strength (default) 10 = 10 mA drive strength 11 = 14 mA drive strength Note: Bit [1] value is the INVERT of the strap value at the pin. Bit[0] value is the SAME of the strap value at the pin. R/W 01 Pin LED [3][0] strap option. Pull-down (0): Select 10 mA drive strength.
PAGE 66
KSZ8895MQX/RQX/FQX/MLX TABLE 4-4: Address 4-0 ADVANCED CONTROL REGISTER DESCRIPTIONS (CONTINUED) Name Description 00000 = filter unknown IP multicast packet 00001 = forward unknown IP multicast packet to port 1, Unknown IP 00010 = forward unknown IP multicast packet to multicast packet port 2, forward port 00011 = forward unknown IP multicast packet to map port 1, port 2 … 11111 = broadcast unknown IP multicast packet to all ports Mode Default R/W 00000 Register 135 (0x87): Global Control 19 7 Res
PAGE 67
KSZ8895MQX/RQX/FQX/MLX TABLE 4-4: Address 3-2 1-0 ADVANCED CONTROL REGISTER DESCRIPTIONS (CONTINUED) Name Description Mode Default DSCP[3:2] IPv4 and IPv6 mapping The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x01 R/W 00 DSCP[1:0] IPv4 and IPv6 mapping The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x00 R/W 00 Register 145 (0x91): TOS Pr
PAGE 68
KSZ8895MQX/RQX/FQX/MLX TABLE 4-4: Address ADVANCED CONTROL REGISTER DESCRIPTIONS (CONTINUED) Name Description Mode Default 3-2 DSCP[67:66] IPv4 and IPv6 mapping _ for value 0x21 R/W 00 1-0 DSCP[65:64] IPv4 and IPv6 mapping _ for value 0x20 R/W 00 Register 153 (0x99): TOS Priority Control Register 9 7-6 DSCP[79:78] IPv4 and IPv6 mapping _ for value 0x27 R/W 00 5-4 DSCP[77:76] IPv4 and IPv6 mapping _ for value 0x26 R/W 00 3-2 DSCP[75:74] IPv4 and IPv6 mapping _ for value 0x25 R/W
PAGE 69
KSZ8895MQX/RQX/FQX/MLX TABLE 4-4: Address 3 ADVANCED CONTROL REGISTER DESCRIPTIONS (CONTINUED) Name Description Register 176: insert source Port 1 PVID for untagged frame at egress Port 5 Register 192: insert source Port 2 PVID for Insert Source untagged frame at egress Port 5 Port PVID for Register 208: insert source Port 3 PVID for Untagged untagged frame at egress Port 5 Packet Destina- Register 224: insert source Port 4 PVID for tion to Highest untagged frame at egress Port 5 Egress Port Register 24
PAGE 70
KSZ8895MQX/RQX/FQX/MLX TABLE 4-4: Address ADVANCED CONTROL REGISTER DESCRIPTIONS (CONTINUED) Name Description Mode Default 4 Queue Split Enable This bit in combination with Register 16/32/48/ 64/80 bit 0 will select the split of 1/2/4 queues: {Register177 bit 1, Register16 bit 0}= 11, reserved. 10, the port output queue is split into four priority queues or if map 802.1p to priority 0-3 mode. 01, the port output queue is split into two priority queues or if map 802.1p to priority 0-3 mode.
PAGE 71
KSZ8895MQX/RQX/FQX/MLX TABLE 4-4: Address 6-0 ADVANCED CONTROL REGISTER DESCRIPTIONS (CONTINUED) Name Description Mode Default Port Transmit Queue 1 Ratio[6:0] Packet number for Transmit Queue 1 for low/ high priority packets in four queues mode and high priority packets in two queues mode R/W 0000010 0, strict priority, will transmit all the packets from this priority queue 0 before transmit lower priorEnable Port ity queue.
PAGE 72
KSZ8895MQX/RQX/FQX/MLX TABLE 4-4: Address 6-0 ADVANCED CONTROL REGISTER DESCRIPTIONS (CONTINUED) Name Description Port-Based Priority 0 Ingress Limit Ingress data rate limit for priority 0 frames Ingress traffic from this port is shaped according to the Data Rate Selected Table.
PAGE 73
KSZ8895MQX/RQX/FQX/MLX TABLE 4-4: Address 6-0 ADVANCED CONTROL REGISTER DESCRIPTIONS (CONTINUED) Name Description Port Queue 1 Egress Limit Egress data rate limit for priority 1 frames Egress traffic from this priority queue is shaped according to the Data Rate Selected Table. See the table follow the end of Egress limit control registers. In four queues mode, it is low/high priority. In two queues mode, it is high priority.
PAGE 74
KSZ8895MQX/RQX/FQX/MLX TABLE 4-4: Address 4 3-0 ADVANCED CONTROL REGISTER DESCRIPTIONS (CONTINUED) Name Description Mode Default Invert phase of SMRXC clock output on SW5RMII for RQX part 1 = Invert the phase of SMRXC clock output in RMII mode that will add opposite RMII output delay 10ns from clock rising edge to data out. 0 = normal phase if SMRXC clock output Note: MQX and FQX are reserved with read only for this bit.
PAGE 75
KSZ8895MQX/RQX/FQX/MLX 4.4 Static MAC Address Table KSZ8895MQX/RQX/FQX/MLX has a static and a dynamic address table. When a DA look-up is requested, both tables will be searched to make a packet forwarding decision. When an SA look-up is requested, only the dynamic table is searched for aging, migration, and learning purposes. The static DA look-up result will have precedence over the dynamic DA look-up result. If there are DA matches in both tables, the result from the static table will be used.
PAGE 76
KSZ8895MQX/RQX/FQX/MLX TABLE 4-7: Address FORMAT OF STATIC MAC TABLE FOR WRITES (CONTINUED) Name Description 52 - 48 Forwarding Ports The 5 bits control the forward ports, example: 00001, forward toPort 1 00010, forward to Port 2 ..... 10000, forward to Port 5 00110, forward to Port 2 and Port 3 11111, broadcasting (excluding the ingress port) 47 - 0 MAC 48-bit MAC address. Address (DA) Mode Default W 00000 W 0x0 Examples: 1.
PAGE 77
KSZ8895MQX/RQX/FQX/MLX 4.5 VLAN Table The VLAN table is used for VLAN table look-up. If 802.1q VLAN mode is enabled (Register 5 bit 7 = 1), this table is used to retrieve VLAN information that is associated with the ingress packet. There are three fields for FID (filter ID), Valid, and VLAN membership in the VLAN table. The three fields must be initialized before the table is used. There is no VID field because 4096 VIDs are used as a dedicated memory address index into a 1024x52-bit memory space.
PAGE 78
KSZ8895MQX/RQX/FQX/MLX Read Register 116 (0x74), (Register116 [6:0] are bits 12-6 of VLAN VID=2 entry) Read Register 117 (0x75), (Register117 [7:2] are bits 5-0 of VLAN VID=2 entry) 2. VLAN Table Write (write the VID=10 entry) Read the VLAN set that contains VID=8, 9, 10, 11.
PAGE 79
KSZ8895MQX/RQX/FQX/MLX 4.6 Dynamic MAC Address Table Table 4-10 is read-only. The contents are maintained only by the KSZ8895MQX/RQX/FQX/MLX. TABLE 4-10: Address DYNAMIC MAC ADDRESS TABLE Name Description Mode Default Format of Dynamic MAC Address Table (1K entries) MAC Empty 1, there is no valid entry in the table. 0, there are valid entries in the table. RO 1 70 - 61 Number of Valid Entries Indicates how many valid entries in the table.
PAGE 80
KSZ8895MQX/RQX/FQX/MLX Read Register 119 (15-8) Read Register 120 (7-0) 4.7 Management Information Base (MIB) Counters The MIB counters are provided on per port basis. These counters are read using indirect memory access as noted in the following table: TABLE 4-11: Offset MIB COUNTERS Counter Name Description RxLoPriorityByte Rx lo-priority (default) octet count including bad packets. 0x1 RxHiPriorityByte Rx hi-priority octet count including bad packets.
PAGE 81
KSZ8895MQX/RQX/FQX/MLX TABLE 4-11: Offset MIB COUNTERS (CONTINUED) Counter Name Description 0x19 TxMulticastPkts Tx good multicast packets (not including errored multicast packets or valid broadcast packets). 0x1A TxUnicastPkts Tx good unicast packets. 0x1B TxDeferred Tx packets by a port for which the 1st Tx attempt is delayed due to the busy medium. 0x1C TxTotalCollision Tx total collision, half-duplex only.
PAGE 82
KSZ8895MQX/RQX/FQX/MLX The KSZ8895MQX/RQX/FQX/MLX provides a total of 34 MIB counter per port. These counter are used to monitor the port detail activity for network management and maintenance. These MIB counters are read using indirect memory access as illustrated in the following examples: Programming Examples: (Note 4-2) 1.
PAGE 83
KSZ8895MQX/RQX/FQX/MLX 4.8 MIIM Registers All the registers defined in this section can be also accessed via the SPI interface. Note: different mapping mechanisms are used for MIIM and SPI. The “PHYAD” defined in IEEE is assigned as “0x1” for Port 1, “0x2” for Port 2, “0x3” for Port 3, “0x4” for Port 4, and “0x5” for Port 5. The “REGAD” supported are 0x0-0x5 (0h-5h), 0x1D (1dh) and 0x1F (1fh). TABLE 4-12: Address MIIM REGISTERS Name Description Mode Default Soft Reset 1, PHY soft reset.
PAGE 84
KSZ8895MQX/RQX/FQX/MLX TABLE 4-12: Address MIIM REGISTERS (CONTINUED) Name Description 13 100 Half Capable 12 11 10 - 7 Mode Default 1, 100BASE-TX half-duplex capable. 0, Not 100BASE-TX half-duplex capable. RO 1 10 Full Capable 1, 10BASE-T full-duplex capable. 0, Not 10BASE-T full-duplex capable. RO 1 10 Half Capable 1, 10BASE-T half-duplex capable. 0, 10BASE-T half-duplex capable.
PAGE 85
KSZ8895MQX/RQX/FQX/MLX TABLE 4-12: MIIM REGISTERS (CONTINUED) Address Name Description Mode Default 10 Pause 1, link partner flow control capable. 0, link partner not flow control capable. RO 0 9 Reserved — RO 0 8 Adv 100 Full 1, link partner 100BT full-duplex capable. 0, link partner not 100BT full-duplex capable. RO 0 7 Adv 100 Half 1, link partner 100BT half-duplex capable. 0, link partner not 100BT half-duplex capable.
PAGE 86
KSZ8895MQX/RQX/FQX/MLX TABLE 4-12: Address MIIM REGISTERS (CONTINUED) Name Description Mode Default Remote Loopback 1 = Perform Remote loopback, loopback path as follows: Port 1 (PHY ID address 0x1 reg. 1f, bit 1 = ‘1’) Start: RXP1/RXM1 (port 1) Loopback: PMD/PMA of port 1’s PHY End: TXP1/TXM1 (port 1) Setting PHY ID address 0x2, 3, 4, 5 reg. 1f, bit 1 = ‘1’ will perform remote loopback on port 2, 3, 4, 5. 0 = Normal Operation.
PAGE 87
KSZ8895MQX/RQX/FQX/MLX 5.0 OPERATIONAL CHARACTERISTICS 5.1 Absolute Maximum Ratings* Supply Voltage (VDDAR, VDDAP, VDDC)............................................................................................................................... –0.5V to +2.4V (VDDAT, VDDIO) .......................................................................................................................................... –0.5V to +4.0V Input Voltage ..............................................................
PAGE 88
KSZ8895MQX/RQX/FQX/MLX 6.0 ELECTRICAL CHARACTERISTICS VIN = 1.2V/3.3V (typical). TA = 25°C. Specification is for packaged product only. There is not an additional transformer consumption due to the use of on-chip termination technology with internal biasing for 10BASE-T and 100BASE-TX. Measurements were taken with operating ratings. TABLE 6-1: ELECTRICAL CHARACTERISTICS Parameters Symbol Min. Typ. Max. Units Note 100BASE-TX Operation—All Ports 100% Utilization 100BASE-TX (Transmitter) 3.
PAGE 89
KSZ8895MQX/RQX/FQX/MLX TABLE 6-1: ELECTRICAL CHARACTERISTICS (CONTINUED) Parameters Symbol Min. Typ. Max. Units Note Energy-Detect Mode + PLL OFF 1.2V IEDM2 — 1.5 — mA VDDAR + VDDC Input High Voltage (VDDIO = 3.3/2.5/1.8V) VIH 2.0/1.8/ 1.3 — — V — Input Low Voltage (VDDIO = 3.3/2.5/1.8V) VIL — — 0.8/0.7/ 0.5 V — Input Current (Excluding Pull-Up/ Pull-Down) IIN –10 — 10 µA VIN = GND ~ VDDIO Input High Voltage (VDDIO = 3.3/2.5/1.8V) VOH 2.4/2.0/ 1.
PAGE 90
KSZ8895MQX/RQX/FQX/MLX 7.0 TIMING DIAGRAMS 7.1 EEPROM Timing FIGURE 7-1: EEPROM INTERFACE INPUT RECEIVE TIMING DIAGRAM FIGURE 7-2: EEPROM INTERFACE OUTPUT TRANSMIT TIMING DIAGRAM TABLE 7-1: EEPROM TIMING PARAMETERS Parameter Description Min. Typ. Max. Units tCYC1 Clock cycle — 16384 — ns tS1 Setup time 20 — — ns tH1 Hold time 20 — — ns tOV1 Output valid 4096 4112 4128 ns DS00002246A-page 90  2016 Microchip Technology Inc.
PAGE 91
KSZ8895MQX/RQX/FQX/MLX 7.2 SNI Timing FIGURE 7-3: SNI INPUT TIMING FIGURE 7-4: SNI OUTPUT TIMING TABLE 7-2: SNI TIMING PARAMETERS Parameter Description Min. Typ. tCYC2 tS2 Clock Cycle — 100 — ns Set-Up Time 10 — — ns tH2 Hold Time 0 — — ns tO2 Output Valid 0 3 6 ns  2016 Microchip Technology Inc. Max.
PAGE 92
KSZ8895MQX/RQX/FQX/MLX 7.3 MII Timing FIGURE 7-5: MAC MODE MII TIMING - DATA RECEIVED FROM MII FIGURE 7-6: MAC MODE MII TIMING - DATA TRANSMITTED FROM MII TABLE 7-3: MAC MODE MII TIMING PARAMETERS Symbol Parameter tCYC3 tS3 10BASE-T/100BASE-TX Min. Typ. Clock Cycle — 400/40 — ns Setup Time 10 — — ns tH3 Hold Time 5 — — ns tOV3 Output Valid 3 7 25 ns DS00002246A-page 92 Max. Units  2016 Microchip Technology Inc.
PAGE 93
KSZ8895MQX/RQX/FQX/MLX FIGURE 7-7: PHY MODE MII TIMING - DATA RECEIVED FROM MII FIGURE 7-8: PHY MODE MII TIMING - DATA TRANSMITTED FROM MII TABLE 7-4: PHY MODE MII TIMING PARAMETERS 10BASE-T/100BASE-TX Symbol Parameter tCYC4 tS4 tH4 Hold Time 0 — — ns tOV4 Output Valid 16 20 25 ns Min. Typ. Clock Cycle — 400/40 — ns Setup Time 10 — — ns  2016 Microchip Technology Inc. Max.
PAGE 94
KSZ8895MQX/RQX/FQX/MLX 7.4 RMII Timing FIGURE 7-9: RMII TIMING - DATA RECEIVED FROM RMII FIGURE 7-10: RMII TIMING - DATA TRANSMITTED TO RMII TABLE 7-5: RMII TIMING PARAMETERS Symbol Description Min. Typ. Max. Units tcyc Clock Cycle — 20 — µs t1 Setup Time 4 — — ms t2 Hold Time 2 — — ns tod Output Delay 6 10 14 ns DS00002246A-page 94  2016 Microchip Technology Inc.
PAGE 95
KSZ8895MQX/RQX/FQX/MLX 7.
PAGE 96
KSZ8895MQX/RQX/FQX/MLX FIGURE 7-12: TABLE 7-7: SPI OUTPUT TIMING SPI OUTPUT TIMING PARAMETERS Symbol Parameter fC Clock Frequency tCLQX SPIQ Hold Time 0 — 0 ns tCLQV Clock Low to SPIQ Valid — — 15 ns tCH Clock High Time 18 — — ns tCL Clock Low Time 18 — — ns tQLQH SPIQ Rise Time — — 50 ns tQHQL SPIQ Fall Time — — 50 ns tSHQZ SPIQ Disable Time — — 15 ns DS00002246A-page 96 Min. Typ. Max. Units — — 25 MHz  2016 Microchip Technology Inc.
PAGE 97
KSZ8895MQX/RQX/FQX/MLX 7.6 Auto-Negotiation Timing FIGURE 7-13: TABLE 7-8: AUTO-NEGOTIATION TIMING AUTO-NEGOTIATION TIMING PARAMETERS Symbol Parameter Min. Typ. Max. Units tBTB FLP burst to FLP burst 8 16 24 ms tFLPW FLP burst width — 2 — ms tPW Clock/Data pulse width — 100 — ns tCTD Clock pulse to Data pulse 55.5 64 69.5 µs tCTC Clock pulse to Clock pulse 111 128 139 µs — Number of Clock/Data pulses per burst 17 — 33 —  2016 Microchip Technology Inc.
PAGE 98
KSZ8895MQX/RQX/FQX/MLX 7.7 MDC/MDIO Timing FIGURE 7-14: TABLE 7-9: MDC/MDIO TIMING MDC/MDIO TYPICAL TIMING PARAMETERS Symbol Parameter Min. Typ. Max. Units tP MDC period — 400 — ns tMD1 MDIO (PHY input) setup to rising edge of MDC 10 — — ns tMD2 MDIO (PHY input) gold from rising edge of MDC 4 — — ns tMD3 MDIO (PHY output) delay from rising edge of MDC — 222 — ns DS00002246A-page 98  2016 Microchip Technology Inc.
PAGE 99
KSZ8895MQX/RQX/FQX/MLX 7.8 Reset Timing FIGURE 7-15: TABLE 7-10: RESET TIMING DIAGRAM RESET TIMING PARAMETERS Symbol Parameter Min. Typ. Max. Units tSR Stable Supply Voltages to Reset High 10 — — ms tCS Configuration Setup Time 50 — — ns tCH Configuration Hold Time 50 — — ns tRC Reset to Strap-In Pin Output 50 — — ns tVR 3.3V Rise Time 100 — — µs  2016 Microchip Technology Inc.
PAGE 100
KSZ8895MQX/RQX/FQX/MLX 8.0 RESET CIRCUIT A discreet reset circuit, as shown in Figure 8-1, is recommended for the power-up reset circuit. FIGURE 8-1: RECOMMENDED RESET CIRCUIT VDDIO D1: 1N4148 D1 KSZ8895 5 Nȍ RST# C 10μF Figure 8-2 shows a reset circuit recommended for applications where reset is driven by another device (for example, the CPU or an FPGA). The reset out RST_OUT_n from CPU/FPGA provides the warm reset after power up reset.
PAGE 101
KSZ8895MQX/RQX/FQX/MLX 9.0 SELECTION OF ISOLATION TRANSFORMER, (Note 9-1) One simple 1:1 isolation transformer is needed at the line interface. An isolation transformer with integrated commonmode choke is recommended for exceeding FCC requirements at line side. Request to separate the center taps of RX/ TX at chip side. Table 9-1 gives recommended transformer characteristics.
PAGE 102
KSZ8895MQX/RQX/FQX/MLX 10.0 PACKAGE OUTLINE FIGURE 10-1: Note: 128-LEAD LQFP 14 MM X 14 MM PACKAGE For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging. DS00002246A-page 102  2016 Microchip Technology Inc.
PAGE 103
KSZ8895MQX/RQX/FQX/MLX FIGURE 10-2: Note: 128-LEAD PQFP 14 MM X 20 MM PACKAGE For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging.  2016 Microchip Technology Inc.
PAGE 104
KSZ8895MQX/RQX/FQX/MLX APPENDIX A: TABLE A-1: DATA SHEET REVISION HISTORY REVISION HISTORY Revision DS00002246A (08-12-16) DS00002246A-page 104 Section/Figure/Entry — Correction Converted Micrel data sheet KSZ8895MQX/RQX/ FQX/MLX to Microchip DS00002246A. Minor text changes throughout.  2016 Microchip Technology Inc.
PAGE 105
KSZ8895MQX/RQX/FQX/MLX THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
PAGE 106
KSZ8895MQX/RQX/FQX/MLX PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X X X X Device Interface Package Special Temp.
PAGE 107
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PAGE 108
Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.