KS8999 Integrated 9-Port 10/100 Switch with PHY and Frame Buffer Rev 1.14 General Description The KS8999 contains eight 10/100 physical layer transceivers, nine MAC (Media Access Control) units with an integrated layer 2 switch. The device runs in two modes. The first mode is an eight port integrated switch and the second is as a nine port switch with the ninth port available through an MII (Media Independent Interface).
Micrel, Inc.
Micrel, Inc. KS8999 Revision History Revision Date Summary of Changes 1.00 11/27/00 Preliminary Release 1.01 03/30/01 Update maximum frame size Update EEPROM priority descriptions Update I/O pin definition Update I/O descriptions Update Electrical Characteristics 1.02 04/20/01 Correct timing information 1.03 05/11/01 Add MDI/MDI-X description 1.04 06/22/01 Change electrical requirements 1.05 0/6/25/01 Correct I/O descriptions 1.
Micrel, Inc. KS8999 Contents System Level Applications.............................................................................................................................................6 Pin Configuration ............................................................................................................................................................7 Pin Description .........................................................................................................................
Micrel, Inc. KS8999 EEPROM Memory Map..................................................................................................................................................29 General Control Register ..........................................................................................................................................29 Priority Classification Control –802.1p tag field ........................................................................................................
Micrel, Inc. KS8999 network access. The major benefits of using the KS8999 are the lower power consumption, unmanaged operation, flexible configuration, built in frame buffering, VLAN abilities and traffic priority control. Two such applications are depicted below. System Level Applications The KS8999 can be configured to fit either in an eight port 10/100 application or as a nine port 10/100 network interface with an extra MII/7-wire port.
Micrel, Inc.
Micrel, Inc. KS8999 Pin Description Pin Number Pin Name Type(1) 1 VDD_RX Pwr 2.0V for equalizer 2 GND_RX GND Ground for equalizer 3 GND_RX GND Ground for equalizer 4 VDD_RX Pwr 2.
Micrel, Inc.
Micrel, Inc. KS8999 Pin Number Pin Name Type(1) 78 VDD_RCV Pwr 2.0V for clock recovery circuit 79 VDD_RCV Pwr 2.
Micrel, Inc. KS8999 Pin Number Pin Name Type(1) Port 117 LED[2][1] Ipu/O 2 LED indicator 1 118 LED[2][0] Ipu/O 2 LED indicator 0 119 MRXDV Opd 9 MII receive data valid 120 MRXD[3] Opu 9 MII receive bit 3 121 MRXD[2] Opu 9 MII receive bit 2 122 MRXD[1] Opu 9 MII receive bit 1 123 MRXD[0] Opu 9 MII receive bit 0 124 MRXC Ipu/O 9 MII receive clock 125 VDD-IO Pwr 2.0V, 2.5V or 3.
Micrel, Inc. KS8999 Pin Number Pin Name Type(1) 156 IO_SWM Ipu Factory test pin –tie high for normal operation 157 VDD Pwr 2.
Micrel, Inc. KS8999 Pin Number Pin Name Type(1) 195 GND_RX GND 196 RXP[1] I 1 Physical receive signal + (differential) 197 RXM[1] I 1 Physical receive signal - (differential) 198 GND_TX GND 199 TXP[1] O 1 Physical transmit signal + (differential) 200 TXM[1] O 1 Physical transmit signal - (differential) 201 VDD_TX Pwr 2.0V for transmit circuitry 202 VDD_TX Pwr 2.
Micrel, Inc.
Micrel, Inc.
Micrel, Inc.
Micrel, Inc. Group KS8999 I/O Names Active Status LED[7][3] Programs flow control D = No flow control, F/U = Flow control enabled (default) Programs broadcast storm protection. D = 5% broadcast frames allowed, F/U = Unlimited broadcast frames (default) Programs buffer sharing feature. D = Equal amount of buffers per port (113 buffers), F/U = Share buffers up to 512 buffers on a single port (default) Reserved – use float configuration LED[7][2] LED[7][1] LED[7][0] LED[8][3] Programs address aging.
Micrel, Inc.
Micrel, Inc. KS8999 Functional Overview: Physical Layer Transceiver 100BaseTX Transmit The 100BaseTX transmit function performs parallel to serial conversion, 4B/5B coding, scrambling, NRZ to NRZI conversion, MLT3 encoding and transmission. The circuit starts with a parallel to serial conversion, which converts the data from the MAC into a 125MHz serial bit stream. The data and control stream is then converted into 4B/5B coding followed by a scrambler.
Micrel, Inc. KS8999 and a PLL perform the decoding function. The Manchester-encoded data stream is separated into clock signal and NRZ data. A squelch circuit rejects signals with levels less than 400mV or with short pulse widths in order to prevent noises at the RXP or RXM input from falsely triggering the decoder. When the input exceeds the squelch limit, the PLL locks onto the incoming signal and the KS8999 decodes a data frame.
Micrel, Inc. KS8999 Functional Overview: Switch Core Address Look-Up The internal look-up table stores MAC addresses and their associated information. It contains 1K full CAM with 48-bit address plus switching information. The KS8999 is guaranteed to learn 1K addresses and distinguishes itself from hash-based lookup tables which, depending on the operating environment and probabilities, may not guarantee the absolute number of addresses it can learn.
Micrel, Inc. KS8999 MAC Operation The KS8999 strictly abides by IEEE 802.3 standard to maximize compatibility. Inter Packet Gap (IPG) If a frame is successfully transmitted, the 96 bit time IPG is measured between the two consecutive MTXEN. If the current packet is experiencing collision, the 96 bit time IPG is measured from MCRS and the next MTXEN. Backoff Algorithm The KS8999 implements the IEEE Std 802.3 binary exponential back-off algorithm, and optional “aggressive mode” back off.
Micrel, Inc. KS8999 MII Interface Operation The MII (Media Independent Interface) operates in either a MAC or PHY mode. In the MAC mode, the KS8999 MII acts like a MAC and in the PHY mode, it acts like a PHY device. This interface is specified by the IEEE 802.3 committee and provides a common interface between physical layer and MAC layer devices. There are two distinct groups, one being for transmission and the other for receiving.
Micrel, Inc. KS8999 Note that the signal MRXER is not provided on the MII interface for the KS8999 for PHY mode operation and MTXER is not represented for MAC mode. Normally this would indicate a receive / transmit error coming from the physical layer /MAC device, but is not appropriate for this configuration. If the connecting device has a MRXER pin, this should be tied low on the other device for reverse or if it has a MTXER pin in the forward mode it should also be tied low on the other device.
Micrel, Inc. KS8999 SNI Interface (7-wire) Operation The SNI (Serial Network Interface) is compatible with some controllers used for network layer protocol processing. KS8999 acts like a PHY device to external controllers. This interface can be directly connected to these types of devices. The signals are divided into two groups, one being for transmission and the other being the receive side. The signals involved are described in the table below.
Micrel, Inc. KS8999 is Priority Control Scheme (register 2 bits 2-3) which controls the interleaving of high and low priority frames. Options allow from a 2:1 ratio up to a setting that sends all the high priority first. This setting controls all ports globally. Another global feature is Priority Buffer Reserve (register 2 bit 1). If this is set, there is a 6KB (10%) buffer dedicated to high priority traffic, otherwise if cleared the buffer is shared between all traffic.
Micrel, Inc. KS8999 The table below briefly summarizes VLAN features. For more detailed settings see the EEPROM register description. Register(s) Bit(s) Global/Port Description 4-12 2 Port Insert VLAN Tags: If specified, will add VLAN tags to frames without existing tags 4-12 1 Port Strip VLAN Tags: If specified, will remove VLAN tags from frames if they exist 2 0 Global 13-21 7-0 Port VLAN Mask Registers: Allows configuration of individual VLAN grouping.
Micrel, Inc. KS8999 Optional CPU Interface Instead of using an EEPROM to program the KS8999, one can use an external processor. To utilize this feature, the CFGMODE pin (only available on the 208 pin package) needs to pulled low. This makes the KS8999 serial and clock interface into a slave rather than a master. In this mode, clock and data are sourced from the processor. Due to timing constraints, the maximum clock speed that the processor can generate is 8MHz.
Micrel, Inc. KS8999 EEPROM Memory Address Name Description 0 7-0 Signature byte 1. Value = “55” Default (chip) Value 0x55 1 7-0 Signature byte 2.
Micrel, Inc. Address KS8999 Name Description Default (chip) Value Port 2 Control Register 5 7-6 Reserved –set to zero 00 5 5 0 5 4 5 3 5 2 5 1 5 0 TOS priority classification enable for port 2 1 = Enable 0 = Disable 802.
Micrel, Inc. KS8999 Address Name Description 7 1 7 0 Strip VLAN tags for port 4 if existent 1 = Enable 0 = Disable Enable high and low output priority queues for port 4 1 = Enable 0 = Disable Default (chip) Value 0 0 Port 5 Control Register 8 7-6 Reserved –set to zero 00 8 5 0 8 4 8 3 8 2 8 1 8 0 TOS priority classification enable for port 5 1 = Enable 0 = Disable 802.
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Micrel, Inc.
Micrel, Inc.
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Micrel, Inc.
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Micrel, Inc. KS8999 Absolute Maximum Ratings(1) Operating Ratings(2) Supply Voltage (VDD_RX, VDD_TX, VDD_RCV, VDD, VDD_PLLTX,) ....................................... –0.5V to +2.3V (VDDIO) ............................................. –0.5V to +3.8V Input Voltage ......................................... –0.5V to +4.0V Output Voltage ...................................... –0.5V to +4.0V Lead Temperature (soldering, 10 sec) ................ 270°C Storage Temperature (TS) ..................
Micrel, Inc. Symbol KS8999 Parameter Condition Min Typ Max Units ±0.5 ns 5 % 100BaseTX Transmit (measured differentially after 1:1 transformer) Duty Cycle Distortion Overshoot VSET Reference Voltage of ISET Output Jitters 0.75 V Peak-to-peak 0.7 1.4 ns 5MHz square wave 400 mV 2.
Micrel, Inc. KS8999 Timing Diagrams Figure 7. EEPROM Input Timing Symbol Parameter Min Typ Max tCYC Clock Cycle tS Set-Up Time 20 ns tH Hold Time 20 ns 16384 Units ns Table 5. EEPROM Input Timing Parameters Figure 8. EEPROM Output Timing Symbol Parameter tCYC Clock Cycle tOV Output Valid Min Typ Max 16384 4096 4112 Units ns 4128 ns Table 6.
Micrel, Inc. KS8999 Figure 9. SNI (7-wire) Input Timing Symbol Parameter Min Typ Max tCYC Clock Cycle tS Set-Up Time 10 ns tH Hold Time 0 ns 100 Units ns Table 7. SNI (7-wire) Input Parameters Figure 10. SNI (7-wire) Output Timing Symbol Parameter tCYC Clock Cycle tOV Output Valid Min Typ Max 100 0 3 Units ns 6 ns Table 8.
Micrel, Inc. KS8999 Figure 11. KS8999 PHY Mode―Data Sent from External MAC Controller to KS8999 Figure 12. KS8999 PHY Mode Receive Timing Symbol Parameter Min Typ Max Units tCYC Clock Cycle (100BaseT) 40 ns tCYC Clock Cycle (10BaseT) 400 ns tS Set-Up Time 10 ns TH Hold Time 0 ns Table 9.
Micrel, Inc. KS8999 Figure 13. KS8999 PHY Mode―Data Sent from KS8999 PHY Mode to External MAC Controller Figure 14 KS8999 PHY Mode Transmit Timing Symbol Parameter Min Typ Max Units tCYC Clock Cycle (100BaseT) 40 ns tCYC Clock Cycle (10BaseT) 400 ns tOV Output Valid 18 25 28 ns Table 10.
Micrel, Inc. KS8999 Figure 15. KS8999 MAC Mode―Data Sent from External PHY Device to KS8999 Figure 16. KS8999 MAC Mode Receive Timing Symbol Parameter Min Typ Max Units tCYC Clock Cycle (100BaseT) 40 ns tCYC Clock Cycle (10BaseT) 400 ns tS Output Valid 10 ns tH Output Valid 5 ns Table 11.
Micrel, Inc. KS8999 Figure 17. KS8999 MAC Mode Timing―Data Sent from KS8999 MAC mode to External PHY Device Figure 18. KS8999 MAC Mode Transit Timing Symbol Parameter Min Typ Max Units tCYC Clock Cycle (100BaseT) 40 ns tCYC Clock Cycle (10BaseT) 400 ns tOV Output Valid 7 11 16 ns Table 12.
Micrel, Inc. KS8999 Reference Circuits See “I/O Description” section for pull-up/pull-down and float information. Figure 19. Unmanaged Programming Circuit Reset Reference Circuit Micrel recommended the following discrete reset circuit as shown in Figure 20 when powering up the KS8999 device. For the application where the reset circuit signal comes from another device (e.g., CPU, FPGA, etc), we recommend the reset circuit as shown in Figure 21. Figure 20.
Micrel, Inc. KS8999 Figure 21. Recommended Circuit for Interfacing with CPU/FPGA Reset At power-on-reset, R, C, and D1 provide the necessary ramp rise time to reset the KS8999 device. The reset out from CPU/FPGA provides warm reset after power up. It is also recommended to power up the VDD core voltage earlier than VDDIO voltage. At worst case, the both VDD core and VDDIO voltages should come up at the same time.
Micrel, Inc. KS8999 4B/5B Coding In 100BaseTX and 100BaseFX the data and frame control are encoded in the transmitter (and decoded in the receiver) using a 4B/5B code. The extra code space is required to encode extra control (frame delineation) points. It is also used to reduce run length as well as supply sufficient transitions for clock recovery. The table below provides the translation for the 4B/5B coding.
Micrel, Inc. KS8999 MLT3 Coding For 100BaseTX operation the NRZI (Non-Return to Zero Invert on ones) signal is line coded as MLT3. The net result of using MLT3 is to reduce the EMI (Electro Magnetic Interference) of the signal over twisted pair media. In NRZI coding, the level changes from high to low or low to high for every “1” bit. For a “0” bit there is no transition. MLT3 line coding transitions through three distinct levels.
Micrel, Inc. KS8999 Selection of Isolation Transformer(1) One simple 1:1 isolation transformer is needed at the line interface. An isolation transformer with integrated commonmode choke is recommended for exceeding FCC requirements. The following table gives recommended transformer characteristics. Characteristics Name Value Turns Ratio Test Condition 1 CT : 1 CT Open-Circuit Inductance (min.) 350µH 100mV, 100 KHz, 8mA Leakage Inductance (max.) 0.4µH 1MHz (min.) Inter-Winding Capacitance (max.
Micrel, Inc.
Micrel, Inc. KS8999 MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.