LAN8710A/LAN8710Ai Small Footprint MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and flexPWR® Technology Highlights Key Benefits • Single-Chip Ethernet Physical Layer Transceiver (PHY) • Comprehensive flexPWR® Technology - Flexible Power Management Architecture - LVCMOS Variable I/O voltage range: +1.6V to +3.6V - Integrated 1.
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LAN8710A/LAN8710AI Table of Contents 1.0 Introduction ..................................................................................................................................................................................... 4 2.0 Pin Description and Configuration .................................................................................................................................................. 6 3.0 Functional Description ............................................................
LAN8710A/LAN8710AI 1.0 INTRODUCTION 1.1 General Terms and Conventions The following is list of the general terms used throughout this document: 1.2 BYTE 8-bits FIFO First In First Out buffer; often used for elasticity buffer MAC Media Access Controller MII Media Independent Interface RMII™ Reduced Media Independent InterfaceTM N/A Not Applicable X Indicates that a logic state is “don’t care” or undefined. RESERVED Refers to a reserved bit field or address.
LAN8710A/LAN8710AI FIGURE 1-1: SYSTEM BLOCK DIAGRAM 10/100 Ethernet MAC MII/ RMII LAN8710A/ LAN8710Ai Mode MDI Transformer RJ45 LED Crystal or Clock Oscillator FIGURE 1-2: MODE[0:2] nRST ARCHITECTURAL OVERVIEW Mode Control Reset Control AutoNegotiation 100M TX Logic 100M Transmitter HP Auto-MDIX RXP/RXN Transmitter RMIISEL TXD[0:3] SMI TXEN Management Control 10M TX Logic 10M Transmitter TXP/TXN MDIX Control TXER XTAL1/CLKIN TXCLK RXDV RXER RXCLK RMII/MII Logic RXD[0:3] PLL
LAN8710A/LAN8710AI 2.
LAN8710A/LAN8710AI TABLE 2-1: MII/RMII SIGNALS Num Pins Name Symbol Buffer Type 1 Transmit Data 0 TXD0 VIS The MAC transmits data to the transceiver using this signal in all modes. 1 Transmit Data 1 TXD1 VIS The MAC transmits data to the transceiver using this signal in all modes. 1 Transmit Data 2 (MII Mode) TXD2 VIS The MAC transmits data to the transceiver using this signal in MII Mode.
LAN8710A/LAN8710AI TABLE 2-1: MII/RMII SIGNALS (CONTINUED) Num Pins Name Symbol Buffer Type 1 Receive Data 0 RXD0 VO8 Bit 0 of the 4 (2 in RMII Mode) data bits that are sent by the transceiver on the receive path. PHY Operating Mode 0 Configuration Strap MODE0 VIS (PU) Combined with MODE1 and MODE2, this configuration strap sets the default PHY mode. Description See Note 2-3 for more information on configuration straps. Note: Refer to Section 3.7.
LAN8710A/LAN8710AI TABLE 2-1: MII/RMII SIGNALS (CONTINUED) Num Pins Name Symbol Buffer Type 1 Receive Error RXER VO8 Description This signal is asserted to indicate that an error was detected somewhere in the frame presently being transferred from the transceiver. Note: This signal is optional in RMII Mode. Receive Data 4 (MII Mode) RXD4 VO8 In Symbol Interface (5B Decoding) mode, this signal is the MII Receive Data 4 signal, the MSB of the received 5-bit symbol code-group.
LAN8710A/LAN8710AI TABLE 2-1: MII/RMII SIGNALS (CONTINUED) Num Pins Name Symbol Buffer Type 1 Carrier Sense / Receive Data Valid (RMII Mode) CRS_DV VO8 Description This signal is asserted to indicate the receive medium is non-idle in RMII Mode. When a 10BASE-T packet is received, CRS_DV is asserted, but RXD[1:0] is held low until the SFD byte (10101011) is received. Note: Per the RMII standard, transmitted data is not looped back onto the receive data pins in 10BASE-T half-duplex mode.
LAN8710A/LAN8710AI TABLE 2-2: NUM PINS LED PINS NAME SYMBOL BUFFER TYPE LED 1 LED1 O12 DESCRIPTION Link activity LED Indication. This pin is driven active when a valid link is detected and blinks when activity is detected. Note: Refer to Section 3.8.1, "LEDs," on page 32 for additional LED information. Regulator Off Configuration Strap REGOFF IS (PD) This configuration strap is used to disable the internal 1.2V regulator. When the regulator is disabled, external 1.2V must be supplied to VDDCR.
LAN8710A/LAN8710AI TABLE 2-3: SERIAL MANAGEMENT INTERFACE (SMI) PINS BUFFER TYPE Num PINs NAME SYMBOL 1 SMI Data Input/Output MDIO VIS/ VOD8 1 SMI Clock MDC VIS TABLE 2-4: DESCRIPTION Serial Management Interface data input/output Serial Management Interface clock ETHERNET PINS Num PINs NAME SYMBOL BUFFER TYPE 1 Ethernet TX/ RX Positive Channel 1 TXP AIO Transmit/Receive Positive Channel 1 1 Ethernet TX/ RX Negative Channel 1 TXN AIO Transmit/Receive Negative Channel 1 1 Ethern
LAN8710A/LAN8710AI TABLE 2-6: ANALOG REFERENCE PINS Num PINs NAME SYMBOL BUFFER TYPE 1 External 1% Bias Resistor Input RBIAS AI DESCRIPTION This pin requires connection of a 12.1k ohm (1%) resistor to ground. Refer to the LAN8710A/LAN8710Ai reference schematic for connection information. Note: The nominal voltage is 1.2V and the resistor will dissipate approximately 1mW of power. TABLE 2-7: POWER PINS Num PINs NAME SYMBOL BUFFER TYPE 1 +1.6V to +3.6V Variable I/O Power VDDIO P +1.
LAN8710A/LAN8710AI 2.
LAN8710A/LAN8710AI TABLE 2-9: BUFFER TYPES (CONTINUED) BUFFER TYPE DESCRIPTION PD 50uA (typical) internal pull-down. Unless otherwise noted in the pin description, internal pulldowns are always enabled. Note: Internal pull-down resistors prevent unconnected inputs from floating. Do not rely on internal resistors to drive signals external to the device. When connected to a load that must be pulled low, an external resistor must be added.
LAN8710A/LAN8710AI 3.0 FUNCTIONAL DESCRIPTION This chapter provides functional descriptions of the various device features. These features have been categorized into the following sections: • • • • • • • • • Transceiver Auto-negotiation HP Auto-MDIX Support MAC Interface Serial Management Interface (SMI) Interrupt Management Configuration Straps Miscellaneous Functions Application Diagrams 3.1 3.1.1 Transceiver 100BASE-TX TRANSMIT The 100BASE-TX transmit data path is shown in Figure 3-1.
LAN8710A/LAN8710AI The first 16 code-groups are referred to by the hexadecimal values of their corresponding data nibbles, 0 through F. The remaining code-groups are given letter designations with slashes on either side. For example, an IDLE code-group is / I/, a transmit error code-group is /H/, etc.
LAN8710A/LAN8710AI TABLE 3-1: 4B/5B CODE TABLE (CONTINUED) CODE GROUP SYM 00010 V INVALID, RXER if during RXDV INVALID 00011 V INVALID, RXER if during RXDV INVALID 00101 V INVALID, RXER if during RXDV INVALID 01000 V INVALID, RXER if during RXDV INVALID 01100 V INVALID, RXER if during RXDV INVALID 10000 V INVALID, RXER if during RXDV INVALID 3.1.1.
LAN8710A/LAN8710AI 3.1.2 100BASE-TX RECEIVE The 100BASE-TX receive data path is shown in Figure 3-2. Each major block is explained in the following subsections.
LAN8710A/LAN8710AI Special logic in the descrambler ensures synchronization with the remote transceiver by searching for IDLE symbols within a window of 4000 bytes (40us). This window ensures that a maximum packet size of 1514 bytes, allowed by the IEEE 802.3 standard, can be received with no interference. If no IDLE-symbols are detected within this time-period, receive operation is aborted and the descrambler re-starts the synchronization process. 3.1.2.
LAN8710A/LAN8710AI In RMII mode, the 2-bit data nibbles are sent to the RMII block. These data nibbles are clocked to the controller at a rate of 50MHz. The controller samples the data on the rising edge of XTAL1/CLKIN (REF_CLK). To ensure that the setup and hold requirements are met, the nibbles are clocked out of the transceiver on the falling edge of XTAL1/CLKIN (REF_CLK). 3.1.3 10BASE-T TRANSMIT Data to be transmitted comes from the MAC layer controller.
LAN8710A/LAN8710AI 3.1.4.2 Manchester Decoding The output of the SQUELCH goes to the 10M RX block where it is validated as Manchester encoded data. The polarity of the signal is also checked. If the polarity is reversed (local RXP is connected to RXN of the remote partner and vice versa), the condition is identified and corrected. The reversed condition is indicated by the XPOL bit of the Special Control/Status Indications Register.
LAN8710A/LAN8710AI On detection of one of these events, the transceiver begins auto-negotiation by transmitting bursts of Fast Link Pulses (FLP), which are bursts of link pulses from the 10M transmitter. They are shaped as Normal Link Pulses and can pass uncorrupted down CAT-3 or CAT-5 cable. A Fast Link Pulse Burst consists of up to 33 pulses. The 17 odd-numbered pulses, which are always present, frame the FLP burst.
LAN8710A/LAN8710AI 3.2.3 DISABLING AUTO-NEGOTIATION Auto-negotiation can be disabled by setting the Auto-Negotiation Enable bit of the Basic Control Register to zero. The device will then force its speed of operation to reflect the information in the Basic Control Register (Speed Select bit and Duplex Mode bit). These bits should be ignored when auto-negotiation is enabled. 3.2.4 HALF VS.
LAN8710A/LAN8710AI 3.4.1 MII The MII includes 16 interface signals: • • • • • • • • • • transmit data - TXD[3:0] transmit strobe - TXEN transmit clock - TXCLK transmit error - TXER/TXD4 receive data - RXD[3:0] receive strobe - RXDV receive clock - RXCLK receive error - RXER/RXD4/PHYAD0 collision indication - COL carrier sense - CRS In MII mode, on the transmit path, the transceiver drives the transmit clock, TXCLK, to the controller.
LAN8710A/LAN8710AI 3.4.2.2 Reference Clock (REF_CLK) The RMII REF_CLK is a continuous clock that provides the timing reference for CRS_DV, RXD[1:0], TXEN, TXD[1:0] and RXER. The device uses REF_CLK as the network clock such that no buffering is required on the transmit data path. However, on the receive data path, the receiver recovers the clock from the incoming data stream, and the device uses elasticity buffering to accommodate for differences between the recovered clock and the local REF_CLK. 3.4.2.
LAN8710A/LAN8710AI 3.5 Serial Management Interface (SMI) The Serial Management Interface is used to control the device and obtain its status. This interface supports registers 0 through 6 as required by Clause 22 of the 802.3 standard, as well as “vendor-specific” registers 16 to 31 allowed by the specification. Non-supported registers (such as 7 to 15) will be read as hexadecimal “FFFF”. Device registers are detailed in Section 4.0, "Register Descriptions," on page 43.
LAN8710A/LAN8710AI 3.6.1 PRIMARY INTERRUPT SYSTEM The Primary interrupt system is the default interrupt mode (ALTINT bit of the Mode Control/Status Register is “0”). The Primary interrupt system is always selected after power-up or hard reset. In this mode, to set an interrupt, set the corresponding mask bit in the Interrupt Mask Register (see Table 3-3). Then when the event to assert nINT is true, the nINT output will be asserted.
LAN8710A/LAN8710AI For example, setting the INT7 bit in the Interrupt Mask Register will enable the ENERGYON interrupt. After a cable is plugged in, the ENERGYON bit in the Mode Control/Status Register goes active and nINT will be asserted low. To deassert the nINT interrupt output, either clear the ENERGYON bit in the Mode Control/Status Register by removing the cable and then writing a ‘1’ to the INT7 bit in the Interrupt Mask Register, OR clear the INT7 mask (bit 7 of the Interrupt Mask Register).
LAN8710A/LAN8710AI The device’s SMI address may be configured using hardware configuration to any value between 0 and 7. The user can configure the PHY address using Software Configuration if an address greater than 7 is required. The PHY address can be written (after SMI communication at some address is established) using the PHYAD bits of the Special Modes Register. The PHYAD[2:0] configuration straps are multiplexed with other signals as shown in Table 3-5. TABLE 3-5: 3.7.
LAN8710A/LAN8710AI TABLE 3-6: MODE[2:0] BUS Default Register Bit Values MODE[2:0] Mode Definitions Register 0 Register 4 [13,12,10,8] [8,7,6,5] 000 10Base-T Half Duplex. Auto-negotiation disabled. 0000 N/A 001 10Base-T Full Duplex. Auto-negotiation disabled. 0001 N/A 010 100Base-TX Half Duplex. Auto-negotiation disabled. CRS is active during Transmit & Receive. 1000 N/A 011 100Base-TX Full Duplex. Auto-negotiation disabled. CRS is active during Receive.
LAN8710A/LAN8710AI 3.7.4 REGOFF: INTERNAL +1.2V REGULATOR CONFIGURATION The incorporation of flexPWR technology provides the ability to disable the internal +1.2V regulator. When the regulator is disabled, an external +1.2V must be supplied to the VDDCR pin. Disabling the internal +1.2V regulator makes it possible to reduce total system power, since an external switching regulator with greater efficiency (versus the internal linear regulator) can be used to provide +1.2V to the transceiver circuitry.
LAN8710A/LAN8710AI 3.8.1.1 REGOFF and LED1 Polarity Selection The REGOFF configuration strap is shared with the LED1 pin. The LED1 output will automatically change polarity based on the presence of an external pull-up resistor. If the LED1 pin is pulled high to VDD2A by an external pull-up resistor to select a logical high for REGOFF, then the LED1 output will be active low.
LAN8710A/LAN8710AI 3.8.2 VARIABLE VOLTAGE I/O The device’s digital I/O pins are variable voltage, allowing them to take advantage of low power savings from shrinking technologies. These pins can operate from a low I/O voltage of +1.62V up to +3.6V. The applied I/O voltage must maintain its value with a tolerance of ± 10%. Varying the voltage up or down after the transceiver has completed power-on reset can cause errors in the transceiver operation. Refer to Section 5.
LAN8710A/LAN8710AI 3.8.6 CARRIER SENSE The carrier sense (CRS) is output on the CRS pin in MII mode, and the CRS_DV pin in RMII mode. CRS is a signal defined by the MII specification in the IEEE 802.3u standard. The device asserts CRS based only on receive activity whenever the transceiver is either in repeater mode or full-duplex mode. Otherwise the transceiver asserts CRS based on either transmit or receive activity.
LAN8710A/LAN8710AI is routed through the PCS and PMA layers into the PMD sublayer before it is looped back. The COL signal will be inactive in this mode, unless Collision Test is enabled in the Basic Control Register. The transmitters are powered down regardless of the state of TXEN. FIGURE 3-9: NEAR-END LOOPBACK BLOCK DIAGRAM TXD 10/100 Ethernet MAC X RXD Digital X Analog TX RX XFMR CAT-5 SMSC Ethernet Transceiver 3.8.9.
LAN8710A/LAN8710AI 3.8.9.3 Connector Loopback The device maintains reliable transmission over very short cables, and can be tested in a connector loopback as shown in Figure 3-11. An RJ45 loopback cable can be used to route the transmit signals an the output of the transformer back to the receiver inputs, and this loopback will work at both 10 and 100. FIGURE 3-11: 10/100 Ethernet MAC CONNECTOR LOOPBACK BLOCK DIAGRAM TXD TX RXD RX Digital Analog SMSC Ethernet Transceiver 3.
LAN8710A/LAN8710AI 3.9.1 SIMPLIFIED SYSTEM LEVEL APPLICATION DIAGRAM FIGURE 3-12: SIMPLIFIED SYSTEM LEVEL APPLICATION DIAGRAM LAN8710A/LAN8710Ai 10/100 PHY 32-QFN MII MDIO MII MDC nINT Mag TXD[3:0] RJ45 TXP TXN 4 TXCLK TXER TXEN RXP RXN RXD[3:0] 4 RXCLK RXDV XTAL1/CLKIN 25MHz LED[2:1] XTAL2 2 nRST Interface DS00002164B-page 38 2016 Microchip Technology Inc.
LAN8710A/LAN8710AI 3.9.2 POWER SUPPLY DIAGRAM (1.2V SUPPLIED BY INTERNAL REGULATOR) FIGURE 3-13: POWER SUPPLY DIAGRAM (1.2V SUPPLIED BY INTERNAL REGULATOR) LAN8710A/LAN8710Ai 32-QFN Ch.2 3.3V Circuitry Core Logic VDDCR OUT 470 pF 1 uF VDDDIO Supply 1.8 - 3.3V Internal Regulator IN VDD2A CBYPASS Ch.1 3.3V Circuitry VDDIO CF Power Supply 3.3V VDD1A CBYPASS CBYPASS RBIAS LED1/ REGOFF VSS 12.1k ~270 Ohm 2016 Microchip Technology Inc.
LAN8710A/LAN8710AI 3.9.3 POWER SUPPLY DIAGRAM (1.2V SUPPLIED BY EXTERNAL SOURCE) FIGURE 3-14: POWER SUPPLY DIAGRAM (1.2V SUPPLIED BY EXTERNAL SOURCE) LAN8710A/LAN8710Ai 32-QFN Ch.2 3.3V Circuitry Core Logic VDDCR Supply 1.2V VDDCR OUT 470 pF 1 uF VDDDIO Supply 1.8 - 3.3V Internal Regulator VDD2A IN (Disabled) CBYPASS VDD1A Ch.1 3.3V Circuitry VDDIO CF Power Supply 3.3V CBYPASS CBYPASS RBIAS LED1/ REGOFF VSS 12.1k ~270 Ohm 10k DS00002164B-page 40 2016 Microchip Technology Inc.
LAN8710A/LAN8710AI 3.9.4 TWISTED-PAIR INTERFACE DIAGRAM (SINGLE POWER SUPPLY) FIGURE 3-15: TWISTED-PAIR INTERFACE DIAGRAM (SINGLE POWER SUPPLY) LAN8710A/LAN8710Ai 32-QFN Power Supply 3.3V Ferrite bead 49.9 Ohm Resistors VDD2A CBYPASS VDD1A CBYPASS Magnetics RJ45 TXP 1 2 3 4 5 6 7 8 75 TXN RXP 75 RXN 1000 pF 3 kV CBYPASS 2016 Microchip Technology Inc.
LAN8710A/LAN8710AI 3.9.5 TWISTED-PAIR INTERFACE DIAGRAM (DUAL POWER SUPPLIES) FIGURE 3-16: TWISTED-PAIR INTERFACE DIAGRAM (DUAL POWER SUPPLIES) LAN8710A/LAN8710Ai 32-QFN Power Supply 3.3V Power Supply 2.5V - 3.3V 49.9 Ohm Resistors VDD2A CBYPASS VDD1A CBYPASS Magnetics RJ45 TXP 1 2 3 4 5 6 7 8 75 TXN RXP 75 RXN 1000 pF 3 kV CBYPASS DS00002164B-page 42 2016 Microchip Technology Inc.
LAN8710A/LAN8710AI 4.0 REGISTER DESCRIPTIONS This chapter describes the various control and status registers (CSRs). All registers follow the IEEE 802.3 (clause 22.2.4) management register set. All functionality and bit definitions comply with these standards. The IEEE 802.3 specified register index (in decimal) is included with each register definition, allowing for addressing of these registers via the Serial Management Interface (SMI) protocol. 4.
LAN8710A/LAN8710AI TABLE 4-2: SMI REGISTER MAP Register Index (Decimal) 4.2.
LAN8710A/LAN8710AI Bits Description Type Default 11 Power Down 0 = normal operation 1 = General power down mode The Auto-Negotiation Enable must be cleared before setting the Power Down. R/W 0b 10 Isolate 0 = normal operation 1 = electrical isolation of PHY from the MII/RMII R/W 0b 9 Restart Auto-Negotiate 0 = normal operation 1 = restart auto-negotiate process Bit is self-clearing. R/W SC 0b 8 Duplex Mode 0 = half duplex 1 = full duplex Ignored if Auto-Negotiation is enabled (0.12 = 1).
LAN8710A/LAN8710AI Bits Description Type Default 10 100BASE-T2 Full Duplex 0 = PHY not able to perform full duplex 100BASE-T2 1 = PHY able to perform full duplex 100BASE-T2 RO 0b 9 100BASE-T2 Half Duplex 0 = PHY not able to perform half duplex 100BASE-T2 1 = PHY able to perform half duplex 100BASE-T2 RO 0b 8 Extended Status 0 = no extended status information in register 15 1 = extended status information in register 15 RO 0b RESERVED RO — 5 Auto-Negotiate Complete 0 = auto-negotiate proc
LAN8710A/LAN8710AI Bits Type Default PHY ID Number Assigned to the 19th through 24th bits of the OUI. R/W 110000b 9:4 Model Number Six-bit manufacturer’s model number. R/W 001111b 3:0 Revision Number Four-bit manufacturer’s revision number. R/W Note 4-2 15:10 Note 4-2 4.2.5 Description The default value of this field will vary dependent on the silicon revision number.
LAN8710A/LAN8710AI Bits 4:0 Note 4-3 4.2.6 Description Selector Field 00001 = IEEE 802.3 Default R/W 00001b The default value of this bit is determined by the MODE[2:0] configuration straps. Refer to Section 3.7.2, MODE[2:0]: Mode Configuration for additional information.
LAN8710A/LAN8710AI 4.2.
LAN8710A/LAN8710AI Bits Type Default RESERVED RO — ALTINT Alternate Interrupt Mode: 0 = Primary interrupt system enabled (Default) 1 = Alternate interrupt system enabled Refer to Section 3.6, Interrupt Management for additional information. R/W 0b RESERVED RO — 1 ENERGYON Indicates whether energy is detected. This bit transitions to “0” if no valid energy is detected within 256ms. It is reset to “1” by a hardware reset and is unaffected by a software reset. Refer to Section 3.8.3.
LAN8710A/LAN8710AI 4.2.10 SYMBOL ERROR COUNTER REGISTER Index (In Decimal): 26 Size: 16 bits Bits Description Type Default 15:0 SYM_ERR_CNT The symbol error counter increments whenever an invalid code symbol is received (including IDLE symbols) in 100BASE-TX mode. The counter is incremented only once per packet, even when the received packet contains more than one symbol error. This counter increments up to 65,536 (216) and rolls over to 0 after reaching the maximum value.
LAN8710A/LAN8710AI Bits 15:8 Description RESERVED Type Default RO — 7 INT7 0 = not source of interrupt 1 = ENERGYON generated RO/LH 0b 6 INT6 0 = not source of interrupt 1 = Auto-Negotiation complete RO/LH 0b 5 INT5 0 = not source of interrupt 1 = Remote Fault Detected RO/LH 0b 4 INT4 0 = not source of interrupt 1 = Link Down (link status negated) RO/LH 0b 3 INT3 0 = not source of interrupt 1 = Auto-Negotiation LP Acknowledge RO/LH 0b 2 INT2 0 = not source of interrupt 1 = Paralle
LAN8710A/LAN8710AI 4.2.14 PHY SPECIAL CONTROL/STATUS REGISTER Index (In Decimal): 31 Bits Size: 16 bits Type Default RESERVED RO — Autodone Auto-negotiation done indication: 0 = Auto-negotiation is not done or disabled (or not active) 1 = Auto-negotiation is done RO 0b RESERVED R/W — 6 Enable 4B5B 0 = bypass encoder/decoder 1 = enable 4B5B encoding/decoding. MAC Interface must be configured in MII mode.
LAN8710A/LAN8710AI 5.0 OPERATIONAL CHARACTERISTICS 5.1 Absolute Maximum Ratings* Supply Voltage (VDDIO, VDD1A, VDD2A) (Note 5-1) ............................................................................... -0.5V to +3.6V Digital Core Supply Voltage (VDDCR) (Note 5-1) ...................................................................................... -0.5V to +1.5V Ethernet Magnetics Supply Voltage .....................................................................................................
LAN8710A/LAN8710AI 5.3 Power Consumption This section details the device power measurements taken over various operating conditions. Unless otherwise noted, all measurements were taken with power supplies at nominal values (VDDIO, VDD1A, VDD2A = 3.3V, VDDCR = 1.2V). See Section 3.8.3, Power-Down Modes for a description of the power down modes. TABLE 5-1: DEVICE ONLY CURRENT CONSUMPTION AND POWER DISSIPATION VDDA3.
LAN8710A/LAN8710AI 5.4 DC Specifications TABLE 5-2: details the non-variable I/O buffer characteristics. These buffer types do not support variable voltage operation. TABLE 5-3: details the variable voltage I/O buffer characteristics. Typical values are provided for 1.8V, 2.5V, and 3.3V VDDIO cases. TABLE 5-2: NON-VARIABLE I/O BUFFER CHARACTERISTICS Parameter Symbol Min Low Input Level VILI -0.3 High Input Level VIHI Negative-Going Threshold VILT 1.
LAN8710A/LAN8710AI TABLE 5-3: VARIABLE I/O BUFFER CHARACTERISTICS Parameter 1.8V Typ 2.5V Typ Symbol Min Low Input Level VILI -0.3 High Input Level VIHI Neg-Going Threshold VILT 0.64 0.83 1.15 Pos-Going Threshold VIHT 0.81 0.99 Schmitt Trigger Hysteresis (VIHT - VILT) VHYS 102 158 Input Leakage (VIN = VSS or VDDIO) IIH -10 Input Capacitance 3.3V Typ Max Units Notes VIS Type Input Buffer V 3.6 V 1.41 1.76 V Schmitt trigger 1.29 1.65 1.
LAN8710A/LAN8710AI Note 5-14 TABLE 5-5: Measured differentially. 10BASE-T TRANSCEIVER CHARACTERISTICS Parameter Symbol Min Typ Max Units Notes Transmitter Peak Differential Output Voltage VOUT 2.2 2.5 2.8 V Note 5-15 Receiver Differential Squelch Threshold VDS 300 420 585 mV — Note 5-15 5.5 Min/max voltages guaranteed as measured with 100 resistive load. AC Specifications This section details the various AC timing specifications of the device.
LAN8710A/LAN8710AI 5.5.2 POWER SEQUENCE TIMING This diagram illustrates the device power sequencing requirements. The VDDIO, VDD1A, VDD2A and magnetics power supplies can turn on in any order provided they all reach operational levels within the specified time period tpon. Device power supplies can turn off in any order provided they all reach 0 volts within the specified time period poff.
LAN8710A/LAN8710AI FIGURE 5-3: POWER-ON NRST & CONFIGURATION STRAP TIMING All External Power Supplies 80% tpurstd tpurstv trstia nRST tcss tcsh Configuration Strap Pins Input totaa todad Configuration Strap Pins Output Drive TABLE 5-7: POWER-ON NRST & CONFIGURATION STRAP TIMING VALUES symbol DESCRIPTION min typ max units tpurstd External power supplies at 80% to nRST deassertion 25 — — mS tpurstv External power supplies at 80% to nRST valid 0 — — nS trstia nRST input assertio
LAN8710A/LAN8710AI FIGURE 5-4: MII RECEIVE TIMING tclkp tclkh tclkl RXCLK tval tval thold RXD[3:0] thold tval RXDV Table 1.1 MII Receive Timing Values SYMBOL DESCRIPTION MIN MAX UNITS Note 5-21 — ns NOTES tclkp RXCLK period tclkh RXCLK high time tclkp*0.4 tclkp*0.6 ns tclkl RXCLK low time tclkp*0.4 tclkp*0.6 ns tval RXD[3:0], RXDV output valid from rising edge of RXCLK 28.0 ns Note 5-22 thold RXD[3:0], RXDV output hold from rising edge of RXCLK — ns Note 5-22 10.
LAN8710A/LAN8710AI FIGURE 5-5: MII TRANSMIT TIMING tclkp tclkh tclkl TXCLK tsu thold tsu thold thold TXD[3:0] thold tsu TXEN TABLE 5-8: MII TRANSMIT TIMING VALUES SYMBOL DESCRIPTION MIN MAX UNITS NOTES Note 5-23 — ns — tclkp TXCLK period tclkh TXCLK high time tclkp*0.4 tclkp*0.6 ns — tclkl TXCLK low time tclkp*0.4 tclkp*0.6 ns — tsu TXD[3:0], TXEN setup time to rising edge of TXCLK 12.
LAN8710A/LAN8710AI 5.5.5 RMII INTERFACE TIMING FIGURE 5-6: RMII TIMING tclkp tclkh CLKIN (REF_CLK) tclkl toval RXD[1:0], RXER toval tohold tohold toval CRS_DV tsu tihold tsu tihold tihold TXD[1:0] tihold tsu TXEN TABLE 5-9: RMII TIMING VALUES Symbol Description Min Max Units Notes 20 — ns — tclkp CLKIN period tclkh CLKIN high time tclkp*0.35 tclkp*0.65 ns — tclkl CLKIN low time tclkp*0.35 tclkp*0.
LAN8710A/LAN8710AI 5.5.5.1 RMII CLKIN Requirements TABLE 5-10: RMII CLKIN (REF_CLK) TIMING VALUES Parameter Min Typ Max Units Notes CLKIN frequency 50 — MHz — CLKIN Frequency Drift — ± 50 ppm — — 60 % — — 150 psec p-p – not RMS CLKIN Duty Cycle 40 CLKIN Jitter 5.5.6 SMI TIMING This section specifies the SMI timing of the device. Please refer to Section 3.5, Serial Management Interface (SMI) for additional details.
LAN8710A/LAN8710AI 5.6 Clock Circuit The device can accept either a 25MHz crystal (preferred) or a 25MHz single-ended clock oscillator (±50ppm) input. If the single-ended clock oscillator method is implemented, XTAL2 should be left unconnected and XTAL1/CLKIN should be driven with a nominal 0-3.3V clock signal. It is recommended that a crystal utilizing matching parallel load capacitors be used for the crystal input/output signals (XTAL1/XTAL2). Either a 300uW or 100uW 25MHz crystal may be utilized.
LAN8710A/LAN8710AI Note 5-26 The maximum allowable values for Frequency Tolerance and Frequency Stability are application dependent. Since any particular application must meet the IEEE ±50 PPM Total PPM Budget, the combination of these two values must be approximately ±45 PPM (allowing for aging). Note 5-27 Frequency Deviation Over Time is also referred to as Aging. Note 5-28 The total deviation for the Transmitter Clock Frequency is specified by IEEE 802.3u as ±100 PPM.
LAN8710A/LAN8710AI TABLE 5-13: 100UW 25MHZ CRYSTAL SPECIFICATIONS (CONTINUED) Parameter Symbol Min Nom Max Units Notes Equivalent Series Resistance R1 — — 80 Ohm — XTAL2 Series Resistor Rs 495 500 505 Ohm — Operating Temperature Range — Note 5-35 — +85 XTAL1/CLKIN Pin Capacitance — — 3 typ XTAL2 Pin Capacitance — — 3 typ o C — — pF Note 5-36 — pF Note 5-36 Note 5-31 The maximum allowable values for Frequency Tolerance and Frequency Stability are application depe
LAN8710A/LAN8710AI 6.0 PACKAGE INFORMATION 6.1 32-QFN (Punch) FIGURE 6-1: TABLE 6-1: 32-QFN PACKAGE 32-QFN DIMENSIONS Min Nominal Max A 0.70 0.85 1.00 A1 0 0.02 0.05 A2 — 0.65 0.90 D/E 4.90 5.00 5.10 D1/E1 4.55 4.75 4.95 D2/E2 3.20 3.30 3.40 L 0.30 0.40 0.50 b 0.18 0.25 0.30 k 0.35 0.45 — e 0.50 BSC Note 1: All dimensions are in millimeters unless otherwise noted.
LAN8710A/LAN8710AI FIGURE 6-2: 32-QFN RECOMMENDED PCB LAND PATTERN 2016 Microchip Technology Inc.
LAN8710A/LAN8710AI 6.2 32-SQFN (Sawn) FIGURE 6-3: DS00002164B-page 70 32-SQFN PACKAGE 2016 Microchip Technology Inc.
LAN8710A/LAN8710AI 6.3 Tape & Reel Information FIGURE 6-4: TAPING DIMENSIONS AND PART ORIENTATION FIGURE 6-5: TAPE LENGTH AND PART QUANTITY Note: Standard reel size is 5,000 pieces per reel. 2016 Microchip Technology Inc.
LAN8710A/LAN8710AI FIGURE 6-6: DS00002164B-page 72 REEL DIMENSIONS 2016 Microchip Technology Inc.
LAN8710A/LAN8710AI 7.0 APPLICATION NOTES 7.1 Application Diagram The device requires few external components. The voltage on the magnetics center tap can range from 2.5 - 3.3V. 7.1.1 MII DIAGRAM FIGURE 7-1: SIMPLIFIED APPLICATION DIAGRAM MII MDIO MDC nINT LAN8710 10/100 PHY 32-QFN MII Mag TXD[3:0] RJ45 TXP TXN 4 TXCLK TXER TXEN RXP RXN RXD[3:0] 4 RXCLK RXDV XTAL1/CLKIN 25MHz LED[2:1] XTAL2 2 nRST Interface 7.1.2 POWER SUPPLY DIAGRAM 2016 Microchip Technology Inc.
LAN8710A/LAN8710AI FIGURE 7-2: HIGH-LEVEL SYSTEM DIAGRAM FOR POWER Analog Supply 3.3V Power to magnetics interface. 6 LAN8710 32-QFN VDDCR VDD1A 27 CBYPASS 1uF VDDDIO Supply 1.8 - 3.3V 12 CF VDDIO VDD2A 1 CBYPASS CBYPASS R 19 RBIAS 32 nRST C 12.1k VSS 7.1.3 TWISTED-PAIR INTERFACE DIAGRAM FIGURE 7-4: COPPER INTERFACE DIAGRAM LAN8710 32-QFN Analog Supply 3.3V VDD2A 49.9 Ohm Resistors Magnetic Supply 2.5 - 3.
LAN8710A/LAN8710AI APPENDIX A: TABLE A-1: DATA SHEET REVISION HISTORY REVISION HISTORY Revision Section/Figure/Entry Rev B. (07-15-16) Section 5.1, "Absolute Maximum Ratings*," on page 54 Update to Positive voltage on XTAL1/CLKIN, with respect to ground. Table 5-2, “Non-Variable I/O Buffer Characteristics,” on page 56 Update to min/max values for the last row, ICLK Type Buffer (XTAL1 Input) - High Input Level. All Document converted to Microchip look and feel. Replaces SMSC Rev. 1.4 (08-23-12).
LAN8710A/LAN8710AI THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
LAN8710A/LAN8710AI PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO.
LAN8710A/LAN8710AI NOTES: DS00002164B-page 78 2016 Microchip Technology Inc.
LAN8710A/LAN8710AI Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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