LAN9514/LAN9514i USB 2.0 Hub and 10/100 Ethernet Controller Highlights Key Features (continued) • Four downstream ports, one upstream port • High-Performance 10/100 Ethernet Controller - Four integrated downstream USB 2.0 PHYs - One integrated upstream USB 2.
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LAN9514/LAN9514I Table of Contents 1.0 Introduction ..................................................................................................................................................................................... 4 2.0 Pin Description and Configuration .................................................................................................................................................. 6 3.0 EEPROM Controller (EPC) .............................................................
LAN9514/LAN9514I 1.0 INTRODUCTION 1.1 Block Diagram FIGURE 1-1: INTERNAL BLOCK DIAGRAM LAN9514/LAN9514i JTAG USB DP/DM TAP Controller Upstream USB PHY Downstream USB PHY USB DP/DM 1.1.1 USB 2.0 Hub Downstream USB PHY USB DP/DM 10/100 Ethernet Controller Downstream USB PHY USB DP/DM EEPROM Controller Ethernet PHY EEPROM Ethernet Downstream USB PHY USB DP/DM OVERVIEW The LAN9514/LAN9514i is a high performance Hi-Speed USB 2.0 hub with a 10/100 Ethernet controller.
LAN9514/LAN9514I All required resistors on the USB ports are integrated into the hub. This includes all series termination resistors on D+ and D- pins and all required pull-down and pull-up resistors on D+ and D- pins. The over-current sense inputs for the downstream facing ports have internal pull-up resistors. Four external ports are available for general USB device connectivity. 1.1.
LAN9514/LAN9514I 2.
LAN9514/LAN9514I TABLE 2-1: Num PINs EEPROM PINS Buffer Type Name Symbol 1 EEPROM Data In EEDI IS (PD) This pin is driven by the EEDO output of the external EEPROM. 1 EEPROM Data Out EEDO O8 This pin drives the EEDI input of the external EEPROM. 1 EEPROM Chip Select EECS O8 This pin drives the chip select output of the external EEPROM. 1 EEPROM Clock EECLK O8 This pin drives the EEPROM clock of the external EEPROM.
LAN9514/LAN9514I TABLE 2-3: MISCELLANEOUS PINS Num PINs Name Symbol Buffer Type 1 System Reset nRESET IS Description This active low pin allows external hardware to reset the device. Note: 1 This pin should be tied high if it is not used. Ethernet Full-Duplex Indicator LED nFDX_LED OD12 (PU) This pin is driven low (LED on) when the Ethernet link is operating in full-duplex mode.
LAN9514/LAN9514I TABLE 2-3: Num PINs 1 MISCELLANEOUS PINS (CONTINUED) Name Symbol Buffer Type Detect Upstream VBUS Power VBUS_DET IS_5V Description This pin detects the state of the upstream bus power. The Hub monitors VBUS_DET to determine when to assert the USBDP0 pin's internal pull-up resistor (signaling a connect event). For bus-powered hubs, this pin must be tied to VDD33IO. For self-powered hubs where the device is permanently attached to a host, VBUS_DET should be pulled to VDD33IO.
LAN9514/LAN9514I TABLE 2-4: Num PINs USB PINS (CONTINUED) Name Symbol Buffer Type 1 Downstream USB DMINUS 3 USBDM3 AIO Downstream USB peripheral 3 DMINUS signal. 1 Downstream USB DPLUS 3 USBDP3 AIO Downstream USB peripheral 3 DPLUS signal. 1 Downstream USB DMINUS 4 USBDM4 AIO Downstream USB peripheral 4 DMINUS signal. 1 Downstream USB DPLUS 4 USBDP4 AIO Downstream USB peripheral 4 DPLUS signal. 1 Downstream USB DMINUS 5 USBDM5 AIO Downstream USB peripheral 5 DMINUS signal.
LAN9514/LAN9514I TABLE 2-4: Num PINs USB PINS (CONTINUED) Name Symbol Buffer Type 1 USB PLL +1.8V Power Supply VDD18USBPLL P 1 Crystal Input XI ICLK Description Refer to the LAN9514/LAN9514i reference schematics for additional connection information. External 25 MHz crystal input. Note: 1 Crystal Output TABLE 2-5: Num PINs XO This pin can also be driven by a singleended clock oscillator. When this method is used, XO should be left unconnected OCLK External 25 MHz crystal output.
LAN9514/LAN9514I TABLE 2-6: I/O POWER PINS, CORE POWER PINS, AND GROUND PAD Num PINs Name Symbol Buffer Type 5 +3.3V I/O Power VDD33IO P Description +3.3V Power Supply for I/O Pins. Refer to the LAN9514/LAN9514i reference schematics for connection information. 2 Digital Core +1.8V Power Supply Output VDD18CORE P +1.8V power from the internal core voltage regulator. All VDD18CORE pins must be tied together for proper operation.
LAN9514/LAN9514I TABLE 2-7: 64-QFN PACKAGE PIN ASSIGNMENTS (CONTINUED) Pin Num Pin Name Pin Num Pin Name Pin Num Pin Name Pin Num Pin Name 15 VDD18CORE 31 TDO 47 TEST4 63 USBRBIAS 16 PRTCTL3 32 TCK 48 VDD18ETHPLL 64 VDD33A EXPOSED PAD MUST BE CONNECTED TO VSS 2.1 Power Connections Figure 2-2 illustrates the power connections for LAN9514/LAN9514i. 2009-2016 Microchip Technology Inc.
LAN9514/LAN9514I FIGURE 2-2: POWER CONNECTIONS LAN9514 64-PIN QFN +3.3V Internal Core Regulator 0.1uF VDD33IO +3.3V (IN) +1.8V (OUT) VDD18CORE 4.7uF 0.1uF 0.1uF 0.1uF VDD33IO 0.1uF VDD33IO VDD18CORE Core Logic 0.1uF VDD33IO 0.1uF VDD33IO 2.0A 120 ohm @ 100MHz PLL & Ethernet PHY 0.1uF VDD18ETHPLL 0.1uF VDD33A 0.1uF VDD33A 0.1uF VDD33A 0.1uF 2.0A 120 ohm @ 100MHz Internal USB PLL Regulator +3.3V (IN) +1.8V (OUT) VDD18USBPLL 1.0uF VDD33A 0.1uF VDD33A 0.1uF VDD33A USB PHY 0.
LAN9514/LAN9514I enabled, creating an open drain output. If there is an over-current situation, the USB Power Switch will assert the open drain OCS signal. The Schmitt trigger input will recognize this situation as a low. The open drain output does not interfere. The overcurrent sense filter handles the transient conditions, such as low voltage, while the device is powering up.
LAN9514/LAN9514I current situation, the poly fuse will open. This will cause the cathode of the diode to go to 0_volts. The anode of the diode will be at 0.7_volts, and the Schmidt trigger input will register this as a low, resulting in an overcurrent detection. The open drain output does not interfere.
LAN9514/LAN9514I Many customers use a single poly fuse to power all their devices. For the ganged situation, all power control pins must be tied together. FIGURE 2-5: PORT POWER WITH GANGED CONTROL WITH POLY FUSE 5V Poly Fuse PRTCTL5 PRTCTL4 LAN9514/ LAN9514i PRTCTL3 PRTCTL2 USB Device 2.
LAN9514/LAN9514I TABLE 2-8: BUFFER TYPES (CONTINUED) Buffer Type PD Description 50 μA (typical) internal pull-down. Unless otherwise noted in the pin description, internal pull-downs are always enabled. Note: AI Internal pull-down resistors prevent unconnected inputs from floating. Do not rely on internal resistors to drive signals external to LAN9514/LAN9514i. When connected to a load that must be pulled low, an external resistor must be added.
LAN9514/LAN9514I 3.0 EEPROM CONTROLLER (EPC) LAN9514/LAN9514i may use an external EEPROM to store the default values for the USB descriptors and the MAC address. The EEPROM controller supports most “93C46” type EEPROMs. A total of nine address bits are used to support 256/512 byte EEPROMs. A 3-wire style 2K/4K EEPROM that is organized for 256/512 x 8-bit operation must be used. The MAC address is used as the default Ethernet MAC address and is loaded into the MAC’s ADDRH and ADDRL registers.
LAN9514/LAN9514I TABLE 3-1: EEPROM FORMAT (CONTINUED) EEPROM Address EEPROM Contents 0Eh Product Name String Descriptor Length (bytes) 0Fh Product Name String Descriptor EEPROM Word Offset 10h Serial Number String Descriptor Length (bytes) 11h Serial Number String Descriptor EEPROM Word Offset 12h Configuration String Descriptor Length (bytes) 13h Configuration String Descriptor Word Offset 14h Interface String Descriptor Length (bytes) 15h Interface String Descriptor Word Offset 16h Hi
LAN9514/LAN9514I TABLE 3-1: EEPROM FORMAT (CONTINUED) EEPROM Address Note: EEPROM Contents 2Fh Hub Controller Max Current (Bus) Register (HCMCB) 30h Power-on Time Register (PWRT) 31h Boost_Up Register (BOOSTUP) 32h Boost_5 Register (BOOST5) 33h Boost_4:2 Register (BOOST42) 34h RESERVED 35h Port Swap Register (PRTSP) 36h Port Remap 12 Register (PRTR12) 37h Port Remap 34 Register (PRTR34) 38h Port Remap 5 Register (PRTR5) 39h Status/Command Register (STCD) EEPROM byte addresses past
LAN9514/LAN9514I TABLE 3-3: HUB CONFIGURATION (CONTINUED) EEPROM Offset Description Default 21h Vendor ID MSB (VIDM) Most Significant Byte of the Vendor ID. This is a 16-bit value that uniquely identifies the Vendor of the user device (assigned by USB-Interface Forum). 04h 22h Product ID LSB Register (PIDL) Least Significant Byte of the Product ID. This is a 16-bit value that the Vendor can assign that uniquely identifies this particular product (assigned by the OEM).
LAN9514/LAN9514I TABLE 3-3: HUB CONFIGURATION (CONTINUED) EEPROM Offset 2Ah Description Default Port Disable (Self) Register (PDS) Disables 1 or more ports. 00h 0 = Port is available 1 = Port is disabled During Self-Powered operation, this selects the ports which will be permanently disabled, and are not available to be enabled or enumerated by a host controller.
LAN9514/LAN9514I TABLE 3-3: HUB CONFIGURATION (CONTINUED) EEPROM Offset 2Eh Description Default Hub Controller Max Current (Self) Register (HCMCS) Value in 2 mA increments that the Hub consumes from an upstream port (VBUS) when operating as a self-powered hub. This value includes the hub silicon along with the combined power consumption (from VBUS) of all associated circuitry on the board.
LAN9514/LAN9514I TABLE 3-3: HUB CONFIGURATION (CONTINUED) EEPROM Offset 36h Description Default Port Remap 12 Register (PRTR12) When a hub is enumerated by a USB Host Controller, the hub is only permitted to report how many ports it has. The hub is not permitted to select a numerical range or assignment. The Host Controller will number the downstream ports of the hub starting with the number 1, up to the number of ports that the hub reported having.
LAN9514/LAN9514I TABLE 3-3: HUB CONFIGURATION (CONTINUED) EEPROM Offset 37h Description Default Port Remap 34 Register (PRTR34) When a hub is enumerated by a USB Host Controller, the hub is only permitted to report how many ports it has. The hub is not permitted to select a numerical range or assignment. The Host Controller will number the downstream ports of the hub starting with the number 1, up to the number of ports that the hub reported having.
LAN9514/LAN9514I TABLE 3-3: HUB CONFIGURATION (CONTINUED) EEPROM Offset 38h Description Default Port Remap 5 Register (PRTR5) When a hub is enumerated by a USB Host Controller, the hub is only permitted to report how many ports it has. The hub is not permitted to select a numerical range or assignment. The Host Controller will number the downstream ports of the hub starting with the number 1, up to the number of ports that the hub reported having.
LAN9514/LAN9514I TABLE 3-4: CONFIG DATA BYTE 1 REGISTER (CFG1) FORMAT Bits 7 Description Default Self or Bus Power (SELF_BUS_PWR) Selects between Self or Bus-Powered operation. 1b 0 = Bus-Powered 1 = Self-Powered The Hub is either Self-Powered (draws less than 2 mA of upstream bus power) or Bus-Powered (limited to a 100 mA maximum of upstream power prior to being configured by the host controller).
LAN9514/LAN9514I TABLE 3-4: CONFIG DATA BYTE 1 REGISTER (CFG1) FORMAT (CONTINUED) Bits Description Default 2:1 Over Current Sense (CURRENT_SNS) Selects current sensing on a port-by-port basis, all ports ganged, or none (only for bus-powered hubs) The ability to support current sensing on a port or ganged basis is hardware implementation dependent.
LAN9514/LAN9514I TABLE 3-6: CONFIG DATA BYTE 3 REGISTER (CFG3) FORMAT (CONTINUED) Bits 3 Description Default Port Re-Mapping Enable (PRTMAP_EN) Selects the method used by the Hub to assign port numbers and disable ports. 0b 0 = Standard Mode. The following EEPROM addresses are used to define which ports are enabled.
LAN9514/LAN9514I TABLE 3-9: BOOST_4:2 REGISTER (BOOST42) FORMAT Bits 7:6 Description Default Upstream USB Electrical Signaling Drive Strength Boost Bit for Downstream Port 4 (BOOST_IOUT_4) 00b 00 = Normal electrical drive strength 01 = Elevated electrical drive strength (+4% boost) 10 = Elevated electrical drive strength (+8% boost) 11 = Elevated electrical drive strength (+12% boost) 5:4 Upstream USB Electrical Signaling Drive Strength Boost Bit for Downstream Port 3 (BOOST_IOUT_3) 00b 00 = Norma
LAN9514/LAN9514I 3.2 EEPROM Defaults The signature value of 0xA5 is stored at address 0. A different signature value indicates to the EEPROM controller that no EEPROM or an un-programmed EEPROM is attached to the device. In this case, the hardware default values are used, as shown in Table 3-11.
LAN9514/LAN9514I TABLE 3-12: DUMP OF EEPROM MEMORY (CONTINUED) Offset Byte Value 0008h 04 05 09 04 0A 1D 00 00 0010h 00 00 00 00 00 00 12 22 0018h 12 2B 12 34 12 3D 00 00 0020h 24 04 14 95 00 01 9B 18 0028h 00 02 00 00 01 00 01 00 0030h 32 00 00 00 00 00 21 43 0038h 05 01 0A 03 53 00 4D 00 0040h 53 00 43 00 12 01 00 02 0048h FF 00 01 40 24 04 00 EC 0050h 00 01 01 00 00 01 09 02 0058h 27 00 01 01 00 E0 01 09 0060h 04 00 00 03 FF 00 FF 00 0068h 12 01 00 02 FF 00 FF 40 0070h 24 0
LAN9514/LAN9514I TABLE 3-13: EEPROM EXAMPLE - 256 BYTE EEPROM (CONTINUED) EEPROM Address EEPROM Contents (Hex) 0Ah-0Bh 09 04 0Ch 0A Manufacturer ID String Descriptor Length (10 bytes) 0Dh 1D Manufacturer ID String Descriptor EEPROM Word Offset (1Dh) Corresponds to EEPROM Byte Offset 3Ah 0Eh 00 Product Name String Descriptor Length (0 bytes - NA) 0Fh 00 Product Name String Descriptor EEPROM Word Offset (Don’t Care) 10h 00 Serial Number String Descriptor Length (0 bytes - NA) 11h 00 Ser
LAN9514/LAN9514I TABLE 3-13: EEPROM EXAMPLE - 256 BYTE EEPROM (CONTINUED) EEPROM Address EEPROM Contents (Hex) 28h 00 Config Data Byte 3 Register (CFG3) 29h 02 Non-Removable Devices Register (NRD) 2Ah 00 Port Disable (Self) Register (PDS) 2Bh 00 Port Disable (Bus) Register (PDB) 2Ch 01 Max Power (Self) Register (MAXPS) 2Dh 00 Max Power (Bus) Register (MAXPB) 2Eh 01 Hub Controller Max Current (Self) Register (HCMCS) 2Fh 00 Hub Controller Max Current (Bus) Register (HCMCB) 30h 32
LAN9514/LAN9514I TABLE 3-13: EEPROM EXAMPLE - 256 BYTE EEPROM (CONTINUED) EEPROM Address EEPROM Contents (Hex) 52h 01 Index of Manufacturer String Descriptor 53h 00 Index of Product String Descriptor 54h 00 Index of Serial Number String Descriptor 55h 01 Number of Possible Configurations 56h 09 Size of Hi-Speed Configuration Descriptor in bytes (9 bytes) 57h 02 Descriptor Type (Configuration Descriptor - 02h) 58h-59h 27 00 5Ah 01 Number of Interfaces 5Bh 01 Value to use as an ar
LAN9514/LAN9514I TABLE 3-13: EEPROM EXAMPLE - 256 BYTE EEPROM (CONTINUED) EEPROM Address EEPROM Contents (Hex) 76 01 Index of Manufacturer String Descriptor 77h 00 Index of Product String Descriptor 78h 00 Index of Serial Number String Descriptor 79h 01 Number of Possible Configurations 7Ah 09 Size of Full-Speed Configuration Descriptor in bytes (9 bytes) 7Bh 02 Descriptor Type (Configuration Descriptor - 02h) 7Ch-7Dh 27 00 7Eh 01 Number of Interfaces 7Fh 01 Value to use as an a
LAN9514/LAN9514I 4.0 OPERATIONAL CHARACTERISTICS 4.1 Absolute Maximum Ratings* Supply Voltage (VDD33IO, VDD33A) (Note 4-1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +3.6V Positive voltage on signal pins, with respect to ground (Note 4-2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6V Negative voltage on signal pins, with respect to ground (Note 4-3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LAN9514/LAN9514I 4.3.1 SUSPEND0 TABLE 4-1: SUSPEND0 CURRENT CONSUMPTION AND POWER DISSIPATION (VDD33IO = VDD33A = 3.3V) Parameter Min Typical Max Unit Supply current (VDD33IO, VDD33A) — 74 — mA Power Dissipation (Device Only) — 245 — mW Power Dissipation (Device and Ethernet components) — 379 — mW 4.3.2 SUSPEND1 TABLE 4-2: SUSPEND1 CURRENT CONSUMPTION AND POWER DISSIPATION (VDD33IO = VDD33A = 3.
LAN9514/LAN9514I TABLE 4-4: OPERATIONAL CURRENT CONSUMPTION & POWER DISSIPATION (VDD33IO = VDD33A = 3.
LAN9514/LAN9514I 4.4 DC Specifications TABLE 4-5: I/O BUFFER CHARACTERISTICS Parameter Symbol Min Low Input Level VILI -0.3 High Input Level VIHI Negative-Going Threshold VILT 1.01 Positive-Going Threshold VIHT SchmittTrigger Hysteresis (VIHT - VILT) Typ Max Units Notes IS Type Input Buffer V 3.6 V 1.18 1.35 V Schmitt trigger 1.39 1.6 1.8 V Schmitt trigger VHYS 345 420 485 mV Input Leakage (VIN = VSS or VDD33IO) IIH -10 10 μA Input Capacitance CIN 2.
LAN9514/LAN9514I TABLE 4-5: I/O BUFFER CHARACTERISTICS (CONTINUED) Parameter Symbol Min Typ Max Units Notes ICLK Type Buffer (XI Input) Note 4-8 Low Input Level VILI -0.3 0.5 V High Input Level VIHI 1.4 3.6 V Note 4-6 This specification applies to all inputs and tri-stated bidirectional pins. Internal pull-down and pull-up resistors add +/- 50 μA per-pin (typical). Note 4-7 This is the total 5.5V input leakage for the entire device.
LAN9514/LAN9514I Note: 4.5.1 The USBDP and USBDM pin timing adheres to the USB 2.0 specification. Refer to the Universal Serial Bus Revision 2.0 specification for detailed USB timing information. EQUIVALENT TEST LOAD Output timing specifications assume the 25 pF equivalent test load illustrated in Figure 4-1 below. FIGURE 4-1: OUTPUT EQUIVALENT TEST LOAD OUTPUT 25 pF 4.5.2 RESET TIMING The nRESET pin input assertion time must be a minimum of 1 μS. Assertion of nRESET is not a requirement.
LAN9514/LAN9514I TABLE 4-8: EEPROM TIMING VALUES Symbol Description Min TYP Max Units tckcyc EECLK Cycle time 1110 — 1130 ns tckh EECLK High time 550 — 570 ns tckl EECLK Low time 550 — 570 ns tcshckh EECS high before rising edge of EECLK 1070 — — ns tcklcsl EECLK falling edge to EECS low 30 — — ns tdvckh EEDO valid before rising edge of EECLK 550 — — ns tckhdis EEDO disable after rising edge EECLK 550 — — ns tdsckh EEDI setup to rising edge of EECLK 90 —
LAN9514/LAN9514I TABLE 4-9: JTAG TIMING VALUES Symbol 4.6 Description ttckp TCK clock period ttckhl TCK clock high/low time Min Max Units Notes 66.67 — ns — ttckp*0.4 ttckp*0.
LAN9514/LAN9514I Note 4-13 The maximum allowable values for Frequency Tolerance and Frequency Stability are application dependent. Since any particular application must meet the IEEE +/-50 PPM Total PPM Budget, the combination of these two values must be approximately +/-45 PPM (allowing for aging). Note 4-14 Frequency Deviation Over Time is also referred to as Aging. Note 4-15 The total deviation for the Transmitter Clock Frequency is specified by IEEE 802.3u as +/- 50 PPM.
LAN9514/LAN9514I 5.0 PACKAGE OUTLINE 5.1 64-QFN Package FIGURE 5-1: TABLE 5-1: LAN9514/LAN9514I 64-QFN PACKAGE DEFINITION LAN9514/LAN9514I 64-QFN DIMENSIONS Min Nominal Max Remarks A 0.80 0.85 1.00 Overall Package Height A1 0.00 0.02 0.05 Standoff A2 — 0.65 0.80 Mold Cap Thickness D/E 8.90 9.00 9.10 X/Y Body Size D1/E1 8.65 8.75 8.85 X/Y Mold Cap Size D2/E2 7.20 7.30 7.40 X/Y Exposed Pad Size L 0.30 0.40 0.50 Terminal Length 2009-2016 Microchip Technology Inc.
LAN9514/LAN9514I TABLE 5-1: b LAN9514/LAN9514I 64-QFN DIMENSIONS (CONTINUED) 0.18 e 0.25 0.30 0.50 BSC K 0.35 — Terminal Width Terminal Pitch — Pin to Center Pad Clearance Note 1: All dimensions are in millimeters unless otherwise noted. 2: Dimension “b” applies to plated terminals and is measured between 0.15 and 0.30 mm from the terminal tip. 3: Details of terminal #1 identifier are optional, but must be located within the area indicated.
LAN9514/LAN9514I APPENDIX A: TABLE A-1: DATASHEET REVISION HISTORY CUSTOMER REVISION HISTORY REVISION LEVEL AND DATE DS00002306A (11-02-16) SECTION/FIGURE/ENTRY All CORRECTION Converted document to Microchip template. Replaces SMSC Rev 1.2. Fixed typos. Table 2-2, “JTAG Pins,” on page 7 Updated description for JTAG Test Clock. Rev. 1.2 (02-29-12) Section 4.3, "Power Consumption," on page 38 Added suspend 0, suspend 1, and suspend 3 power consumption data. Rev. 1.1 (09-19-11) All Fixed typos.
LAN9514/LAN9514I NOTES: DS00002306A-page 50 2009-2016 Microchip Technology Inc.
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LAN9514/LAN9514I Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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