Datasheet

© 2008 Microchip Technology Inc. DS22058C-page 21
MCP6V01/2/3
4.0 APPLICATIONS
The MCP6V01/2/3 family of auto-zeroed op amps is
manufactured using Microchip’s state of the art CMOS
process. It is designed for low cost, low power and high
precision applications. Its low supply voltage, low
quiescent current and wide bandwidth makes the
MCP6V01/2/3 ideal for battery-powered applications.
4.1 Overview of Auto-zeroing
Operation
Figure 4-1 shows a simplified diagram of the
MCP6V01/2/3 auto-zeroed op amps. This will be used
to explain how the DC voltage errors are reduced in this
architecture.
FIGURE 4-1: Simplified Auto-zeroed Op Amp Functional Diagram.
4.1.1 BUILDING BLOCKS
The Null Amp. and Main Amp. are designed for high
gain and accuracy using a differential topology. They
have an auxiliary input (bottom left) used for correcting
the offset voltages. Both inputs are added together
internally. The capacitors at the auxiliary inputs (C
FW
and C
H
) hold the corrected values during normal
operation.
The Output Buffer is designed to drive external loads at
the V
OUT
pin. It also produces a single ended output
voltage (V
REF
is an internal reference voltage).
All of these switches are make-before-break in order to
minimize glitch-induced errors. They are driven by two
clock phases (φ
1
and φ
2
) that select between normal
mode and auto-zeroing mode.
The clock is derived from an internal R-C oscillator
running at a rate of f
OSC1
= 300 kHz. The oscillator’s
output is divided down to the desired rate. It is also
randomized to minimize (spread) undesired clock
tones in the output.
The internal POR ensures the part starts up in a known
good state. It also provides protection against power
supply brown out events.
The Chip Select input places the op amp in a low power
state when it is high. When it goes low, it powers the op
amp at its normal level and starts operation properly.
The Digital Control circuitry takes care of all of the
housekeeping details of the switching operation. It also
takes care of Chip Select and POR events.
V
IN
+
V
IN
–
Main
Output
V
OUT
V
REF
Amp.
Buffer
NC
Null
Amp.
Null
Input
φ
1
Switches
Null
Correct
φ
2
Switches
Null
Output
Switches
C
H
C
FW
POR
Digital
Control
Oscillator
CS
Clock
Randomization
φ
1
φ
2