Datasheet

© 2008 Microchip Technology Inc. DS22058C-page 23
MCP6V01/2/3
4.2 Other Functional Blocks
4.2.1 RAIL-TO-RAIL INPUTS
The input stage of the MCP6V01/2/3 op amps uses two
differential CMOS input stages in parallel. One
operates at low common mode input voltage (V
CM
,
which is approximately equal to V
IN
+ and V
IN
– in nor-
mal operation) and the other at high V
CM
. With this
topology, the input operates with V
CM
up to 0.2V past
either supply rail at +25°C (see Figure 2-18). The input
offset voltage (V
OS
) is measured at V
CM
=V
SS
–0.2V
and V
DD
+ 0.2V to ensure proper operation.
The transition between the input stages occurs when
V
CM
≈ V
DD
– 0.9V (see Figure 2-7 and Figure 2-8). For
the best distortion and gain linearity, with non-inverting
gains, avoid this region of operation.
4.2.1.1 Phase Reversal
The input devices are designed to not exhibit phase
inversion when the input pins exceed the supply
voltages. Figure 2-43 shows an input voltage
exceeding both supplies with no phase inversion.
4.2.1.2 Input Voltage and Current Limits
The ESD protection on the inputs can be depicted as
shown in Figure 4-4. This structure was chosen to
protect the input transistors, and to minimize input bias
current (I
B
). The input ESD diodes clamp the inputs
when they try to go more than one diode drop below
V
SS
. They also clamp any voltages that go too far
above V
DD
; their breakdown voltage is high enough to
allow normal operation, and low enough to bypass
quick ESD events within the specified limits.
FIGURE 4-4: Simplified Analog Input ESD
Structures.
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the currents
(and voltages) at the input pins (see Section 1.1
“Absolute Maximum Ratings †”). Figure 4-5 shows
the recommended approach to protecting these inputs.
The internal ESD diodes prevent the input pins (V
IN
+
and V
IN
–) from going too far below ground, and the
resistors R
1
and R
2
limit the possible current drawn out
of the input pins. Diodes D
1
and D
2
prevent the input
pins (V
IN
+ and V
IN
–) from going too far above V
DD
, and
dump any currents onto V
DD
. When implemented as
shown, resistors R
1
and R
2
also limit the current
through D
1
and D
2
.
FIGURE 4-5: Protecting the Analog
Inputs.
It is also possible to connect the diodes to the left of the
resistor R
1
and R
2
. In this case, the currents through
the diodes D
1
and D
2
need to be limited by some other
mechanism. The resistors then serve as in-rush current
limiters; the DC current into the input pins (V
IN
+ and
V
IN
–) should be very small.
A significant amount of current can flow out of the
inputs (through the ESD diodes) when the common
mode voltage (V
CM
) is below ground (V
SS
); see
Figure 2-17. Applications that are high impedance may
need to limit the usable voltage range.
4.2.2 RAIL-TO-RAIL OUTPUT
The output voltage range of the MCP6V01/2/3
auto-zeroed op amps is V
DD
– 15 mV (minimum) and
V
SS
+ 15 mV (maximum) when R
L
=20kΩ is
connected to V
DD
/2 and V
DD
= 5.5V. Refer to
Figure 2-19 and Figure 2-20 for more information.
These op amps are designed to drive light loads; use
another amplifier to buffer the output from heavy loads.
4.2.3 CHIP SELECT (CS)
The single MCP6V03 has a Chip Select (CS) pin.
When CS
is pulled high, the supply current for the
corresponding op amp drops to about 1 µA (typical),
and is pulled through the CS
pin to V
SS
. When this
happens, the amplifier is put into a high impedance
state. By pulling CS
low, the amplifier is enabled. If the
CS pin is left floating, the internal pull-down resistor
(about 5 MΩ) will keep the part on. Figure 1-4 shows
the output voltage and supply current response to a CS
pulse.
Bond
Pad
Bond
Pad
Bond
Pad
V
DD
V
IN
+
V
SS
Input
Stage
Bond
Pad
V
IN
–
V
1
MCP6V0X
R
1
V
DD
D
1
R
1
>
V
SS
– (minimum expected V
1
)
2mA
V
OUT
R
2
>
V
SS
– (minimum expected V
2
)
2mA
V
2
R
2
D
2