Datasheet

 2007-2019 Microchip Technology Inc. DS30009905F-page 117
PIC24FJ256GA110 FAMILY
8.0 OSCILLATOR
CONFIGURATION
The oscillator system for PIC24FJ256GA110 family
devices has the following features:
• A Total of Four External and Internal Oscillator Options
as Clock Sources, Providing 11 Different Clock modes
• On-Chip 4x PLL to Boost Internal Operating
Frequency on Select Internal and External Oscillator
Sources
• Software-Controllable Switching between Various
Clock Sources
• Software-Controllable Postscaler for Selective
CLOCKING of CPU for System Power Savings
• A Fail-Safe Clock Monitor (FSCM) that Detects
Clock Failure and Permits Safe Application
Recovery or Shutdown
• A Separate and Independently Configurable System
Clock Output for Synchronizing External Hardware
A simplified diagram of the oscillator system is shown
in Figure 8-1.
FIGURE 8-1: PIC24FJ256GA110 FAMILY CLOCK DIAGRAM
Note: This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive refer-
ence source. For more information, refer
to “Oscillator” (www.microchip.com/
DS39700) in the “dsPIC33/PIC24 Family
Reference Manual”. The information in this
data sheet supersedes the information in
the FRM.
Secondary Oscillator
SOSCEN
Enable
Oscillator
SOSCI
SOSCO
Clock Source Option
for Other Modules
OSCO
OSCI
Primary Oscillator
XT, HS, EC
Postscaler
CLKDIV[10:8]
WDT, PWRT
8 MHz
FRCDIV
31 kHz (nominal)
FRC
Oscillator
LPRC
Oscillator
SOSC
LPRC
Clock Control Logic
Fail-Safe
Clock
Monitor
FRC
(nominal)
4 x PLL
XTPLL, HSPLL
ECPLL,FRCPLL
8 MHz
4 MHz
CPU
Peripherals
Postscaler
CLKDIV[14:12]
CLKO
Reference Clock
Generator
REFO
REFOCON[15:8]
DIV/2
(FCY)