Datasheet

 2007-2019 Microchip Technology Inc. DS30009905F-page 127
PIC24FJ256GA110 FAMILY
9.0 POWER-SAVING FEATURES
The PIC24FJ256GA110 family of devices provides the
ability to manage power consumption by selectively
managing clocking to the CPU and the peripherals. In
general, a lower clock frequency and a reduction in the
number of circuits being clocked constitutes lower
consumed power. All PIC24F devices manage power
consumption in four different ways:
• Clock Frequency
• Instruction-Based Sleep and Idle modes
• Software Controlled Doze mode
• Selective Peripheral Control in Software
Combinations of these methods can be used to
selectively tailor an application’s power consumption,
while still maintaining critical application features, such
as timing-sensitive communications.
9.1 Clock Frequency and Clock
Switching
PIC24F devices allow for a wide range of clock
frequencies to be selected under application control. If
the system clock configuration is not locked, users can
choose low-power or high-precision oscillators by simply
changing the NOSCx bits. The process of changing a
system clock during operation, as well as limitations to
the process, are discussed in more detail in Section 8.0
“Oscillator Configuration”.
9.2 Instruction-Based Power-Saving
Modes
PIC24F devices have two special power-saving modes
that are entered through the execution of a special
PWRSAV instruction. Sleep mode stops clock operation
and halts all code execution; Idle mode halts the CPU
and code execution, but allows peripheral modules to
continue operation. The assembly syntax of the
PWRSAV instruction is shown in Example 9-1.
Sleep and Idle modes can be exited as a result of an
enabled interrupt, WDT time-out or a device Reset.
When the device exits these modes, it is said to
“wake-up”.
9.2.1 SLEEP MODE
Sleep mode has these features:
• The system clock source is shut down. If an
on-chip oscillator is used, it is turned off.
• The device current consumption will be reduced
to a minimum provided that no I/O pin is sourcing
current.
• The Fail-Safe Clock Monitor does not operate
during Sleep mode since the system clock source
is disabled.
• The LPRC clock will continue to run in Sleep
mode if the WDT is enabled.
• The WDT, if enabled, is automatically cleared
prior to entering Sleep mode.
• Some device features or peripherals may
continue to operate in Sleep mode. This includes
items such as the Input Change Notification (ICN)
on the I/O ports, or peripherals that use an exter-
nal clock input. Any peripheral that requires the
system clock source for its operation will be
disabled in Sleep mode.
Additional power reductions can be achieved by
disabling the on-chip voltage regulator whenever Sleep
mode is invoked. This is done by clearing the PMSLP
bit (RCON[8]). Disabling the regulator adds an addi-
tional delay of about 190 µs to the device wake-up time.
It is recommended that applications not using the volt-
age regulator leave the PMSLP bit set. For additional
details on the regulator and Sleep mode, see
Section 25.2.5 “Voltage Regulator Standby Mode”.
The device will wake-up from Sleep mode on any of
these events:
• On any interrupt source that is individually
enabled
• On any form of device Reset
• On a WDT time-out
EXAMPLE 9-1: PWRSAV INSTRUCTION SYNTAX
Note: This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive
reference source. For more information,
refer to “Power-Saving Features”
(www.microchip.com/DS39698) in the
“dsPIC33/PIC24 Family Reference Man-
ual”. The information in this data sheet
supersedes the information in the FRM.
PWRSAV #0 ; Put the device into SLEEP mode
PWRSAV #1 ; Put the device into IDLE mode