Datasheet

 2007-2019 Microchip Technology Inc. DS30009905F-page 211
PIC24FJ256GA110 FAMILY
FIGURE 18-5: MASTER MODE, PARTIALLY MULTIPLEXED ADDRESSING (SEPARATE READ
AND WRITE STROBES, TWO CHIP SELECTS)
FIGURE 18-6: MASTER MODE, FULLY MULTIPLEXED ADDRESSING (SEPARATE READ AND
WRITE STROBES, TWO CHIP SELECTS)
FIGURE 18-7: EXAMPLE OF A MULTIPLEXED ADDRESSING APPLICATION
PMRD
PMWR
PMD[7:0]
PMCS1
PMA[13:8]
PMALL
PMA[7:0]
PIC24F
Address Bus
Multiplexed
Data and
Address Bus
Control Lines
PMCS2
PMRD
PMWR
PMD[7:0]
PMCS1
PMALH
PMA[13:8]
PIC24F
Multiplexed
Data and
Address Bus
Control Lines
PMALL
PMCS2
PMD[7:0]
PMALH
D[7:0]
373
A[15:0]
D[7:0]
A[7:0]
373
PMRD
PMWR
OE
WR
CE
PIC24F
Address Bus
Data Bus
Control Lines
PMCS1
PMALL
A[15:8]