Datasheet

© 2010 Microchip Technology Inc. DS61156D-page 125
PIC32MX5XX/6XX/7XX
13.0 TIMER1
This family of PIC32MX devices features one
synchronous/asynchronous 16-bit timer that can operate
as a free-running interval timer for various timing applica-
tions and counting external events. This timer can also
be used with the Low-Power Secondary Oscillator
(S
OSC) for Real-Time Clock (RTC) applications. The
following modes are supported:
• Synchronous Internal Timer
• Synchronous Internal Gated Timer
• Synchronous External Timer
• Asynchronous External Timer
13.1 Additional Supported Features
• Selectable clock prescaler
• Timer operation during CPU Idle and Sleep mode
• Fast bit manipulation using CLR, SET and INV
registers
• Asynchronous mode can be used with the S
OSC
to function as a Real-Time Clock (RTC)
FIGURE 13-1: TIMER1 BLOCK DIAGRAM
(1)
Note 1: This data sheet summarizes the features of
the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to
Section 14. “Timers”
(DS61105) in the “PIC32MX Family
Reference Manual”, which is available
from the Microchip web site
(www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to
Section 4.0
“Memory Organization”
in this data
sheet for device-specific register and bit
information.
ON (T1CON<15>)
Sync
SOSCI
SOSCO/T1CK
PR1
T1IF
Equal
16-bit Comparator
TMR1
Reset
SOSCEN
Event Flag
1
0
TSYNC (T1CON<2>)
TGATE (T1CON<7>)
TGATE (T1CON<7>)
PBCLK
1
0
TCS (T1CON<1>)
Gate
Sync
TCKPS<1:0>
Prescaler
2
1, 8, 64, 256
x 1
1 0
0 0
Q
Q
D
(T1CON<5:4>)
Note 1: The default state of the SOSCEN (OSCCON<1>) during a device Reset is controlled by the FSOSCEN bit in
Configuration Word, DEVCFG1.