Datasheet

© 2010 Microchip Technology Inc. DS61156D-page 25
PIC32MX5XX/6XX/7XX
1.0 DEVICE OVERVIEW
This document contains device-specific information for
PIC32MX5XX/6XX/7XX devices.
Figure 1-1 illustrates a general block diagram of the
core and peripheral modules in the
PIC32MX5XX/6XX/7XX family of devices.
Table 1-1 lists the functions of the various pins shown
in the pinout diagrams.
FIGURE 1-1: BLOCK DIAGRAM
(1,2)
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to the related section of the
“PIC32MX Family Reference Manual”,
which is available from the Microchip
web site (www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
Note 1: Some features are not available on all device variants.
2: BOR functionality is provided when the on-board voltage regulator is enabled.
UART1A,1B,2A,
Comparators
PORTA
PORTD
PORTE
PORTF
PORTG
PORTB
CN1-22
JTAG
Priority
DMAC
ICD
MIPS32
®
M4K
®
IS DS
EJTAG INT
Bus Matrix
Prefetch
Data RAM
Peripheral Bridge
128
128-bit Wide
Flash
32
32
32
32
32
Peripheral Bus Clocked by PBCLK
Program Flash Memory
Controller
32
Module
32
32
Interrupt
Controller
BSCAN
PORTC
PMP
I2C1,2,1A,
SPI1,1A,2A,3A
IC1-5
PWM
OC1-5
OSC1/CLKI
OSC2/CLKO
V
DD, VSS
Timing
Generation
MCLR
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
Precision
Reference
Band Gap
FRC/LPRC
Oscillators
Regulator
Voltage
VCAP/VDDCORE
OSC/SOSC
Oscillators
PLL
Dividers
SYSCLK
PBCLK
Peripheral Bus Clocked by SYSCLK
USB
PLL-USB
USBCLK
32
RTCC
10-bit ADC
Timer1-5
32
32
2B,3A,3B
CAN1, CAN2
ETHERNET
32
32
CPU Core
2A,3A