Datasheet

PIC32MX5XX/6XX/7XX
DS61156D-page 34 © 2010 Microchip Technology Inc.
ERXD3 58 44 L8 I ST Ethernet Receive Data 3.
(2)
ERXERR 64 35 J5 I ST Ethernet receive error input.
(2)
ERXDV 62 12 F2 I ST Ethernet receive data valid.
(2)
ECRSDV 61 12 F2 I ST Ethernet carrier sense data valid.
(2)
ERXCLK 63 14 F3 I ST Ethernet receive clock.
(2)
EREFCLK 63 14 F3 I ST Ethernet reference clock.
(2)
ETXD0 2 88 A6 O — Ethernet Transmit Data 0.
(2)
ETXD1 3 87 B6 O — Ethernet Transmit Data 1.
(2)
ETXD2 43 79 A9 O — Ethernet Transmit Data 2.
(2)
ETXD3 42 80 D8 O — Ethernet Transmit Data 3.
(2)
ETXERR 54 89 E6 O — Ethernet transmit error.
(2)
ETXEN 1 83 D7 O — Ethernet transmit enable.
(2)
ETXCLK 55 84 C7 I ST Ethernet transmit clock.
(2)
ECOL 44 10 E3 I ST Ethernet collision detect.
(2)
ECRS 45 11 F4 I ST Ethernet carrier sense.
(2)
EMDC 30 71 C11 O — Ethernet management data clock.
(2)
EMDIO 49 68 E9 I/O — Ethernet management data.
(2)
AERXD0 43 18 G1 I ST Alternate Ethernet Receive Data 0.
(2)
AERXD1 42 19 G2 I ST Alternate Ethernet Receive Data 1.
(2)
AERXD2 — 28 L2 I ST Alternate Ethernet Receive Data 2.
(2)
AERXD3 — 29 K3 I ST Alternate Ethernet Receive Data 3.
(2)
AERXERR 55 1 B2 I ST Alternate Ethernet receive error input.
(2)
AERXDV — 12 F2 I ST Alternate Ethernet receive data valid.
(2)
AECRSDV 44 12 F2 I ST Alternate Ethernet carrier sense data valid.
(2)
AERXCLK — 14 F3 I ST Alternate Ethernet receive clock.
(2)
AEREFCLK 45 14 F3 I ST Alternate Ethernet reference clock.
(2)
AETXD0 59 47 L9 O — Alternate Ethernet Transmit Data 0.
(2)
AETXD1 58 48 K9 O — Alternate Ethernet Transmit Data 1.
(2)
AETXD2 — 44 L8 O — Alternate Ethernet Transmit Data 2.
(2)
AETXD3 — 43 K7 O — Alternate Ethernet Transmit Data 3.
(2)
AETXERR — 35 J5 O — Alternate Ethernet transmit error.
(2)
AETXEN 54 67 E8 O — Alternate Ethernet transmit enable.
(2)
AETXCLK — 66 E11 I ST Alternate Ethernet transmit clock.
(2)
AECOL — 42 L7 I ST Alternate Ethernet collision detect.
(2)
AECRS — 41 J7 I ST Alternate Ethernet carrier sense.
(2)
AEMDIO 49 68 E9 I/O — Alternate Ethernet Management Data.
(2)
TRCLK — 91 C5 O — Trace clock.
TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
(1)
Pin
Type
Buffer
Type
Description
64-Pin
QFN/TQFP
100-Pin
TQFP
121-Pin
XBGA
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power
ST = Schmitt Trigger input with CMOS levels O = Output I = Input
TTL = TTL input buffer
Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.
2: See Section 24.0 “Ethernet Controller” for more information.