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PIC32MX5XX/6XX/7XX

TABLE 4-15: SPI1 REGISTER MAP FOR PIC32MX575F256L, PIC32MX575F512L, PIC32MX675F256L, PIC32MX675F512L,

PIC32MX695F512L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES

(1)

Virtual Address

(BF80_#)

Name

Bit Range

Bits

All Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

5E00 SPI1CON

31:16 FRMEN FRMSYNC FRMPOL MSSEN FRMSYPW FRMCNT<2:0>

— — — — — — SPIFE ENHBUF 0000

15:0 ON FRZ SIDL DISSDO MODE32 MODE16 SMP CKE SSEN CKP MSTEN

— STXISEL<1:0> SRXISEL<1:0> 0000

5E10 SPI1STAT

31:16

— — — RXBUFELM<4:0> — — — TXBUFELM<4:0> 0000

15:0

— — — — SPIBUSY — — SPITUR SRMT SPIROV SPIRBE — SPITBE — SPITBF SPIRBF 0000

5E20 SPI1BUF

31:16

DATA<31:0>

0000

15:0 0000

5E30 SPI1BRG

31:16

— — — — — — — — — — — — — — — — 0000

15:0

— — — — — — — BRG<8:0> 0000

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1: All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV

Registers” for more information.