Datasheet

© 2010 Microchip Technology Inc. DS61156D-page 83
PIC32MX5XX/6XX/7XX
TABLE 4-20: COMPARATOR REGISTER MAP
(1)
Virtual Address
(BF80_#)
Register
Name
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
A000 CM1CON
31:16
— — — — — — — — — — — — — — — — 0000
15:0 ON COE CPOL
— — — —COUTEVPOL<1:0> — CREF — — CCH<1:0> 0000
A010 CM2CON
31:16
— — — — — — — — — — — — — — — — 0000
15:0 ON COE CPOL
— — — —COUTEVPOL<1:0> — CREF — — CCH<1:0> 0000
A060 CMSTAT
31:16
— — — — — — — — — — — — — — — — 0000
15:0
— FRZ SIDL — — — — — — — — — — — C2OUT C1OUT 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers”
for more information.
TABLE 4-21: COMPARATOR VOLTAGE REFERENCE REGISTER MAP
(1)
Virtual Address
(BF80_#)
Register
Name
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
9800 CVRCON
31:16
— — — — — — — — — — — — — — — — 0000
15:0 ON
— — — —VREFSEL
(3)
BGSEL<1:0>
(3)
— CVROE CVRR CVRSS CVR<3:0>
(2)
0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers”
for more information.
2: On devices with less than 256K of memory, these bits do not exist and are treated as reserved.
3: These bits are not available on PIC32MX575/675/695/775 devices.