Datasheet

PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
DS60001320B-page 100 Preliminary 2015 Microchip Technology Inc.
5.1 Flash Control Registers
TABLE 5-1: FLASH CONTROLLER REGISTER MAP
Virtual Address
(BF80_#)
Register
Name
Bit Range
Bits
All Resets
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
0600 NVMCON
(1)
31:16 0000
15:0 WR WREN WRERR LVDERR PFSWAP BFSWAP NVMOP<3:0> 00x0
0610 NVMKEY
31:16
NVMKEY<31:0>
0000
15:0 0000
0620
NVMADDR
(1)
31:16
NVMADDR<31:0>
0000
15:0 0000
0630 NVMDATA0
31:16
NVMDATA0<31:0>
0000
15:0 0000
0640 NVMDATA1
31:16
NVMDATA1<31:0>
0000
15:0 0000
0650 NVMDATA2
31:16
NVMDATA2<31:0>
0000
15:0 0000
0660 NVMDATA3
31:16
NVMDATA3<31:0>
0000
15:0 0000
0670
NVMSRC
ADDR
31:16
NVMSRCADDR<31:0>
0000
15:0 0000
0680 NVMPWP
(1)
31:16 PWPULOCK PWP<23:16> 8000
15:0 PWP<15:0> 0000
0690 NVMBWP
(1)
31:16 0000
15:0 LBWPULOCK LBWP4
LBWP3 LBWP2 LBWP1 LBWP0
UBWPULOCK UBWP4 UBWP3 UBWP2 UBWP1 UBWP0 9FDF
06A0 NVMCON2
(1)
31:16 001F
15:0 SWAPLOCK<1:0>
0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: This register has corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV Registers” for more information.