Datasheet

 2015 Microchip Technology Inc. Preliminary DS60001320B-page 175
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
10.0 DIRECT MEMORY ACCESS
(DMA) CONTROLLER
The Direct Memory Access (DMA) Controller is a bus
master module useful for data transfers between
different devices without CPU intervention. The source
and destination of a DMA transfer can be any of the
memory mapped modules existent in the device such
as SPI, UART, PMP, etc., or memory itself.
Key features include:
• Eight identical channels, each featuring:
- Auto-increment source and destination
address registers
- Source and destination pointers
- Memory to memory and memory to
peripheral transfers
• Automatic word-size detection:
- Transfer granularity, down to byte level
- Bytes need not be word-aligned at source and
destination
• Fixed priority channel arbitration
• Flexible DMA channel operating modes:
- Manual (software) or automatic (interrupt) DMA
requests
- One-Shot or Auto-Repeat Block Transfer modes
- Channel-to-channel chaining
• Flexible DMA requests:
- A DMA request can be selected from any of the
peripheral interrupt sources
- Each channel can select any (appropriate)
observable interrupt as its DMA request source
- A DMA transfer abort can be selected from any
of the peripheral interrupt sources
- Up to 2-byte Pattern (data) match transfer
termination
• Multiple DMA channel status interrupts:
- DMA channel block transfer complete
- Source empty or half empty
- Destination full or half full
- DMA transfer aborted due to an external event
- Invalid DMA address generated
• DMA debug support features:
- Most recent error address accessed by a DMA
channel
- Most recent DMA channel to transfer data
• CRC Generation module:
- CRC module can be assigned to any of the
available channels
- CRC module is highly configurable
FIGURE 10-1: DMA BLOCK DIAGRAM
Note: This data sheet summarizes the features
of the PIC32MZ EF family of devices. It is
not intended to be a comprehensive refer-
ence source. To complement the informa-
tion in this data sheet, refer to Section 31.
“Direct Memory Access (DMA) Control
-
ler” (DS60001117) in the “PIC32 Family
Reference Manual”
, which is available
from the Microchip web site
(www.microchip.com/PIC32).
Address Decoder
Channel 0 Control
Channel 1 Control
Channel n Control
Global Control
(DMACON)
Bus
Channel Priority
Arbitration
S
E
L
S
E
L
Y
I
0
I
1
I
2
I
n
System IRQINT Controller
Peripheral Bus
Interface
DMA
SYSCLK
System Bus + Bus Arbitration