Datasheet

 2015 Microchip Technology Inc. Preliminary DS60001320B-page 707
PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family
APPENDIX C: REVISION HISTORY
Revision A (January 2015)
This is the initial released version of the document.
Revision B (July 2015)
The document status was updated from Advance
Information to Preliminary.
The revision includes the following major changes,
which are referenced by their respective chapter in
Table C-1.
In addition, minor updates to text and formatting were
incorporated throughout the document.
TABLE C-1: MAJOR SECTION UPDATES
Section Name Update Description
32-bit MCUs (up to 2 MB Live-
Update Flash and 512 KB SRAM)
with FPU, Audio and Graphics
Interfaces, HS USB, Ethernet,
and Advanced Analog
The Operating Conditions were updated to: 2.1V to 3.6V.
4.0 “Memory Organization” Legal information on the System Bus was added (see 4.2 “System Bus
Arbitration”).
5.0 “Flash Program Memory” The BOOTSWAP bit in the NVMCON register was changed to: BFSWAP (see
Register 5-1).
6.0 “Resets” The NVMLTA bit was removed from the RCON register (see Register 6-1).
The GNMI bit was added to the RNMICON register (see Register 6-3).
7.0 “CPU Exceptions and
Interrupt Controller”
The ADC FIFO Data Ready Interrupt, IRQ 45, was added (see Table 7-2).
ADC FIFO bits were added, and Note 7 regarding devices without a Crypto
module was added to the Interrupt Register Map (see Table 7-3).
The NMIKEY<7:0> bits were added to the INTCON register (see Register 7-1).
8.0 “Oscillator Configuration” The SPLLRDY bit was removed and the SPLLDIVRDY bit was added to the
CLKSTAT register (see Register 8-8
11.0 “Hi-Speed USB with On-The-
Go (OTG)”
The VBUSIE and VBUSIF bits were changed to: VBUSERRIE and
VBUSERRIF, respectively in the USBCSR2 register (see Register 11-3).
15.0 “Deadman Timer (DMT)” The POR values were updated for the PSCNT<4:0> bits in the Post Status
Configure DMT Count Status register (see Register 15-6).
The POR values were updated for the PSINTV<2:0> bits in the Post Status
Configure DMT Interval Status register (see Register 15-7).
16.0 “Watchdog Timer (WDT)” The WDTCON register was updated (see Register 16-1).
23.0 “Parallel Master Port (PMP)” The PMDOUT, PMDIN, and PMRDIN registers were added (see Register 23-4,
Register 23-4, and Register 23-10).
The PMADDR, PMWADDR, and PMRADDR registers were updated (see
Register 23-3, Register 23-8, and Register 23-9).
The PMRDATA register was removed.
24.0 “External Bus Interface
(EBI)”
Reset values for the EBIMSK2, EBIMSK3, EBISMT0-EBISMT2, and
EBIFTRPD registers were updated in the EBI Register Map (see Table 24-2).
POR value changes were implemented to the EBI Static Memory Timing
Register (see Register 24-3).