SST26VF032B / SST26VF032BA 3.0V 32 Mbit Serial Quad I/O (SQI) Flash Memory Features • Single Voltage Read and Write Operations - 2.7-3.
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SST26VF032B / SST26VF032BA 1.0 BLOCK DIAGRAM FIGURE 1-1: FUNCTIONAL BLOCK DIAGRAM OTP Address Buffers and Latches X - Decoder SuperFlash Memory Y - Decoder Page Buffer, I/O Buffers and Data Latches Control Logic Serial Interface WP# HOLD# SCK CE# SIO [3:0] 20005218 B1.0 2015 Microchip Technology Inc.
SST26VF032B / SST26VF032BA 2.0 PIN DESCRIPTION FIGURE 2-1: PIN DESCRIPTION FOR 8-LEAD SOIJ CE# 1 SO/SIO1 2 8 VDD 7 HOLD/SIO3 FIGURE 2-2: PIN DESCRIPTION FOR 8-CONTACT WDFN CE# 1 SO/SIO1 2 VDD 7 HOLD/SIO3 Top View Top View WP#/SIO2 3 6 SCK VSS 4 5 SI/SIO0 WP#/SIO2 3 6 SCK VSS 4 5 SI/SIO0 20005218 08-wson QA P1.0 20005218 08-soic S2A P1.
SST26VF032B / SST26VF032BA TABLE 2-1: PIN DESCRIPTION Symbol Pin Name Functions SCK Serial Clock To provide the timing of the serial interface. Commands, addresses, or input data are latched on the rising edge of the clock input, while output data is shifted out on the falling edge of the clock input. SIO[3:0] Serial Data Input/Output To transfer commands, addresses, or data serially into the device or data out of the device. Inputs are latched on the rising edge of the serial clock.
SST26VF032B / SST26VF032BA 3.0 MEMORY ORGANIZATION The SST26VF032B/032BA SQI memory array is organized in uniform, 4 KByte erasable sectors with the following erasable blocks: eight 8 KByte parameter, two 32 KByte overlay, and sixty-two 64 KByte overlay blocks. See Figure 3-1. FIGURE 3-1: MEMORY MAP Top of Memory Block 8 KByte 8 KByte 8 KByte 8 KByte 32 KByte ... 64 KByte 2 Sectors for 8 KByte blocks 8 Sectors for 32 KByte blocks 16 Sectors for 64 KByte blocks 64 KByte ...
SST26VF032B / SST26VF032BA 4.0 DEVICE OPERATION SST26VF032B/032BA support both Serial Peripheral Interface (SPI) bus protocol and a 4-bit multiplexed SQI bus protocol. To provide backward compatibility to traditional SPI Serial Flash devices, the device’s initial state after a power-on reset is SPI mode which supports multi-I/O (x1/x2/x4) Read/Write commands. A command instruction configures the device to SQI mode.
SST26VF032B / SST26VF032BA The Write Block-Protection Register command is a two-cycle command which requires that Write-Enable (WREN) is executed prior to the Write Block-Protection Register command. The Global Block-Protection Unlock command clears all write protection bits in the Block-Protection register. 4.1.2 WRITE-PROTECTION LOCK-DOWN (VOLATILE) To prevent changes to the Block-Protection register, use the Lock-Down Block-Protection Register (LBPR) command to enable Write-Protection Lock-Down.
SST26VF032B / SST26VF032BA TABLE 4-1: WRITE PROTECTION LOCK-DOWN STATES WP# IOC WPEN WPLD L 0 1 1 Not Allowed Protected L 0 0 1 Not Allowed Writable L 0 1 0 Not Allowed Protected L 01 02 0 Allowed Writable H 0 X 1 Not Allowed Writable H 0 X 0 Allowed Writable X 1 X 1 Not Allowed Writable X 13 2 0 Allowed Writable 0 Execute WBPR Instruction Configuration Register 1. Default at power-up Register settings for SST26VF032B 2.
SST26VF032B / SST26VF032BA 4.5 Status Register The Status register is a read-only register that provides the following status information: whether the flash memory array is available for any Read or Write operation, if the device is write-enabled, whether an erase or program operation is suspended, and if the Block- TABLE 4-2: Protection register and/or Security ID are locked down.
SST26VF032B / SST26VF032BA 4.5.1 WRITE-ENABLE LATCH (WEL) The Write-Enable Latch (WEL) bit indicates the status of the internal memory’s Write-Enable Latch. If the WEL bit is set to ‘1’, the device is write enabled. If the bit is set to ‘0’ (reset), the device is not write enabled and does not accept any memory Program or Erase, Protection Register Write, or Lock-Down commands.
SST26VF032B / SST26VF032BA 4.5.8 I/O CONFIGURATION (IOC) The I/O Configuration (IOC) bit re-configures the I/O pins. The IOC bit is set by writing a ‘1’ to Bit 1 of the Configuration register. When IOC bit is ‘0’ the WP# pin and HOLD# pin are enabled (SPI or Dual Configuration setup). When IOC bit is set to ‘1’ the SIO2 pin and SIO3 pin are enabled (SPI Quad I/O Configuration setup).
SST26VF032B / SST26VF032BA 5.0 INSTRUCTIONS Instructions are used to read, write (erase and program), and configure the SST26VF032B/032BA. The complete list of the instructions is provided in Table 5-1.
SST26VF032B / SST26VF032BA TABLE 5-1: DEVICE OPERATION INSTRUCTIONS FOR SST26VF032B/032BA Mode Command Cycle1 SPI SQI Address Cycle(s)2, 3 Dummy Cycle(s)3 Data Cycle(s)3 Max Freq 104 MHz Instruction Description WRSU Suspends Program/Erase B0H X X 0 0 0 WRRE Resumes Program/Erase 30H X X 0 0 0 RBPR Read Block-Protection Register 72H X 0 0 1 to18 X 0 1 1 to18 WBPR Write Block-Protection Register 42H X X 0 0 1 to 18 LBPR Lock Down Block-Protection Register 8DH
SST26VF032B / SST26VF032BA 5.1 No Operation (NOP) The Reset operation requires the Reset-Enable command followed by the Reset command. Any command other than the Reset command after the Reset-Enable command will disable the Reset-Enable. The No Operation command only cancels a Reset Enable command. NOP has no impact on any other command. 5.
SST26VF032B / SST26VF032BA 5.4 Enable Quad I/O (EQIO) The Enable Quad I/O (EQIO) instruction, 38H, enables the flash device for SQI bus operation. Upon completion of the instruction, all instructions thereafter are FIGURE 5-3: expected to be 4-bit multiplexed input/output (SQI mode) until a power cycle or a “Reset Quad I/O instruction” is executed. See Figure 5-3. ENABLE QUAD I/O SEQUENCE CE# MODE 3 SCK 0 2 1 3 4 5 6 7 MODE 0 SIO0 38 SIO[3:1] 20005218 F43.
SST26VF032B / SST26VF032BA 5.6 High-Speed Read (104 MHz) Initiate High-Speed Read by executing an 8-bit command, 0BH, followed by address bits A[23-0] and a dummy byte. CE# must remain active low for the duration of the High-Speed Read cycle. See Figure 5-6 for the High-Speed Read sequence for SPI bus protocol. The High-Speed Read instruction, 0BH, is supported in both SPI bus protocol and SQI protocol. On power-up, the device is set to use SPI.
SST26VF032B / SST26VF032BA 5.7 SPI Quad-Output Read The SPI Quad-Output Read instruction supports up to 104 MHz frequency. SST26VF032B requires the IOC bit in the configuration register to be set to ‘1’ prior to executing the command. Initiate SPI Quad-Output Read by executing an 8-bit command, 6BH, followed by address bits A[23-0] and a dummy byte. CE# must remain active low for the duration of the SPI Quad Mode Read. See Figure 5-8 for the SPI Quad Output Read sequence.
SST26VF032B / SST26VF032BA 5.8 SPI Quad I/O Read The SPI Quad I/O Read (SQIOR) instruction supports up to 104 MHz frequency. SST26VF032B requires the IOC bit in the configuration register to be set to ‘1’ prior to executing the command. Initiate SQIOR by executing an 8-bit command, EBH. The device then switches to 4-bit I/O mode for address bits A[23-0], followed by the Set Mode configuration bits M[7:0], and two dummy bytes.CE# must remain active low for the duration of the SPI Quad I/O Read.
SST26VF032B / SST26VF032BA FIGURE 5-10: BACK-TO-BACK SPI QUAD I/O READ SEQUENCES WHEN M[7:0] = AXH CE# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 SCK SIO0 b4 b0 b4 b0 A20 A16 A12 A8 A4 A0 M4 M0 X X X X b4 b0 SIO1 b5 b1 b5 b1 A21 A17 A13 A9 A5 A1 M5 M1 X X X X b5 b1 SIO2 b6 b2 b6 b2 A22 A18 A14 A10 A6 A2 M6 M2 X X X X b6 b2 MSN LSN SIO3 b7 b3 b7 b3 A23 A19 A15 A11 A7 A3 M7 M3 X X X X b7 b3 Data Data Byte Byte N+1 N Set Mode Address Dummy Data Byte 0 20005218 F50.
SST26VF032B / SST26VF032BA FIGURE 5-12: SET BURST LENGTH SEQUENCE (SPI) CE# MODE 3 SCK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 MODE 0 SIO0 C0 DIN SIO[3:1] 20005218 F51.0 Note: SIO[3:1] must be driven VIH. 5.10 SQI Read Burst with Wrap (RBSQI) SQI Read Burst with wrap is similar to High Speed Read in SQI mode, except data will output continuously within the burst length until a low-to-high transition on CE#.
SST26VF032B / SST26VF032BA 5.12 SPI Dual-Output Read Following the dummy byte, the SST26VF032B/032BA outputs data from SIO[1:0] starting from the specified address location. The device continually streams data output through all addresses until terminated by a lowto-high transition on CE#. The internal address pointer automatically increments until the highest memory address is reached, at which point the address pointer returns to the beginning of the address space.
SST26VF032B / SST26VF032BA FIGURE 5-14: SPI DUAL I/O READ SEQUENCE CE# MODE 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 MODE 0 SCK SIO0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 BBH SIO1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 A[23:16] A[7:0] A[15:8] M[7:0] CE#(cont’) 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 SCK(cont’) I/O Switches from Input to Output SIO0(cont’) 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 MSB SIO1(cont’) MSB MSB MSB 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 Byte 0 Byte 2 Byte 1 B
SST26VF032B / SST26VF032BA 5.14 JEDEC-ID Read (SPI Protocol) Immediately following the command cycle, SST26VF032B/032BA output data on the falling edge of the SCK signal. The data output stream is continuous until terminated by a low-to-high transition on CE#. The device outputs three bytes of data: manufacturer, device type, and device ID, see Table 5-4. See Figure 5-16 for instruction sequence.
SST26VF032B / SST26VF032BA 5.16 Serial Flash Discoverable Parameters (SFDP) ware support for all future Serial Flash device families. See Table 11-1 on page 58 for address and data values. The Serial Flash Discoverable Parameters (SFDP) contain information describing the characteristics of the device. This allows device-independent, JEDEC IDindependent, and forward/backward compatible soft- FIGURE 5-18: Initiate SFDP by executing an 8-bit command, 5AH, followed by address bits A[23-0] and a dummy byte.
SST26VF032B / SST26VF032BA 5.18 Block-Erase To execute a Block-Erase operation, the host drives CE# low then sends the Block-Erase command cycle (D8H), three address cycles, then drives CE# high. Address bits AMS-A13 determine the block address (BAX); the remaining address bits can be VIL or VIH. For 32 KByte blocks, A14:A13 can be VIL or VIH; for 64 KByte blocks, A15:A13 can be VIL or VIH.
SST26VF032B / SST26VF032BA 5.19 Chip-Erase To execute a Chip-Erase operation, the host drives CE# low, sends the Chip-Erase command cycle (C7H), then drives CE# high. Poll the BUSY bit in the Status register, or wait TSCE, for the completion of the internal, self-timed, Write operation. See Figures 5-23 and 5-24 for the Chip Erase sequence. The Chip-Erase instruction clears all bits in the device to ‘1.’ The Chip-Erase instruction is ignored if any of the memory area is protected.
SST26VF032B / SST26VF032BA 5.20 Page-Program partial Byte to be ignored. Poll the BUSY bit in the Status register, or wait TPP, for the completion of the internal, self-timed, Write operation. See Figures 5-25 and 5-26 for the Page-Program sequence. The Page-Program instruction programs up to 256 Bytes of data in the memory, and supports both SPI and SQI protocols. The data for the selected page address must be in the erased state (FFH) before initiating the Page-Program operation.
SST26VF032B / SST26VF032BA 5.21 SPI Quad Page-Program The SPI Quad Page-Program instruction programs up to 256 Bytes of data in the memory. The data for the selected page address must be in the erased state (FFH) before initiating the SPI Quad Page-Program operation. A SPI Quad Page-Program applied to a protected memory area will be ignored. SST26VF032B requires the ICO bit in the configuration register to be set to ‘1’ prior to executing the command.
SST26VF032B / SST26VF032BA 5.24 Write Suspend During Page Programming or SPI Quad Page Programming Issuing a Write-Suspend instruction during Page Programming allows the host to erase or read any sector that is not being programmed. Erase commands pointing to the suspended sector(s) will be ignored. Any attempt to read from the suspended page will output unknown data because the program will be incomplete.
SST26VF032B / SST26VF032BA 5.28 Lockout Security ID mands function in both SPI and SQI modes. The Status register may be read at any time, even during a Write operation. When a Write is in progress, poll the BUSY bit before sending any new commands to assure that the new commands are properly received by the device. The Lockout Security ID instruction prevents any future changes to the Security ID, and is supported in both SPI and SQI modes. Prior to the operation, execute WREN.
SST26VF032B / SST26VF032BA 5.30 Write-Status Register (WRSR) low, then sends the Write-Status Register command cycle (01H), two cycles of data, and then drives CE# high. Values in the second data cycle will be accepted by the device. See Figures 5-30 and 5-31. The Write-Status Register (WRSR) command writes new values to the Configuration register.
SST26VF032B / SST26VF032BA 5.31 Write-Enable (WREN) Protection Register, Lock-Down Block-Protection Register, Non-Volatile Write-Lock Lock-Down Register, SPI Quad Page program, and Write-Status Register. To execute a Write Enable the host drives CE# low then sends the Write Enable command cycle (06H) then drives CE# high. See Figures 5-32 and 5-33 for the WREN instruction sequence.
SST26VF032B / SST26VF032BA 5.32 Write-Disable (WRDI) during any internal write operations. Any Write operation started before executing WRDI will complete. Drive CE# high before executing WRDI. The Write-Disable (WRDI) instruction sets the WriteEnable-Latch bit in the Status register to ‘0,’ preventing Write operations. The WRDI instruction is ignored FIGURE 5-34: To execute a Write-Disable, the host drives CE# low, sends the Write Disable command cycle (04H), then drives CE# high.
SST26VF032B / SST26VF032BA 5.33 Read Block-Protection Register (RBPR) After the command cycle, the device outputs data on the falling edge of the SCK signal starting with the most significant bit(s), see Table 5-6 for definitions of each bit in the Block-Protection register. The RBPR command does not wrap around. After all data has been output, the device will output 0H until terminated by a low-tohigh transition on CE#. Figures 5-36 and 5-37.
SST26VF032B / SST26VF032BA 5.34 Write Block-Protection Register (WBPR) To execute a Write Block-Protection Register operation the host drives CE# low, sends the Write Block-Protection Register command cycle (42H), sends 18 cycles of data, and finally drives CE# high. Data input must be most significant bit(s) first. See Table 5-6 for definitions of each bit in the Block-Protection register. See Figures 5-38 and 5-39.
SST26VF032B / SST26VF032BA 5.35 Lock-Down Block-Protection Register (LBPR) cycling; this allows the Block-Protection register to be changed. Execute WREN before initiating the LockDown Block-Protection Register instruction. The Lock-Down Block-Protection Register instruction prevents changes to the Block-Protection register during device operation.
SST26VF032B / SST26VF032BA 5.36 Non-Volatile Write-Lock LockDown Register (nVWLDR) After CE# goes high, the non-volatile bits are programmed and the programming time-out must complete before any additional commands, other than Read Status Register, can be entered. Poll the BUSY bit in the Status register, or wait TPP, for the completion of the internal, self-timed, Write operation. Data inputs must be most significant bit(s) first.
SST26VF032B / SST26VF032BA 5.37 Global Block-Protection Unlock (ULBPR) To execute a ULBPR instruction, the host drives CE# low, then sends the ULBPR command cycle (98H), and then drives CE# high. The Global Block-Protection Unlock (ULBPR) instruction clears all write-protection bits in the Block-Protection register, except for those bits that have been locked down with the nVWLDR command. Execute WREN before initiating the ULBPR instruction.
SST26VF032B / SST26VF032BA TABLE 5-6: BLOCK-PROTECTION REGISTER FOR SST26VF032B/032BA (1 OF 2)1 BPR Bits Read Lock Write Lock/ nVWLDR2 79 78 3FE000H - 3FFFFFH 8 KByte 77 76 3FC000H - 3FDFFFH 8 KByte 75 74 3FA000H - 3FBFFFH 8 KByte 73 72 3F8000H - 3F9FFFH 8 KByte Address Range Protected Block Size 71 70 006000H - 007FFFH 8 KByte 69 68 004000H - 005FFFH 8 KByte 67 66 002000H - 003FFFH 8 KByte 65 DS20005218C-page 40 64 000000H - 001FFFH 8 KByte 63 3F0000H - 3F7FFFH 32 K
SST26VF032B / SST26VF032BA TABLE 5-6: BLOCK-PROTECTION REGISTER FOR SST26VF032B/032BA (CONTINUED) (2 OF BPR Bits Read Lock Write Lock/ nVWLDR2 Address Range Protected Block Size 28 1D0000H - 1DFFFFH 64 KByte 27 1C0000H - 1CFFFFH 64 KByte 26 1B0000H - 1BFFFFH 64 KByte 25 1A0000H - 1AFFFFH 64 KByte 24 190000H - 19FFFFH 64 KByte 23 180000H - 18FFFFH 64 KByte 22 170000H - 17FFFFH 64 KByte 21 160000H - 16FFFFH 64 KByte 20 150000H - 15FFFFH 64 KByte 19 140000H - 14FFFFH 64 KByte
SST26VF032B / SST26VF032BA 6.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.
SST26VF032B / SST26VF032BA FIGURE 6-1: POWER-UP TIMING DIAGRAM VDD VDD Max Chip selection is not allowed. Commands may not be accepted or properly interpreted by the device. VDD Min TPU-READ TPU-WRITE Device fully accessible Time 20005218 F27.0 FIGURE 6-2: POWER-DOWN AND VOLTAGE DROP DIAGRAM VDD VDD Max No Device Access Allowed VDD Min TPU Device Access Allowed VOFF TPD Time 20005218 F72.0 2015 Microchip Technology Inc.
SST26VF032B / SST26VF032BA 7.0 DC CHARACTERISTICS TABLE 7-1: DC OPERATING CHARACTERISTICS (VDD = 2.7 - 3.6V) Limits Symbol Parameter IDDR1 Read Current IDDR2 Min Typ Max Units 8 15 mA VDD=VDD Max, CE#=0.1 VDD/0.9 VDD@40 MHz, SO=open Read Current 20 mA VDD = VDD Max, CE#=0.1 VDD/0.
SST26VF032B / SST26VF032BA 8.0 AC CHARACTERISTICS TABLE 8-1: AC OPERATING CHARACTERISTICS (VDD = 2.7 - 3.6V) Limits - 40 MHz Symbol Parameter FCLK Serial Clock Frequency Min Max Limits - 80 MHz Min 40 Max Limits - 104 MHz Min 80 Max Units 104 MHz TCLK Serial Clock Period TSCKH Serial Clock High Time TSCKL Serial Clock Low Time 11 5.5 4.5 ns TSCKR1 Serial Clock Rise Time (slew rate) 0.1 0.1 0.1 V/ns TSCKF1 Serial Clock Fall Time (slew rate) 0.1 0.1 0.
SST26VF032B / SST26VF032BA FIGURE 8-1: HOLD TIMING DIAGRAM CE# THHH THHS THLS SCK THZ THLH TLZ SO SI HOLD# 20005218 F43.1 FIGURE 8-2: SERIAL INPUT TIMING DIAGRAM TCPH CE# TCHH TCES TSCKF TCEH TCHS SCK TDS SIO[3:0] TDH TSCKR LSB MSB 20005218 F70.1 FIGURE 8-3: SERIAL OUTPUT TIMING DIAGRAM CE# TSCKH TSCKL SCK TCLZ SIO[3:0] TOH TCHZ LSB MSB TV TABLE 8-2: 20005218 F25.
SST26VF032B / SST26VF032BA FIGURE 8-4: RESET TIMING DIAGRAM TCPH CE# MODE 3 MODE 3 MODE 3 MODE 0 MODE 0 MODE 0 CLK SIO(3:0) C1 C0 C3 C2 20005218 F14.0 Note: C[1:0] = 66H; C[3:2] = 99H FIGURE 8-5: AC INPUT/OUTPUT REFERENCE WAVEFORMS VIHT VHT INPUT VHT REFERENCE POINTS VLT OUTPUT VLT VILT 20005218 F28.0 AC test inputs are driven at VIHT (0.9VDD) for a logic ‘1’ and VILT (0.1VDD) for a logic ‘0’. Measurement reference points for inputs and outputs are VHT (0.6VDD) and VLT (0.4VDD).
SST26VF032B / SST26VF032BA 9.0 PACKAGING INFORMATION 9.1 Package Marking 8-Lead SOIJ (5.28 mm) Example 26F032B SM e3 1506343 8-Lead WDFN (5x6 mm) Example 26F032B MF e3 1506343 XXXXXXXX XXXXXXXX YYWWNNN 24-Ball TBGA (6x8 mm) Example XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 26F032B TD e3 1506343 Part Number 1st Line Marking Codes SOIJ WDFN TBGA SST26VF032B 26F032B 26F032B 26F032B SST25VF032BA 26F032B 26F032B 26F032B Legend: XX...
SST26VF032B / SST26VF032BA 8-Lead Plastic Very, Very Thin Small Outline No-Lead (MF) - 5x6 mm Body [WDFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A B N (DATUM A) (DATUM B) E NOTE 1 2X 0.15 C 1 2 2X 0.15 C TOP VIEW A1 0.10 C C A SEATING PLANE A3 SIDE VIEW 0.08 C 0.10 C A B D2 e 1 2 0.10 C A B NOTE 1 E2 K N 8Xb 0.10 0.
SST26VF032B / SST26VF032BA 8-Lead Plastic Very, Very Thin Small Outline No-Lead (MF) - 5x6 mm Body [WDFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.
SST26VF032B / SST26VF032BA Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2015 Microchip Technology Inc.
SST26VF032B / SST26VF032BA Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20005218C-page 52 2015 Microchip Technology Inc.
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SST26VF032B / SST26VF032BA TABLE 9-1: REVISION HISTORY Revision Description Date A • Initial release of data sheet Oct 2013 B • • • • Updated “Features” on page 1 Revised “SPI Dual I/O Read” on page 22 Updated Figure 5-29 on page 31 and Figure 5-31 on page 32 Significantly revised Table 11-1 on page 58 Apr 2014 C • • • Revised “Product Description” on page 1 Added Part Markings Added footnote to Table 7-4 on page 44 Feb 2015 2015 Microchip Technology Inc.
SST26VF032B / SST26VF032BA THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
SST26VF032B / SST26VF032BA 10.0 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X Device Tape/Reel Indicator XXX X Operating Frequency Temperature – / XX Package Device: SST26VF032B = 32 Mbit, 2.7-3.6V, SQI Flash Memory WP#/Hold# pin Enable at power-up SST26VF032BA = 32 Mbit, 2.7-3.
SST26VF032B / SST26VF032BA 11.0 APPENDIX TABLE 11-1: Address SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (1 OF 16) Bit Address Data Comments SFDP Header SFDP Header: 1st DWORD 00H A7:A0 53H 01H A15:A8 46H 02H A23:A16 44H 03H A31:A24 50H SFDP Signature SFDP Signature=50444653H SFDP Header: 2nd DWORD 04H A7:A0 06H SFDP Minor Revision Number 05H A15:A8 01H SFDP Major Revision Number 06H A23:A16 02H Number of Parameter Headers (NPH)=3 07H A31:A24 FFH Unused.
SST26VF032B / SST26VF032BA TABLE 11-1: SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (CONTINUED) (2 OF 16) Address Bit Address Data Comments 13H A31:A24 06H Parameter Table Length Number of DWORDs that are in the Parameter table JEDEC Flash Parameter Header: 4th DWORD 14H A7:A0 00H 15H A15:A8 01H 16H A23:A16 00H 17H A31:A24 FFH Parameter Table Pointer (PTP) This 24-bit address specifies the start of this header’s Parameter Table in the SFDP structure. The address must be DWORD-aligned.
SST26VF032B / SST26VF032BA TABLE 11-1: SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (CONTINUED) (3 OF 16) Address Bit Address Data Comments 31H A15:A8 20H 4 KByte Erase Opcode Supports (1-1-2) Fast Read 0: (1-1-2) Fast Read NOT supported 1: (1-1-2) Fast Read supported A16 Address Bytes Number of bytes used in addressing flash array read, write and erase 00: 3-Byte only addressing 01: 3- or 4-Byte addressing (e.g.
SST26VF032B / SST26VF032BA TABLE 11-1: Address SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (CONTINUED) (4 OF 16) Bit Address Data Comments 08H (1-1-4) Fast Read Number of Wait states (dummy clocks) needed before valid output 01000b: 8 dummy bits are needed with a single input opcode & address and quad output data Fast Read Instruction A20:A16 3AH (1-1-4) Fast Read Number of Mode Bits 000b: No mode bits are needed with a single input opcode & address and quad output data Fast Read Instruction A23:A21
SST26VF032B / SST26VF032BA TABLE 11-1: Address SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (CONTINUED) (5 OF 16) Bit Address Data th JEDEC Flash Parameter Table: 6 Comments DWORD 44H A7:A0 FFH Reserved. Bits default to all 1’s. 45H A15:A8 FFH Reserved. Bits default to all 1’s.
SST26VF032B / SST26VF032BA TABLE 11-1: Address SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (CONTINUED) (6 OF 16) Bit Address Data JEDEC Flash Parameter Table: 10 th A7:A4 Erase Type 1 Erase, Typical time Typical Time = (count +1)*units 1ms to 32ms, 16ms to 512ms, 128ms to 4096ms, 1s to 32s 10:9 units (00b:1ms, 01b: 16ms, 10b:128ms, 11b:1s) A8:A4 count = 12 = 10010b A10:A9 unit = 1ms = 00b A10:A8 A10:A8=001b A15:A11 Erase Type 2 Erase, Typical time Typical time = (count+1)*units 1ms to 32ms, 16ms to
SST26VF032B / SST26VF032BA TABLE 11-1: Address SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (CONTINUED) (7 OF 16) Bit Address Data A18:A16=101b A18:A16 5AH A23:A19 1DH A30:A:24 5BH Comments 81H Byte Program Typical time, Additional Byte Typical time = (count+1)*units 23 units (0b: 1µs, 1b: 8µs) A22:A19 count = 0011b A23=1μs=0b Chip Erase Typical Time Typical time = (count+1)*units 16ms to 512ms, 256ms to 8192ms, 4s to 128s, 64s to 2048s A28:A24 count =1=00001b A30:A29 units =16ms=00b Reserved A31=1
SST26VF032B / SST26VF032BA TABLE 11-1: Address 5EH SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (CONTINUED) (8 OF 16) Bit Address Data Comments A19:A16 0111b A23:A20 Erase Resume to Suspend Interval The device requires this typical amount of time to make progress on the erase operation before allowing another suspend.
SST26VF032B / SST26VF032BA TABLE 11-1: Address 69H 6AH SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (CONTINUED) (9 OF 16) Bit Address Data Comments A8 4-4-4 mode enable sequences A8 = 0 A9 0-4-4 mode supported 0:not supported 1:supported C2H A15:A10 0-4-4 Mode Exit Method X1_xxxx:Mode Bit[7:0] Not= AXh 1x_xxxx Reserved = 1 A19:A16 0-4-4 Mode Entry Method X1xxb: M[7:0]=AXh 1xxxb:Reserved =1 A22:A20 Quad Enable Requirements (QER) 101b: Quad Enable is bit 1 of the configuration register.
SST26VF032B / SST26VF032BA TABLE 11-1: Address SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (CONTINUED) (10 OF 16) Bit Address Data Comments Region 0 Size 4 * 8 KBytes = 32 KBytes Count=32 KBytes/256 Bytes= 128 Value = count -1 =127 A31:A8 = 00007Fh 105H A15:A8 7FH 106H A23:A16 00H 107H A31:A24 00H 108H A7:A0 F5H Region 1 supports 4 KByte erase and 32 KByte erase A3:A0 = 0101b A7:A4=Reserved = 1111b Region 1 size 1 * 32Kbytes = 32Kbytes Count=32Kbytes/256 bytes= 128 Value = count -1 =127 A31:A
SST26VF032B / SST26VF032BA TABLE 11-1: Address SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (CONTINUED) (11 OF 16) Bit Address Data Comments SST26VF032B/032BA (Vendor) Parameter Table SST26VF032B/032BA Identification 200H A7:A0 BFH Manufacturer ID 201H A15:A8 26H Memory Type 202H A23:A16 42H Device ID SST26VF032B/032BA=42H 203H A31:A24 FFH Reserved. Bits default to all 1’s.
SST26VF032B / SST26VF032BA TABLE 11-1: Address 206H SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (CONTINUED) (12 OF 16) Bit Address Data A16 OTP Capable (Security ID) Supported 0: not supported 1: supported A17 Supports Block Group Protect 0: not supported 1: supported A18 FDH Reserved. Bits default to all 1’s.
SST26VF032B / SST26VF032BA TABLE 11-1: SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (CONTINUED) (13 OF 16) Address Bit Address Data Comments 21AH A23:A16 FFH Max. time out from Deep Power-Down mode to Standby mode 0FFH = Reserved 21BH A31:A24 FFH Reserved. Bits default to all 1’s. 21CH A23:A16 FFH Reserved. Bits default to all 1’s. 21DH A31:A24 FFH Reserved. Bits default to all 1’s. 21EH A23:A16 FFH Reserved. Bits default to all 1’s. 21FH A31:A24 FFH Reserved.
SST26VF032B / SST26VF032BA TABLE 11-1: Address SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (CONTINUED) (14 OF 16) Bit Address Data Comments 06H (4-4-4) SQI nB Burst with Wrap Number of Wait states (dummy clocks) needed before valid output 00110b: 6 clocks of dummy cycle A20:A16 23EH (4-4-4) SQI nB Burst with Wrap Number of Mode Bits 000b: Set Mode bits are not supported A23:A21 23FH A31:A24 0CH (4-4-4) SQI nB Burst with Wrap Opcode 00H (1-1-1) Read Memory Number of Wait states (dummy clocks) nee
SST26VF032B / SST26VF032BA TABLE 11-1: Address SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (CONTINUED) (15 OF 16) Bit Address Data Comments 24FH A31:A24 06H Section 1 (bottom) Block Protection Bit End ((2m) +1)+ c, c=06H or 6, m= 6 for 32 Mb Address bits are Read Lock bit locations and Even Address bits are Write Lock bit locations. The most significant (left-most) bit indicates the sign of the integer; it is sometimes called the sign bit.
SST26VF032B / SST26VF032BA TABLE 11-1: Address SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (CONTINUED) (16 OF 16) Bit Address 25EH A23:A16 25FH A31:A24 Data Comments 07H Section 5 Block Protection Bit Start ((2m) +1)+ c, c=07H or 7, m= 6 for 32 Mb Address bits are Read Lock bit locations and Even Address bits are Write Lock bit locations. The most significant (left-most) bit indicates the sign of the integer; it is sometimes called the sign bit.
SST26VF032B / SST26VF032BA 11.1.3 BLOCK-PROTECTION REGISTER BIT START LOCATION (BPSL) Block-Protection Register Bit Start Location (BPSL) designates the start bit location in the Block-Protection Register where the first sector/block of this Major Section begins. If the value of BPSL is 00H, this location is the 0 bit location. If the value is other than 0, then this value is a constant value adder (c) for a given formula, (2m + 1) + (c). See “Memory Configuration”.
SST26VF032B / SST26VF032BA m will have a constant value for specific densities and is defined as: • • • • • 8Mbit = 4 16Mbit = 5 32Mbit = 6 64Mbit = 7 128Mbit = 8 Block Protect Register Start/End Bits are mapped in the SFDP by using the formula (2m + 1) + (c). “m” is a constant value that represents the different densities from 8Mbit to 128Mbit (used also in the formula calculating number of 64Kbyte Blocks above).
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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