Datasheet

USB251xB/xBi
DS00001692C-page 32  2010 - 2015 Microchip Technology Inc.
5.1.32 REGISTER FFH: STATUS/COMMAND
5.2 I
2
C EEPROM
The hub can be configured via a 2-wire (I
2
C) EEPROM (256x8). See Table 5-1 for details on enabling the I
2
C EEPROM
interface. The I
2
C EEPROM interface implements a subset of the I
2
C Master Specification (refer to the Philips Semi-
conductor Standard I
2
C-Bus Specification I
2
C protocol for details). The hub’s interface is designed to attach to a single
dedicated I
2
C EEPROM which conforms to the Standard-mode I
2
C specification (100 kbit/s transfer rate and 7-bit
addressing) for protocol and electrical compatibility. The I
2
C EEPROM shares the same pins as the SMBus interface,
therefore the SMBus interface is not available when the I
2
C EEPROM interface has been enabled (and vice versa).
The hub acts as the master and generates the serial clock SCL, controls the bus access (determines which device acts
as the transmitter and which device acts as the receiver), and generates the START and STOP conditions. The hub will
read the external EEPROM for configuration data and then attach to the upstream USB host.
The hub does not have the capacity to write to the external EEPROM. The hub only has the capability to read from an
external EEPROM. The external EEPROM will be read (even if it is blank), and the hub will be configured with the values
that are read. Any values read for unsupported registers will not be retained (i.e., they will remain as the default values).
Reserved registers should be set to
0 unless otherwise specified. EEPROM reset values are 0x00. Contents read from
unavailable registers should be ignored.
5.2.1 I
2
C SLAVE ADDRESS
The 7-bit slave address is 1010000b.
5.2.2 PROTOCOL IMPLEMENTATION
The hub will only access an EEPROM using the sequential read protocol as outlined in Chapter 8 of MicroChip
24AA02/24LC02B
[4].
5.2.3 PULL-UP RESISTOR
The circuit board designer is required to place external pull-up resistors (10 k recommended) on the SDA/SMBDATA
and SCL/SMBCLK/CFG_SEL[0] lines (per
SMBus 1.0 Specification [3], and EEPROM manufacturer guidelines) to
VDD33 in order to assure proper operation.
Bit Number Bit Name Description
7:3 rsvd
2 INTF_PW_DN SMBus Interface Power Down:
0 : interface is active
1 : interface power down after ACK has completed
1 RESET Reset the SMBus interface and internal memory back to RESET_N assertion
default settings.
0 : normal run/idle state
1 : force a reset of registers to their default state
0 USB_ATTACH USB Attach (and write protect)
0 : SMBus slave interface is active
1 : the hub will signal a USB attach event to an upstream device, and the
internal memory (address range 0x00-0xFE) is write-protected to prevent
unintentional data corruption.
Note: If no external EEPROM is present, the hub will write 0 to all configuration registers.
Note: 10-bit addressing is not supported.