Specifications

How to Write Synthesizable VHDL
3-10 VHDL Reference Manual
end process;
end example;
Case Statement
Like the with statement, VHDL requires that all the possible conditions
be represented in the condition of a case statement. To ensure this,
use the others clause at the end of a case statement to cover any
unspecified conditions.
Note: Since std_ulogic and std_logic types have nine possible values
(instead of two possible values for bit types), you should always
include an others clause when using these types.
The following example illustrates the case statement:
entity control_stmts is
port (sel: in bit_vector (0 to 1); a,b,c,d: in bit;
m: out bit);
end control_stmts;
architecture example of control_stmts is
begin
process (sel,a,b,c,d)
begin
case sel is
when b"00" => m <= c;
when b"01" => m <= d;
when b"10" => m <= a;
when others => m <= b;
end case;
end process;
end example;
Schematic representations of the if and case logic generated for these
two examples are shown in Figure 3-4.
Figure 3-4: Control Statements