Specifications

How to Write Synthesizable VHDL
3-14 VHDL Reference Manual
Figure 3-5: Loop and Subprogram Statements
Gen2: if test_flag = 1 generate
test_pins <= current_state;
end generate Gen2;
When an if generation statement is used, the conditional expression
(in this case "test_flag = 1") must be a metalogic value (one that does
not depend on a signal or variable.) For example, the value of i, used
in the previous for generation statement, is a static value and can be
used in a nested if generation statement, as follows:
for i in 0 to 3 generate
if i /= 2 generate
SM: modl port map A(i),B(i),Y(i);
end generate;
end generate;