Specifications

How to Write Synthesizable VHDL
VHDL Reference Manual 3-17
Alternatively, you can describe a latch as transparent low by inverting
the conditional logic:
process(clk)
begin
if clk='1' then
-- hold
else
y <= a;
end if;
end process;
Or more concisely:
process(clk)
begin
if clk='0' then
y <= a;
end if;
end process;
A rising edge flip-flop is created by making the clock input edge
sensitive:
process(clk)
begin
if clk'event and clk='1' then
y <= a;
end if;
end process;
If you are using the IEEE 1164 std_logic (or std_ulogic) data types,
you can simplify the description of clock edges (and improve the
accuracy of simulations) by using the rising_edge() function: