Specifications

How to Write Synthesizable VHDL
VHDL Reference Manual 3-21
Note: In examples 1, 3 and 4, above, the clk and clk'event
condition expression can be replaced with the IEEE 1164
rising_edge() function, if std_logic (or std_ulogic) is used for the
Clk signal. Using rising_edge() can improve the accuracy of
simulations, particularly in cases where you are simulating transitions
from uninitialized states.
Note: The concurrent conditional assignment shown in example 4 is
allowed in the 1076-1993 VHDL specification, and is not supported in
earlier versions of the language.
Gated Clocks and Clock Enable
The examples in this chapter have assumed that the clock is a simple
signal. In principle, any complex Boolean expression could be used to
specify clocking. The use of a complex clock expression implies a gated
clock.
As with any kind of hardware design, there is a risk that gated clocks
may cause glitches in the register clock, and hence produce unreliable
hardware. You need to be aware of the constraints of the target
hardware and, as a general rule, use only simple logic in the wait or
if-then expression.
It is possible to specify a gated clock with a statement such as:
if clk='1' and clk1'event and ena then
q <= d;
end if;
which implies a logical and in the clock line. If you want to use a clock
enable feature in the target device, however, you should use nested if
statements as follows:
if clk='1' and clk1'event then
if ena then
q <= d;
end if;
end if;
This style causes a clock enable feature to be specified in the target
architecture if the Generate Clock Enable property of the Synthesize
VHDL process is specified in the Project Navigator. If the Generate
Clock Enable property has not been specified, multiplexer logic will be
generated to hold the value of q when ena is low.