Specifications

How to Write Synthesizable VHDL
VHDL Reference Manual 3-23
elsif clk='1' and clk'event then
y <= a and b;
end if;
end process;
Devices with both an asynchronous reset and preset are also
supported, as long as the reset overrides the preset condition. For
example:
process (clk, reset, preset)
begin
if reset='1' then
y <='0'; -- must be a constant value
elsif preset='1' then
y <='1'; -- must be a constant value
elsif rising_edge(clk) then
y <= a and b;
end if;
end process;
Asynchronous Reset/Preset
You can combine the asynchronous reset and preset conditions in a
single process:
process (clk, reset, preset)
begin
if (reset = '1') then
q <= '0';
elsif (preset = '1') then
q <= '1';
elsif (rising_edge(clk)) then
q <= d;
end if;
end process;
Note that the asynchronous reset condition overrides the preset, as is
generally the case in most flip-flops that actually have both reset and
preset.