Specifications

VHDL Reference Manual 4-1
4. How to Control the
Implementation of VHDL
Using Enumerated Types
Enumerated types are very important in VHDL, and are the only way in
which signals that require more than two values (such as those with
output enables) can be described in the language.
For many circuits, most notably state machines, enumerated types can
help to make complex designs more readable, and can also help to
increase the efficiency of the resulting synthesized circuitry.
The VHDL synthesizer also gives you control over the encoding of
enumerated types, by providing you with a special attribute called
enum_encoding.
Enumerated types can reduce combinational logic requirements
because they make it easy to add don’t-care logic to a design. A don’t-
care (for the purpose of logic synthesis) is a circuit condition (a
combination of inputs, for example) under which the resulting output
of the circuit is not important. The VHDL synthesizer (and other
software, such as devices fitters) can take advantage of don’t-care
conditions to reduce the amount of logic required to implement a
combinational logic function.
A Review of Enumerated Types
Enumerated types in VHDL are user-defined (or predefined) data types
that are specified using symbolic representations. The state machine
template example presented earlier in this chapter was one example of
an enumerated type, and was declared with the following statement:
type states is (st0, st1, st2, st3);
Many of the standard types used in VHDL are actually enumerated
types defined in the standard library (std.vhd) or in the IEEE 1164
library (ieee.vhd). The types bit and Boolean, for example, are
enumerated types with the following definitions (from std.vhd):
type boolean is (false,true);
type bit is ('0','1');