Specifications

How to Control the Implementation of VHDL
VHDL Reference Manual 4-11
The problem with this code is that whenever the sum of a and b
exceeds 7, a fatal error will occur during simulation. To avoid this, the
code must be re-written to handle this boundary condition:
process(a, b)
variable a_var, b_var : integer range 0 to 15;
begin
a_var := a;
b_var := b;
if (a_var + b_var > 7) then
z <= a_var + b_var - 8;
else
z <= a_var + b_var;
end if;
end process;
This model correctly handles overflow conditions, but at great expense
in complexity of the code. More importantly, the synthesizer has no
way of knowing that this code is only present to handle simulation
issues, and will synthesize more logic than is really needed to
implement a 3-bit, unsigned adder.
Using Bit and Bit_vector Types
Types bit and bit_vector have the advantage of being built into the
VHDL language, and are therefore highly portable. These types also
have many disadvantages, however. The first is that built-in arithmetic
operators are not defined for bit_vector. You can overcome this
limitation by using the package bit_ops contained in the file
\synario\lib5\dataio.vhd supplied with your Synario installation. A
second and more serious limitation is the fact that bit may represent
only two states, ’0’ and ’1’. Therefore, it is impossible to model tristate
or wired logic properly using the bit type.
Using Std_ulogic and Std_ulogic_vector Types
Types std_ulogic and std_ulogic_vector are attractive since they allow
modeling of unknown, tristate, and other such logic states. As
unresolved types, though, they may not be used to model wired logic
or tristate buses. Also, there are no overloaded arithmetic operators
defined for std_ulogic_vector.
Using Std_logic and Std_logic_vector Types
Types std_logic and std_logic_vector offer numerous advantages. As
resolved types, they not only have the necessary logic states to model
tristate and wired logic, but they also allow for multiple drivers on the
same signal. Overloaded arithmetic operators are provided for
std_logic_vector in the package std_logic_ops found in the file
dataio.vhd. Overloaded textio functions are available as part of the
package std_logic_textio found in the file \synario\lib5\stdtxtio.vhd.
In addition, all new IEEE packages and libraries (such as VITAL or
1076.3) are based on std_logic. A final advantage of std_logic and
std_logic_vector is that it is the assumed type for wires and buses
drawn on a Synario schematic.