Specifications

How to Control the Implementation of VHDL
VHDL Reference Manual 4-13
Synthesis of Don't Cares
If you are designing using the type std_logic as your base type (as recommended
in the previous section) you are probably aware that one of the values in the
enumeration of std_logic is '-', which is commented in the std_logic_1164
package as meaning "don't care". Unfortunatly, none of the functions defined by
1164 actually give '-' such a meaning. For example, the following expression:
if ('1' = '-') then
...
end if;
will always evaluate to false during simulation.
Prior versions of Synario's VHDL synthesis compiler evaluated the '-' the same as
'0' in relational expressions.The IEEE 1076.3 standard has defined new
semantics for the '-' value that Synario now conforms to. In particular, any use of
the '-' value in an expression involving one of the relational operators (=, /=, >,
etc.) is defined to always return false. To get the simulation and synthesis
semantics of "don't cares" it is necesary to use the std_match functions defined in
the new numeric_std package. For example:
signal a,b,z : unsigned(3 downto 0);
.
.
z <= a when (std_match(b, "000-")) else "0000";
which makes the assignment to z conditional on only the left-most 3 bits of b.
Using Device Fitting Attributes
The VHDL synthesizer supports a small number of custom attributes
that can be used to control features of synthesis that are not normally
accessible from the VHDL language. These synthesis features include
control over pin placement, encoding of enumerated types and other
important optimization and device-related capabilities. All of the
custom attributes are defined in the file metamor.vhd, which can be
included in your VHDL source file with the following library and use
statements:
library metamor;
use metamor.attributes.all;
Alternatively, the required attribute declarations can be entered
directly into your VHDL source file. The declaration syntax for each
attribute is shown in the following subsections.