Specifications

How to Manage VHDL Design Hierarchies
6-6 VHDL Reference Manual
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end design_io;
Placing a use clause before an entity causes the contents of the
specified package contents to be visible to that entity and its
architecture(s), but nowhere else. This means that you must include a
use statement before each entity/architecture pair in the design that
requires access to package contents.
Package Visibility Rules
Standard VHDL package visibility rules ignore file boundaries, meaning
that a package could be in one file, the use clause and entity
declaration in another, and the architecture in a third file. The VHDL
synthesizer and Project Navigator, however, require that each entity
appear in the same source file as its corresponding architecture, and
that library and use statements appear in the same file as the entity
and architecture in which they are used.
For example, if the following library statement is placed in the VHDL
source file:
library my_lib;
then the VHDL synthesizer will analyze the file named my_lib.vhd in
the current directory, then the VHDL synthesizer will search for and
analyze the contents of a file called my_lib.vhd, looking first in the
current working directory and then in the \synario\lib5 directory. (Note
that library names cannot exceed 8 characters, to comply with DOS
filename restrictions.)
To make the library units within the library visible outside that library,
it is necessary to add the following statement to the VHDL source file:
use my_lib.my_package.all;
This use clause must be place just prior to (and in the same source file
as) any entity statement that requires access to the contents of
my_package. (You do not have to repeat the use statement prior to
the architectures associated with the entities; architecture design units
inherit the visibility rules of their parent entities.)
Design Libraries
Each package declaration that you write, and all other design units,
including entities and architectures, are compiled (during simulation or
synthesis) into a special area called a design library. In simulation
environments, if you do not specify a named library during
compilation, then the default library, work, is where the package will
be compiled. For packages that you place in the same source file in
which they are referenced, you will use the name work for all use
clause references to those packages.
Note: There are differences between the way in which the work
library is implemented in the VHDL synthesizer and many VHDL
simulation products. Refer to the information in the next section,
"Using Design Libraries," for a complete explanation.