AMD SP5100 Register Programming Requirements Technical Reference Manual Rev. 3.02 P/N: 44414_sp5100_rpr_pub_3.02 2012 Advanced Micro Devices, Inc.
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Table of Contents 1 Introduction ................................................................................................................ 7 1.1 About This Manual........................................................................................................................ 7 1.2 AMD SP5100 Block Diagram....................................................................................................... 8 1.3 Register Reference Information ...................................................
2.37 2.38 2.39 2.40 2.41 2.42 2.43 Watchdog Timer Resolution ....................................................................................................... 26 Supporting IDLE_EXIT# from CPU .......................................................................................... 27 Supporting HALT Message to Generate C1e.............................................................................. 27 LDT_PWRGD De-assertion with SLP_S3# .............................................................
.10 5.11 5.12 5.13 5.14 Enabling Lock Operation ............................................................................................................ 40 Enabling Additional Optional PCI Clock (PCICLK5) ................................................................ 41 Enabling One-Prefetch-Channel Mode ....................................................................................... 41 Disabling PCIB MSI Capability .............................................................................
7.9 Internal and External SATA Ports Indication Registers.............................................................. 60 7.10 Aggressive Link Power Management ......................................................................................... 60 7.11 SATA MSI and D3 Power State Capability ................................................................................ 61 7.11.1 SATA MSI Settings .........................................................................................................
1 Introduction 1.1 About This Manual This document lists the register settings required for the proper operation of the AMD SP5100 (previously referred to as SB700S). Current sampling of AMD SP5100 is with silicon revision A14 and A15, with the latter being the production part. This document covers settings for prior revision A12 (used exclusively for SB7xx products) as a reference since the SP5100 CIMx is shared between SP5100 and SB7xx.
1.2 AMD SP5100 Block Diagram This section contains a block diagram for the SP5100. Figure 1 below shows the SP5100 internal PCI devices and major functional blocks. Alink Express II AB B-LINK A-LINK PORT 1 PORT 0 12 USB2.0 + 2 USB1.
1.3 Register Reference Information Tables within this document contain information showing the applicable revision, recommended settings, and comments associated with the register.
2 ACPI/SMBUS Controller (bus-0, dev-20, fun-0) 2.1 Enabling Legacy Interrupt ASIC Rev All Revs SP5100 2.
ASIC Rev Register Settings Function/Comment All Revs SP5100 PM_IO 0x9A [4] = 1 For system with dual core CPU, set this bit to 1 and BM_STS will cause C3 to wakeup regardless of BM_RLD. All Revs SP5100 PM_IO 0x8F [5] = 1 Ignores BM_STS_SET message from NB All Revs SP5100 + PM_IO 0x8F [4] = 1 RS4x0 ASIC family of NB The SB will monitor BmReq# for C3 pop-up. The SB will de-assert LDTSTP# when BmReq# is active.
ASIC Rev Register Settings Function/Comment All Revs SP5100 PM_IO 0x7C [1] = 1 Set this bit to 1 to allow pop-up request being latched during the minimum LDTSTP# assertion time. Pop-up will happen thereafter even if the request has gone. All Revs SP5100 PM_IO 0x61 [2] = 0 This bit should be cleared to 0 if C3 pop-up is enabled. If this bit is set to 1, the BmReq# input or internal bus mastering will set BM_STS.
2.5 Enable C1e Stutter Timer and Limit Link Disconnect to < 20 ms ASIC Rev Register Settings Function/Comment Stutter timer settings The following settings will program the stutter timer settings. There are two different values that need to be applied based on the condition listed below.
2.6 MTC1e and FID VID Setting ASIC Rev Register Settings Function/Comment The following registers should be programmed only if FIDVID is enabled in conjunction with MTC1e SP5100 All Revs 2.7 PM_IO 0x9A [2] = 0 K8CpopUp is disabled PM_IO 0x7C 0] = 0 EnableBreak is disabled SATA USB SMBUS PATA AC97 HD AUDIO RTC ACPI PM_REG x A-LINK I/O REG XIOAPIC LPC PCI For register details refer to the sections check-marked in the SP5100 Register Reference Guide.
2.9 Enabling Non-Posted Memory Write ASIC Rev Register Settings All Revs SP5100 AXINDC:0x10 [9] = 1 Function/Comment Enables non-posted memory write. Programming Sequence: OUT AB_INDX, OUT AB_DATA, OUT AB_INDX, IN AB_DATA, OR TMP, OUT AB_DATA, 0x00000030 0x00000010 0x00000034 TMP 0x00000200 TMP // // // // // // Load AB_INDX with pointer to AX_INDXC Write 0x10 to AX_INDXC Load AB_INDX with pointer to AX_DATAC Read PCIE_CTL register (AXINDC:0x10) Set bit 9 Set PCIE_HT_NP_MEM_WRITE.
2.12 Output Drive Strength Settings ASIC Rev Register Settings Function/Comment All Revs SP5100 Smbus_PCI_config 0xC0 [29:0] Setting TBD These register bits configure the drive strength of each individual bus. Refer to the AMD SP5100 Register Reference Guide, SMBUS section describing the PCI config C0h for the recommended driving strength values. Note: For more detail please refer to the AMD SP5100 Register Reference Guide.
All Revs SP5100 Set to 0000_0000h when USB legacy support is disabled in internal USB host controller side. SW has to make sure that the USB Hc memory decoding is enabled in PCI configuration space command register. USB HC(bus0, dev 19, fun 0) MMio+160h USB HC(bus0, dev 20, fun 5) MMio+160h SATA RTC USB X ACPI SMBUS X PM REG Set to 0000_0000h when USB legacy support is disabled in internal USB host controller side.
2.17 Legacy DMA Prefetch Enhancement ASIC Rev Register Settings Function/Comment All Revs SP5100 Smbus_PCI_config 0x43 [0] = 1 (only when Enables legacy DMA prefetch enhancement for channel 0, the system is non-DOS mode) 1, 2, and 3. This bit should be set to improve DMA out (eg memory-to-floppy disk) performance. Note: This bit should only be enabled in the ACPI method (called by the OS). This ensures that it is enabled only when the system is in Window mode.
2.20 PCIe Native Mode ASIC Rev Register Settings Function/Comment Set to 1 to enable PCIe native mode. If PCIe is in Native mode: set the bit to 1. If PCIe is not in Native mode: set the bit to 0. All Revs SP5100 PM_IO 0x55 [3] PM_IO 0x10 [6] Set to 1 to make PCIE_WAK_DIS visible in ACPI Pm1a register group. If PCIe is in Native mode: set the bit to 1. If PCIe is not in Native mode: set the bit to 0. PM_IO 0x55 [4] Set to 0 to enable PCIE_WAK_DIS/PCIE_WAK_STS function.
2.22 Cir Interrupt Config ASIC Rev Register Settings All Revs SP5100 Smbus_PCI_config 0xE1[6] SATA USB RTC ACPI SMBUS X PM REG Function/Comment Set to 1 to treat Cir interrupt as level signal; otherwise it is edge.trigger: PATA AC97 HD AUDIO A-LINK I/O REG XIOAPIC LPC PCI For register details refer to the sections check-marked in the SP5100 Register Reference Guide 2.
2.25 CPU Reset ASIC Rev Register Settings Function/Comment All Revs SP5100 PM_IO 0xB2[2] = 1 SATA USB RTC ACPI SMBUS X PM REG Enables the CPU Reset timing option defined in PM register D5[1:0]. Required only if the default timing needs to be changed. PATA AC97 HD AUDIO A-LINK I/O REG XIOAPIC LPC PCI For register details refer to the sections check-marked in the SP5100 Register Reference Guide 2.
ASFSMbusIoBase- RW - 16 bits - [PCI_Reg: 58h] Field Name Reserved ASFSMBase • Bits Default 3:1 15:4 000b FFFh Description ASF SM bus controller Io base address Step 3: Disable Legacy Sensor support by programming bit[6] of ASF I/O 0Dh to 1 SlaveMisc- RW - 8 bits - [ASF_IO: 0Dh] Field Name Bits Default SlavePECError 0 0b SlaveBusCollision 1 0b SlaveDevError 2 0b WrongSP 3 0b Reserved SuspendSlave 4 5 0b 0b KillSlave 6 0b LegacySensorEn 7 0b • Description RO 0: No PEC error 1:
2.28 ACPI System Clock Setting ASIC Rev Register Settings Function/Comment All Revs SP5100 PMIO 0x53 [6] = 1 Enables the internally generated 14.318Mhz clock to the ACPI logic. SATA USB SMBUS PATA AC97 HD AUDIO RTC ACPI PM REG x A-LINK I/O REG XIOAPIC LPC PCI For register details refer to the sections check-marked in the SP5100 Register Reference Guide 2.
2.31 Alternate Pin for 14 MHz Clock Input ASIC Rev Register Settings Function/Comment The following change is required for SP5100 revision A14 and above and if the 14 MHz clock is connected to the SB on to 25M_48M_66M_OSC. This reference clock is required to resolve the revision A12 Errata item #5 in hardware instead of using the BIOS workaround. If external 14 MHz clock is not used on SP5100 rev A14 and above, then the BIOS workaround described in erratum #5 should be implemented.
2.33 SMBUS Block Write Filtering ASIC Rev Register Settings SP5100 A14 and Smbus_PCI_config 0x38 [7]=0 above Function/Comment Enable SMBUS filtering circuit. Setting this bit to 0 to enable SMBUS filtering (1194). THIS FEATURE WILL RESOLVE THE ISSUE DESCRIBED IN REVISION A12 ERRATA ITEM # 13. SATA USB RTC ACPI SMBUS x PM_REG PATA AC97 HD AUDIO A-LINK I/O REG XIOAPIC LPC PCI For register details, refer to the sections check-marked in the SP5100 Register Reference Guide. 2.
SATA USB SMBUS PATA AC97 HD AUDIO RTC ACPI PM_REG X A-LINK I/O REG XIOAPIC LPC PCI For register details, refer to the sections check-marked in the SP5100 Register Reference Guide. 2.36 Unconditional Shutdown ASIC Rev SP5100 A15 Register Settings Smbus_PCI_config 0x38[12] = 1 Function/Comment Enable the enhancement for unconditional shutdown Set sm cfg 43 bit 3 to 0 first before programming this bit, then set 43h bit 3 back to 1 after programming.
2.
2.40 LDT_PWRGD De-assertion with SLP_S3# ASIC Rev SP5100 A15 SATA USB RTC ACPI Register Settings Smbus_PCI_config 0x41 [3]=1 SMBUS x PM_REG Function/Comment Set this bit to 1 to force LDT_PWRGD to be de-asserted at the same time as SLP_S3#. PATA AC97 HD AUDIO A-LINK I/O REG XIOAPIC LPC PCI For register details, refer to the sections check-marked in the SP5100 Register Reference Guide. 2.
2.43 SMAF Matching Setting ASIC Rev Register Settings All Revs SP5100 Smbus_PCI_config 0x60 [22] = 1b SATA USB RTC ACPI SMBUS x PM_REG Function/Comment This bit is required to be set to cover a corner case of concurrent throttling and C1e PATA AC97 HD AUDIO A-LINK I/O REG XIOAPIC 2012 Advanced Micro Devices, Inc. AMD SP5100 Register Programming Requirements LPC PCI For register details, refer to the sections check-marked in the SP5100 Register Reference Guide.
3 LPC Controller (bus-0, dev-20, fun-3) 3.1 IO / Mem Decoding ASIC Rev All Revs SP5100 3.2 Register Settings Lpc_PCI_config 0xBB[7] = 1 Lpc_PCI_config 0xBB[6] = 1 Lpc_PCI_config 0xBB[3] = 1 Function/Comment These bits are required to be set for LPC PCI slave interface.
4 A-Link Express Settings - Indirect I/O Access 4.1 Defining AB_REG_BAR ASIC Rev Register Settings All Revs SP5100 Smbus_PCI_config 0xF0 [31:0] = AB_REG_BAR 4.2 SATA USB RTC ACPI SMBUS X PM REG Function/Comment Defines the AB I/O base address. Refer to AMD SP5100 Register Reference Guide, chapter 4: A-Link Express/A-Link Bridge Registers for more information.
4.3 Enabling Upstream DMA Access ASIC Rev Register Settings All Revs SP5100 AXCFG: 0x04 [2] = 1 Function/Comment Enables the SP5100 to issue memory read/write requests in the upstream direction. Programming Sequence: OUT IN OR OUT 4.
4.6 B-Link Client’s Credit Variable Settings for the Downstream Arbitration Equation ASIC Rev Register Settings All Revs SP5100 ABCFG 0x9C [0] = 1 4.7 Disables the credit variable in the downstream arbitration equation.
4.9 Enabling Detection of Upstream Interrupts ASIC Rev Register Settings Function/Comment All Revs SP5100 ABCFG 0x94 [20] = 1 Enables A-Link Express logic to detect upstream interrupts ABCFG 0x94 [19:0] = CPU interrupt delivery for the purposes of system management. address [39:20]. SATA USB SMBUS PATA AC97 HD AUDIO RTC ACPI PM REG A-LINK X I/O REG XIOAPIC LPC PCI For register details refer to the sections check-marked in the SP5100 Register Reference Guide 4.
4.12 Enabling AB and BIF Clock Gating ASIC Rev Register Settings All Revs SP5100 ABCFG 0x54[24] = 0 ABCFG 0x10054[24] = 1 ABCFG 0x98[11:8] = 0x7 Function/Comment Enables the AB and BIF clock-gating logic. SATA USB SMBUS PATA AC97 HD AUDIO RTC ACPI PM REG A-LINK X I/O REG XIOAPIC LPC PCI For register details refer to the sections check-marked in the SP5100 Register Reference Guide 4.
4.
4.19 Enabling Posted Pass Non-Posted Upstream ASIC Rev SP5100 A15 Register Settings ABCFG 0x58[11] = 1 ABCFG 0x58[15:12] = 0xE Function/Comment Posted pass non-posted upstream direction feature enable. SATA USB SMBUS PATA AC97 HD AUDIO RTC ACPI PM REG A-LINK X I/O REG XIOAPIC LPC PCI For register details, refer to the sections check-marked in the SP5100 Register Reference Guide. 4.
5 PCIB (PCI-bridge, bus-0, dev-20, fun-04) 5.1 Enabling PCI-bridge Subtractive Decode ASIC REV All Revs SP5100 5.2 Register Settings PCIB_PCI_config 0x40 [5] = 1 PCIB_PCI_config 0x4B [7]= 1 Enables the PCI-bridge subtractive decode. This setting is strongly recommended since it supports some legacy PCI add-on cards.
5.4 PCI Bus DMA Write Cacheline Alignment ASIC REV All Revs SP5100 5.5 Register Settings PCIB_PCI_config 0x40 [1] = 1 (default) Enables the PCIB writes to be cacheline aligned. The size of the writes will be set in the Cacheline Register (PCIB_PCI_config 0x4B[4:0]). Refer to section 5.3 for more information.
5.7 Enabling Idle To Gnt# Check ASIC REV All Revs SP5100 5.8 Register Settings PCIB_PCI_config 0x4B [0] = 1 (default) When enabled, the PCI arbiter checks for the Bus Idle before asserting GNT#. Note: This setting is recommended. SATA USB SMBUS PATA AC97 HD AUDIO RTC ACPI PM REG A-LINK I/O REG XIOAPIC LPC PCI X For register details refer to the sections check-marked in the SP5100 Register Reference Guide GNT# Timing Adjustment ASIC REV All Revs SP5100 5.
5.11 Enabling Additional Optional PCI Clock (PCICLK5) ASIC REV All Revs SP5100 Register Settings Function/Comment PCIB_PCI_config 0x64 [8] = 1 This only applies when PCICLK5/PCIREQ5#/PCIGNT5# are enabled: When this bit is set, PCICLK5, PCIREQ#5, and PCIGNT5# are enabled for PCI use. Since PCICLK5 is not enabled by default (the clock is off), the PCI device which uses this clock may not see the system reset during power-up.
5.14 Adjusting CLKRUN# ASIC REV All Revs SP5100 Register Settings PCIB_PCI_config 0x64 [15] = 0x1 Function/Comment This bit should be set to 1 for the proper operation of CLKRUN#. Note: This setting is mandatory. SATA USB SMBUS PATA AC97 HD AUDIO RTC ACPI PM REG A-LINK I/O REG XIOAPIC 2012 Advanced Micro Devices, Inc.
6 USB – OHCI & EHCI controllers (bus-0, dev-18/19, fun-00 ~02/ bus-0, dev-20, fun-05) Please note the following information for this section: • EHCI BAR address = EHCI_PCI_config 0x10[31:8] • EHCI_EOR is the EHCI operation register = EHCI_BAR + 0x20 • The device list for all USB Controllers is as follows: 6.
6.2 USB Device Support to Wake Up System from S3/S4 State ASIC Rev All Revs SP5100 Register Settings Function/Comment PM_IO 0x61 [6] = 1 PM_IO 0x65 [2] = 1 (default) Enables the USB PME event. Enables USB resume support. PM_IO 0x65 [6] = 1 Enable PME generation for USB Wake event from connect and disconnect of USB devices. Note: BIOS workaround A2 described in Appendix A must be implemented for this feature to work reliably. Without the workaround PME Wake for Connect/Disconnect of USB 1.
6.5 USB Reset Sequence ASIC Rev Register Settings Function/Comment All Revs SP5100 PM_IO 0x65 [4] = 1 Enables the USB controller to get reset by any software that generates a PCIRst# condition. However, this bit should be cleared before a software generated reset condition occurs during S3 resume so the USB controller will not lose the connection status during the S3 resume procedure. The software generated PCIRst# conditions include Keyboard Reset, or write to the IO-CF9 register. 6.
6.8 Adjusting USB 2.0 Ports Driving Strength ASIC Rev Register Settings All Revs SP5100 Step 1: Function/Comment Adjusts the USB2.0 ports driving strength. EHCI_BAR 0xB4 [2:0] = “HSADJ” EHCI_BAR 0xB4[12] = 0 EHCI_BAR 0xB4 [16:13] = “port#” HSADJ to set the driving strength value VLoadB to load the value to the PHY for selected port The selected port# The SBIOS can repeat step-1 for those ports with less margin on HS eye diagram.
6.10 OHCI MSI Function Setting ASIC Rev Register Settings All Revs SP5100 OHCI0_PCI_Config 0x40[9:8] = ”11” Function/Comment OHCI MSI function For normal operation the MSI function must be disabled by setting bits [9:8] on dev-18, fun-0, and dev-19, fun-0, OHCI controllers and bit [8] on dev-20, fun-5, OHCI controller. bus-0, dev-18 fun 0 / bus-0, dev-19 fun 0 bus-0, dev-20, fun-5.
6.13 Enabling Fix for EHCI Controller Driver Yellow Sign Issue ASIC Rev SP5100 A12 SATA RTC USB X ACPI Register Settings EHCI_PCI_Config 0x50[20] = 1 Function/Comment Enables the fix for the yellow sign issue observed when the HSET driver gets unloaded and the in box EHCI driver gets loaded. SMBUS PATA AC97 HD AUDIO PM REG A-LINK I/O REG XIOAPIC LPC PCI For register details refer to the sections check-marked in the SP5100 Register Reference Guide 6.
6.17 EHCI Dynamic Clock Gating Feature ASIC Rev Register Settings All Revs SP5100 EHCI_BAR 0xBC Bit[12] = 0 SATA RTC USB X ACPI Function/Comment For normal operation, the clock gating feature must be disabled. At system reset, this bit is set to “1”. So, BIOS needs to program this bit to “0”. EHCI clock gating setting must be programmed in both the EHCI host controllers.
6.20 Async Park Mode ASIC Rev Register Settings SP5100 All Revs EHCI PCI_Config 0x50[23] = 1 Function/Comment Async Park Mode function. For normal operation, the APM function should be disabled by setting the bit in both EHCI controllers: Bus-0 Dev-18 Func-2 and Bus 0 Dev-19 Func-2 If EHCI APM is enabled, some USB card reader devices may not work properly. The USB controller used on these devices may not be able to handle the short delay time between the data packets.
6.23 Advance Async Enhancement ASIC Rev SP5100 A12 Register Settings EHCI PCI Config 0x50[28] = 1 Function/Comment Advance asynchronous enhancement function. For normal operation, the AAE function should be disabled by setting the bit in both EHCI controllers: Bus-0 Dev-18 Func-2 and Bus-0 Dev-19 Func-2 Enabling this function may cause USB 2.0 device to malfunction or be undetected.
6.25 USB PID_ERROR_CHECKING ASIC Rev SP5100 A15 Register Settings EHCI_PCI_Config 0x50[9] =1 Function/Comment Set this bit to enable the Error checking on PID Bus-0 Dev-18 Func-2 and Bus 0 Dev-19 Func-2 SATA USB X SMBUS PATA AC97 HD AUDIO RTC ACPI PM REG A-LINK I/O REG XIOAPIC 2012 Advanced Micro Devices, Inc. LPC PCI For register details, refer to the sections check-marked in the SP5100 Register Reference Guide.
7 SATA: dev-17, func-0 7.1 Enabling SATA ASIC Rev All Revs SP5100 7.2 Register Settings Smbus_PCI_config 0xAC [8] = 1 Function/Comment Enables the SATA controller. SATA Initialization ASIC Rev Register Settings All Revs SP5100 Smbus_PCI_config 0xAC [28:26] SP5100 A12 This bit needs to be cleared to convert the subclass code register to read-only. Refer to section 7.6 for the SATA subclass programming sequence.
SP5100 A14 and above SATA_PCI_config 0x48 [13:7] = 7’h7F SATA_PCI_config 0x48 [14] = 0 ( default) SATA_PCI_config 0x48 [15] = 1 The setting to these register bits should be restored to 1 for A14 1. On resume from S3 and S4. 2. After warm boot reset. The registers listed here apply only to revision A14 and above. These bits enable enhancements made in the A14 and above to address compatibility or minor spec violation issues seen in simulation.
7.4 Disabling Unused SATA Ports ASIC Rev All Revs SP5100 Register Settings Function/Comment SATA_PCI_config 0x40 [16] = 1 When set, SATA port0 is disabled, and port0 clock is shut down. SATA_PCI_config 0x40 [17] = 1 When set, SATA port1 is disabled, and port1 clock is shut down. SATA_PCI_config 0x40 [18] = 1 When set, SATA port2 is disabled, and port2 clock is shut down. SATA_PCI_config 0x40 [19] = 1 When set, SATA port3 is disabled, and port3 clock is shut down.
7.5 SATA Subclass Programming Sequence The SATA controller supports the following modes: • • • IDE mode AHCI mode Raid mode The SBIOS programs the subclass code and the interface register to enable the SATA controller to be represented as the IDE controller, the AHCI controller, or the Raid controller. ASIC Rev All Revs SP5100 Register Settings Function/Comment 1.
7.6 SATA PHY Programming Sequence The SBIOS needs to program the SATA controllers in the following sequence. Performing this procedure gives enough time for the SATA controllers to correctly complete SATA drive detection. The SBIOS needs to do the same procedure after the system resumes back from the S3 state. Note: This will be added once the silicon comes back for PHY fine tune value. ASIC Rev All Revs SP5100 SATA X RTC Register Settings Function/Comment 1.
7.7 7.7.1 SATA Identification Programming Sequence for IDE Mode SATA Drive Detection The following sequence should be included in the SBIOS drive identification loop for SATA drives detection. ASIC Rev All Revs SP5100 Register Settings 1.
SATA X RTC 7.8 USB SMBUS PATA AC97 HD AUDIO ACPI PM REG A-LINK I/O REG XIOAPIC LPC PCI For register details refer to the sections check-marked in the SP5100 Register Reference Guide Restoring SATA Registers after S3 Resume State The following registers need to be restored by the SBIOS after S3 resume for the SATA controller. ASIC Rev All Revs SP5100 Register Settings Function/Comment SATA_PCI_config 0x09 [7:0] SATA_PCI_config 0x0A [7:0] Programmable interface and Subclass code.
7.9 Internal and External SATA Ports Indication Registers The following registers need to be programmed for eSATA ports ASIC Rev All Revs SP5100 Register Settings Function/Comment For the ports which are configured as iSATA PxCMD.ESP (External SATA Port) and PxCMD.HPCP ports. (Hot Plug Capable Port) registers should be programmed 1.PxCMD.ESP should leave as reset default to indicate if the port is used for External SATA and if it (logic 0). requires hot Plug capability. 2.PxCMD.HPCP should be cleared.
Sequence to disable ALPM: ASIC Rev All Revs SP5100 SATA X RTC Register Settings Function/Comment 1. SATA_PCI_config 0x40 [0] = 1 Unlocks the configuration register so that HBA AHCI Capabilities Register can be modified. 2. SATA_BAR5 + 0xFC [11] = 0 Clearing this bit has the following effects. The SupportAggressive-Link-Power-Management Capability is hidden from software in AHCI HBA Capabilities Register.
7.11.3 Capability Pointer Settings The following settings re-program the capability pointer to the recommended start of the capabilities table of supported features (hide MSI, and if S1 is supported, hide D3 state capability from driver/OS). ASIC Rev Register Settings Function/Comment All Revs SP5100 1. 2. 3. SATA_PCI_config 0x40 [0] = 1 SATA_PCI_config 0x61[7:0]=0x70 SATA_PCI_config 0x40 [0] = 0 D3 power state is visible. (If S1 is not supported) MSI capability for SATA is hidden.
8 LPC (bus-0, dev-20, fun-03) 8.1 Enabling/Disabling LPC Controller ASIC Rev All Revs SP5100 8.2 SATA USB RTC ACPI Register Settings Function/Comment Smbus_PCI_config 0x64 [20] = 1 (default) SMBUS X PM REG Enables the LPC controller.
9 IDE Controller (bus-0, dev-20, fun-01) The SP5100 IDE controller supports single primary channel, even though resources of the secondary IDE channel are allocated by the in-box driver from the Microsoft operating system. Therefore the IDE programmable interface (IDE PCI config 0x09 bits [3:2]) is not recommended for modification. 9.1 Disable Second IDE MSI Capability ASIC Rev All Revs SP5100 9.
10 HD Audio (bus-0, dev-20, fun-02) 10.1 Enabling/Disabling HD Audio ASIC Rev All Revs SP5100 Register Settings PM_IO 0x59[3] = 1 (default) Function/Comment 0 = Disables the HD Audio controller 1 = Enables the HD Audio controller SATA USB SMBUS PATA AC97 HD AUDIO RTC ACPI PM REG x A-LINK I/O REG XIOAPIC LPC PCI For register details refer to the sections check-marked in the SP5100 Register Reference Guide 10.
All Revs SP5100 Smbus_PCI_Config_Extend_Reg 0x00[5:4] Port 2 configuration for HD Audio/AC97/GPIO: = 10 (default) 00 or 11 = GPIO 01 = no function 10 = HD Audio Note: Port 2 refers to the ACZ_SDIN2/GPIO44 pin. All Revs SP5100 Smbus_PCI_Config_Extend_Reg 0x00[7:6] Port 3 configuration for HD Audio/AC97/GPIO: = 10 (default) 00 or 11 = GPIO 01 = no function 10 = HD Audio Note: Port 3 is the AZ_SDIN3/GPIO46 pin.
Appendix A: Sample Codes for BIOS Workarounds A1. Sample Code for SP5100 Erratum #11: “Enabling EHCI Dynamic Clock Gating May Cause Bug Code 0xFE System Error”. (Refer to section 6.17 “EHCI Dynamic Clock Gating Feature”) Note: This code is found in the SP5100 BIOS because SP5100 shares the same CIMx as the SB7xx. It has no relevance for the SP5100 but is included in case it shows up in a software debugging process.
or al, 02h out dx, eax mov eax, 080009210h mov dx, 0CF8h out dx, eax mov dx, 0CFCh in eax, dx mov edi, eax add edi, 0BCh mov eax, es:[edi] ;es should be set to 0, and the segment limit should be set 0 to 4GB and ax, 0EFFFh ;clear BIT12 mov es:[edi], eax EHCI1_BAR_NOT_SET: ;For EHCI controller 2 (Bus 0 Dev 0x13 Fun 2) ;read BAR address mov eax, 080009A10h mov dx, 0CF8h out dx, eax mov dx, 0CFCh in eax, dx cmp eax, 0 je EHCI2_BAR_NOT_SET cmp eax, -1 je EHCI2_BAR_NOT_SET ;enable memory access mov eax, 0800
mov eax, 080009A10h mov dx, 0CF8h out dx, eax mov dx, 0CFCh in eax, dx mov edi, eax add edi, 0BCh mov eax, es:[edi] ;es should be set to 0, and the segment limit should be set 0 to 4GB and ax, 0EFFFh ;clear BIT12 mov es:[edi], eax EHCI2_BAR_NOT_SET: popad End of Sample Code ( Erratum # 11) 2012 Advanced Micro Devices, Inc.
A2. Sample Code for SP5100 Erratum #23: “USB Wake on Connect/Disconnect with Low Speed Devices”. (Refer to section 6.2 “USB Device Support to Wake Up System from S3/S4 State”) The following workaround should be implemented in the platform BIOS to resolve the issue as described in the SB7x0 Erratum #23. This routine has to be put in the Sleep trap function.
mov call or call ah, 0c4h read_pci_dword_far ebx, 03h write_pci_dword_far ; Enabled EHCI1 & BAR mov dx, (19 shl 3) + 2 mov ah, 0c4h call read_pci_dword_far and ebx, 0fffffff0h call write_pci_dword_far mov call or call ah, 004h read_pci_dword_far ebx, 07h write_pci_dword_far mov mov call dx, (19 shl 3) + 2 ah, 10h read_pci_dword_far call mov mov call or call ; Set to D3 state ; EHCI 1 ; Set back to D0 state ; ; Enabled IO/Memory/Bus ; ; Get Bar address ; in EBX USBWorkaroundForConnected dx, (19 sh
Appendix B: Revision History Date Revisions Description July, 2012 3.02 • Added new section 6.22 Disable Async QH Cache. Dec 22, 2011 3.01 • • • Updated section 2.4 C-State and VID/FID Change. Added new section 2.6 MTC1e and FID VID Setting. Updated section 3.2 SPI Bus. Nov, 2010 3.00 • • Released as public version. Updated section 2.4 C-State and VID/FID Change: Added stutter time info for different conditions. Modified/combined previous section 2.26 and 2.
April 27, 2009 2.09 • • • • • • • • • • • • • • • • • • • Feb 09, 2009 2.08 • • • • • • • • • • • • • • • • • • • • • • • • • • Added ASIC revision A15 settings. General replacement of “A14” with “A14 and above”. Section 2.4 “C-State and VID/FID Change “: Updated description for PM_IO 0x8B. Section 2.16 ”PCIe Native Mode”: Changed setting from 1 to 0 for PM_IO 0x84[1]; added suggested settings. Updated section 2.20 “IMC Access Control” Updated section 2.28 “Revision ID”. Added new section 2.
September 11, 2008 2.07 • • • • • • • • • • March 05, 2008 1.02 • • February 08, 2008 1.01 • 1.00 Updated section 2.9: Enabling IRQ1/12 Filtering by updating the description for register setting Smbus_PCI_config 0x62 [1:0]. Added section 6.15: EHCI Async Park Mode. • Updated section 2.15: PCIe Native Mode by updating the descriptions and adding registers to the PCIe Native Mode table. Added section 2.16: Hardware Monitor. Added section 2.17: Cir Interrupt Config. Added section 2.
