Service manual

IC32. Pre-sets VR10 and VR13 provides CMR adjustment and capacitors C77, C78, C81, C82,

C96, C97, C98 and C99 provide additional high frequency filtering; C83, C84, C100 and C101

provide AC coupling. The inserts are selected in or out by switches SW7 and SW8.

Post insert signals are fed to the VCA circuits formed by amplifier IC30 and VCAs IC29 and

ICE. The VCAs provide gain control and mute functions for the matrix output. Distortion is

trimmed to a minimum by pre-sets VR11 and VR14. Control voltages are provided from faders

RV38, RV39, CMOS switch IC38 and amplifier IC39. Pre-sets VR4 and VR16 set the nominal

VCA gains to +10dB.

Control of the VCA mute functions is achieved via invertor IC40 which forms two bi-stable flip

flops triggered from switches SW11 and SW12 in conjunction with capacitors C131 and 133. The

flip flop outputs are fed to the CMOS switch IC38 which replaces the fader control voltages with

a fixed DC level when the mute is active. The mutes can also be activated via the mute all line via

resistor R201 and from the automation system via R2076 and R212.

The VCA outputs connect to differential output amplifiers IC31 and IC35. Output symmetry is

adjusted by pre-sets VR12, and VR15 while high frequency stability into any load is assured by

filter capacitors C90, C91, C92, C94, C107, C108, C109 and C111. Further filtering is achieved

by T filters in the console frame and AC coupling is via C89, C93, C106 and C110.

The matrix signals can be sent to the solo busses via CMOS switch IC37 which is controlled by

NAND gates IC34 and IC36. Sections A and C of the NAND gates form two bi-stable flip flops

which are triggered by switches SW9 and SW10 in conjunction with capacitor C116 and C120.

When one of the solos is first enabled capacitor C114 or C118 create a negative going pulse

which is inverted and buffered by section B of the appropriate NAND gate. This will clear any

other solos but is prevented from self clearing by the logic low charge held on C116 or C120;

once this capacitor has charged to a logic high the solo can be cleared by the solo clear bus via

section D of the NAND gate. If the solo switch is held down capacitor C113 or C117 dis-charges

and resets the flip flop; the solo is now held on by diode D38 or D43 until the switch is released.

The stereo aux summing amplifier IC4 is referenced to a clean 0VA or noise reference which is

sent from the master module to minimise crosstalk and mains born interference. Capacitors C11

and C19 provide AC coupling and capacitor/resistor networks C10, C18, R18 and R23 ensure

maximum stability and high frequency rejection at all gains.

Stereo aux bus inject signals are fed via T filters in the frame to differential amplifiers IC1 and

IC6. Pre-sets VR1 and VR3 provide CMR adjustment and capacitors C1, C2, C3, C4, C22, C23,

C24 and C25 provide additional high frequency filtering. C5, C6, C26 and C27 provide AC

coupling.

The stereo aux bus signals can be fed directly into the matrix busses from the output of amplifiers

IC1 and IC6 via switch SW2. This does not effect the remaining parts of the stereo aux section

which continue to function as normal. Signal levels are controlled by potentiometer RV1 and

10dB amplifier IC3 whilst the mute function is performed by switch SW1.

The stereo aux outputs are driven from differential output amplifiers IC2 and IC7. Output symme-

try is adjusted by pre-sets VR2 and VR5 while high frequency stability into any load is assured by

filter capacitors C13, C14, C15, C17 ,C32, C33, C34 and C36. Further filtering is achieved by T

filters in the console frame and AC coupling is via C12, C16, C31 and C35.